18d7e7a98SRuslan Bukin /*- 2b51092c7SRuslan Bukin * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 38d7e7a98SRuslan Bukin * All rights reserved. 48d7e7a98SRuslan Bukin * 58d7e7a98SRuslan Bukin * Portions of this software were developed by SRI International and the 68d7e7a98SRuslan Bukin * University of Cambridge Computer Laboratory under DARPA/AFRL contract 78d7e7a98SRuslan Bukin * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 88d7e7a98SRuslan Bukin * 98d7e7a98SRuslan Bukin * Portions of this software were developed by the University of Cambridge 108d7e7a98SRuslan Bukin * Computer Laboratory as part of the CTSRD Project, with support from the 118d7e7a98SRuslan Bukin * UK Higher Education Innovation Fund (HEIF). 128d7e7a98SRuslan Bukin * 138d7e7a98SRuslan Bukin * Redistribution and use in source and binary forms, with or without 148d7e7a98SRuslan Bukin * modification, are permitted provided that the following conditions 158d7e7a98SRuslan Bukin * are met: 168d7e7a98SRuslan Bukin * 1. Redistributions of source code must retain the above copyright 178d7e7a98SRuslan Bukin * notice, this list of conditions and the following disclaimer. 188d7e7a98SRuslan Bukin * 2. Redistributions in binary form must reproduce the above copyright 198d7e7a98SRuslan Bukin * notice, this list of conditions and the following disclaimer in the 208d7e7a98SRuslan Bukin * documentation and/or other materials provided with the distribution. 218d7e7a98SRuslan Bukin * 228d7e7a98SRuslan Bukin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 238d7e7a98SRuslan Bukin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 248d7e7a98SRuslan Bukin * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 258d7e7a98SRuslan Bukin * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 268d7e7a98SRuslan Bukin * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 278d7e7a98SRuslan Bukin * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 288d7e7a98SRuslan Bukin * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 298d7e7a98SRuslan Bukin * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 308d7e7a98SRuslan Bukin * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 318d7e7a98SRuslan Bukin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 328d7e7a98SRuslan Bukin * SUCH DAMAGE. 338d7e7a98SRuslan Bukin * 348d7e7a98SRuslan Bukin * $FreeBSD$ 358d7e7a98SRuslan Bukin */ 368d7e7a98SRuslan Bukin 378d7e7a98SRuslan Bukin #ifndef _MACHINE_CPU_H_ 388d7e7a98SRuslan Bukin #define _MACHINE_CPU_H_ 398d7e7a98SRuslan Bukin 408d7e7a98SRuslan Bukin #include <machine/atomic.h> 418d7e7a98SRuslan Bukin #include <machine/frame.h> 428d7e7a98SRuslan Bukin 438d7e7a98SRuslan Bukin #define TRAPF_PC(tfp) ((tfp)->tf_ra) 44b51092c7SRuslan Bukin #define TRAPF_USERMODE(tfp) (((tfp)->tf_sstatus & SSTATUS_SPP) == 0) 458d7e7a98SRuslan Bukin 468d7e7a98SRuslan Bukin #define cpu_getstack(td) ((td)->td_frame->tf_sp) 478d7e7a98SRuslan Bukin #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 488d7e7a98SRuslan Bukin #define cpu_spinwait() /* nothing */ 49*4cbbb748SJohn Baldwin #define cpu_lock_delay() DELAY(1) 508d7e7a98SRuslan Bukin 518d7e7a98SRuslan Bukin #ifdef _KERNEL 528d7e7a98SRuslan Bukin 538d7e7a98SRuslan Bukin /* 548d7e7a98SRuslan Bukin * 0x0000 CPU ID unimplemented 558d7e7a98SRuslan Bukin * 0x0001 UC Berkeley Rocket repo 568d7e7a98SRuslan Bukin * 0x00020x7FFE Reserved for open-source repos 578d7e7a98SRuslan Bukin * 0x7FFF Reserved for extension 588d7e7a98SRuslan Bukin * 0x8000 Reserved for anonymous source 598d7e7a98SRuslan Bukin * 0x80010xFFFE Reserved for proprietary implementations 608d7e7a98SRuslan Bukin * 0xFFFF Reserved for extension 618d7e7a98SRuslan Bukin */ 628d7e7a98SRuslan Bukin 638d7e7a98SRuslan Bukin #define CPU_IMPL_SHIFT 0 648d7e7a98SRuslan Bukin #define CPU_IMPL_MASK (0xffff << CPU_IMPL_SHIFT) 658d7e7a98SRuslan Bukin #define CPU_IMPL(mimpid) ((mimpid & CPU_IMPL_MASK) >> CPU_IMPL_SHIFT) 668d7e7a98SRuslan Bukin #define CPU_IMPL_UNIMPLEMEN 0x0 678d7e7a98SRuslan Bukin #define CPU_IMPL_UCB_ROCKET 0x1 688d7e7a98SRuslan Bukin 698d7e7a98SRuslan Bukin #define CPU_PART_SHIFT 62 708d7e7a98SRuslan Bukin #define CPU_PART_MASK (0x3ul << CPU_PART_SHIFT) 7198f50c44SRuslan Bukin #define CPU_PART(misa) ((misa & CPU_PART_MASK) >> CPU_PART_SHIFT) 7298f50c44SRuslan Bukin #define CPU_PART_RV32 0x1 7398f50c44SRuslan Bukin #define CPU_PART_RV64 0x2 7498f50c44SRuslan Bukin #define CPU_PART_RV128 0x3 758d7e7a98SRuslan Bukin 768d7e7a98SRuslan Bukin extern char btext[]; 778d7e7a98SRuslan Bukin extern char etext[]; 788d7e7a98SRuslan Bukin 798d7e7a98SRuslan Bukin void cpu_halt(void) __dead2; 808d7e7a98SRuslan Bukin void cpu_reset(void) __dead2; 818d7e7a98SRuslan Bukin void fork_trampoline(void); 828d7e7a98SRuslan Bukin void identify_cpu(void); 838d7e7a98SRuslan Bukin void swi_vm(void *v); 848d7e7a98SRuslan Bukin 858d7e7a98SRuslan Bukin static __inline uint64_t 868d7e7a98SRuslan Bukin get_cyclecount(void) 878d7e7a98SRuslan Bukin { 888d7e7a98SRuslan Bukin 898d7e7a98SRuslan Bukin /* TODO: This is bogus */ 908d7e7a98SRuslan Bukin return (1); 918d7e7a98SRuslan Bukin } 928d7e7a98SRuslan Bukin 938d7e7a98SRuslan Bukin #endif 948d7e7a98SRuslan Bukin 958d7e7a98SRuslan Bukin #endif /* !_MACHINE_CPU_H_ */ 96