1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2011 Nathan Whitehorn 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/smp.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr_machdep.h> 47 #include <machine/md_var.h> 48 #include <machine/rtas.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #ifdef POWERNV 54 #include <powerpc/powernv/opal.h> 55 #endif 56 57 #include "phyp-hvcall.h" 58 #include "pic_if.h" 59 60 #define XICP_PRIORITY 5 /* Random non-zero number */ 61 #define XICP_IPI 2 62 #define MAX_XICP_IRQS (1<<24) /* 24-bit XIRR field */ 63 64 #define XIVE_XICS_MODE_EMU 0 65 #define XIVE_XICS_MODE_EXP 1 66 67 static int xicp_probe(device_t); 68 static int xicp_attach(device_t); 69 static int xics_probe(device_t); 70 static int xics_attach(device_t); 71 72 static void xicp_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv); 73 static void xicp_dispatch(device_t, struct trapframe *); 74 static void xicp_enable(device_t, u_int, u_int, void **priv); 75 static void xicp_eoi(device_t, u_int, void *priv); 76 static void xicp_ipi(device_t, u_int); 77 static void xicp_mask(device_t, u_int, void *priv); 78 static void xicp_unmask(device_t, u_int, void *priv); 79 80 #ifdef POWERNV 81 void xicp_smp_cpu_startup(void); 82 #endif 83 84 static device_method_t xicp_methods[] = { 85 /* Device interface */ 86 DEVMETHOD(device_probe, xicp_probe), 87 DEVMETHOD(device_attach, xicp_attach), 88 89 /* PIC interface */ 90 DEVMETHOD(pic_bind, xicp_bind), 91 DEVMETHOD(pic_dispatch, xicp_dispatch), 92 DEVMETHOD(pic_enable, xicp_enable), 93 DEVMETHOD(pic_eoi, xicp_eoi), 94 DEVMETHOD(pic_ipi, xicp_ipi), 95 DEVMETHOD(pic_mask, xicp_mask), 96 DEVMETHOD(pic_unmask, xicp_unmask), 97 98 DEVMETHOD_END 99 }; 100 101 static device_method_t xics_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, xics_probe), 104 DEVMETHOD(device_attach, xics_attach), 105 106 DEVMETHOD_END 107 }; 108 109 struct xicp_intvec { 110 int irq; 111 int vector; 112 int cpu; 113 }; 114 115 struct xicp_softc { 116 struct mtx sc_mtx; 117 struct resource *mem[MAXCPU]; 118 119 int cpu_range[2]; 120 121 int ibm_int_on; 122 int ibm_int_off; 123 int ibm_get_xive; 124 int ibm_set_xive; 125 126 /* XXX: inefficient -- hash table? tree? */ 127 struct xicp_intvec intvecs[256]; 128 int nintvecs; 129 int ipi_vec; 130 bool xics_emu; 131 }; 132 133 static driver_t xicp_driver = { 134 "xicp", 135 xicp_methods, 136 sizeof(struct xicp_softc) 137 }; 138 139 static driver_t xics_driver = { 140 "xics", 141 xics_methods, 142 0 143 }; 144 145 #ifdef POWERNV 146 /* We can only pass physical addresses into OPAL. Kernel stacks are in the KVA, 147 * not in the direct map, so we need to somehow extract the physical address. 148 * However, pmap_kextract() takes locks, which is forbidden in a critical region 149 * (which PIC_DISPATCH() operates in). The kernel is mapped into the Direct 150 * Map (0xc000....), and the CPU implicitly drops the top two bits when doing 151 * real address by nature that the bus width is smaller than 64-bits. Placing 152 * cpu_xirr into the DMAP lets us take advantage of this and avoids the 153 * pmap_kextract() that would otherwise be needed if using the stack variable. 154 */ 155 static uint32_t cpu_xirr[MAXCPU]; 156 #endif 157 158 static devclass_t xicp_devclass; 159 static devclass_t xics_devclass; 160 161 EARLY_DRIVER_MODULE(xicp, ofwbus, xicp_driver, xicp_devclass, 0, 0, 162 BUS_PASS_INTERRUPT-1); 163 EARLY_DRIVER_MODULE(xics, ofwbus, xics_driver, xics_devclass, 0, 0, 164 BUS_PASS_INTERRUPT); 165 166 #ifdef POWERNV 167 static struct resource * 168 xicp_mem_for_cpu(int cpu) 169 { 170 device_t dev; 171 struct xicp_softc *sc; 172 int i; 173 174 for (i = 0; (dev = devclass_get_device(xicp_devclass, i)) != NULL; i++){ 175 sc = device_get_softc(dev); 176 if (cpu >= sc->cpu_range[0] && cpu < sc->cpu_range[1]) 177 return (sc->mem[cpu - sc->cpu_range[0]]); 178 } 179 180 return (NULL); 181 } 182 #endif 183 184 static int 185 xicp_probe(device_t dev) 186 { 187 188 if (!ofw_bus_is_compatible(dev, "ibm,ppc-xicp") && 189 !ofw_bus_is_compatible(dev, "ibm,opal-intc")) 190 return (ENXIO); 191 192 device_set_desc(dev, "External Interrupt Presentation Controller"); 193 return (BUS_PROBE_GENERIC); 194 } 195 196 static int 197 xics_probe(device_t dev) 198 { 199 200 if (!ofw_bus_is_compatible(dev, "ibm,ppc-xics") && 201 !ofw_bus_is_compatible(dev, "IBM,opal-xics")) 202 return (ENXIO); 203 204 device_set_desc(dev, "External Interrupt Source Controller"); 205 return (BUS_PROBE_GENERIC); 206 } 207 208 static int 209 xicp_attach(device_t dev) 210 { 211 struct xicp_softc *sc = device_get_softc(dev); 212 phandle_t phandle = ofw_bus_get_node(dev); 213 214 if (rtas_exists()) { 215 sc->ibm_int_on = rtas_token_lookup("ibm,int-on"); 216 sc->ibm_int_off = rtas_token_lookup("ibm,int-off"); 217 sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive"); 218 sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive"); 219 #ifdef POWERNV 220 } else if (opal_check() == 0) { 221 /* No init needed */ 222 #endif 223 } else { 224 device_printf(dev, "Cannot attach without RTAS or OPAL\n"); 225 return (ENXIO); 226 } 227 228 if (OF_hasprop(phandle, "ibm,interrupt-server-ranges")) { 229 OF_getencprop(phandle, "ibm,interrupt-server-ranges", 230 sc->cpu_range, sizeof(sc->cpu_range)); 231 sc->cpu_range[1] += sc->cpu_range[0]; 232 device_printf(dev, "Handling CPUs %d-%d\n", sc->cpu_range[0], 233 sc->cpu_range[1]-1); 234 #ifdef POWERNV 235 } else if (ofw_bus_is_compatible(dev, "ibm,opal-intc")) { 236 /* 237 * For now run POWER9 XIVE interrupt controller in XICS 238 * compatibility mode. 239 */ 240 sc->xics_emu = true; 241 opal_call(OPAL_XIVE_RESET, XIVE_XICS_MODE_EMU); 242 #endif 243 } else { 244 sc->cpu_range[0] = 0; 245 sc->cpu_range[1] = mp_ncpus; 246 } 247 248 #ifdef POWERNV 249 if (mfmsr() & PSL_HV) { 250 int i; 251 252 if (sc->xics_emu) { 253 opal_call(OPAL_INT_SET_CPPR, 0xff); 254 for (i = 0; i < mp_ncpus; i++) { 255 opal_call(OPAL_INT_SET_MFRR, 256 pcpu_find(i)->pc_hwref, 0xff); 257 } 258 } else { 259 for (i = 0; i < sc->cpu_range[1] - sc->cpu_range[0]; i++) { 260 sc->mem[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 261 &i, RF_ACTIVE); 262 if (sc->mem[i] == NULL) { 263 device_printf(dev, "Could not alloc mem " 264 "resource %d\n", i); 265 return (ENXIO); 266 } 267 268 /* Unmask interrupts on all cores */ 269 bus_write_1(sc->mem[i], 4, 0xff); 270 bus_write_1(sc->mem[i], 12, 0xff); 271 } 272 } 273 } 274 #endif 275 276 mtx_init(&sc->sc_mtx, "XICP", NULL, MTX_DEF); 277 sc->nintvecs = 0; 278 279 powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XICP_IRQS, 280 1 /* Number of IPIs */, FALSE); 281 root_pic = dev; 282 283 return (0); 284 } 285 286 static int 287 xics_attach(device_t dev) 288 { 289 phandle_t phandle = ofw_bus_get_node(dev); 290 291 /* The XICP (root PIC) will handle all our interrupts */ 292 powerpc_register_pic(root_pic, OF_xref_from_node(phandle), 293 MAX_XICP_IRQS, 1 /* Number of IPIs */, FALSE); 294 295 return (0); 296 } 297 298 static __inline struct xicp_intvec * 299 xicp_setup_priv(struct xicp_softc *sc, u_int irq, void **priv) 300 { 301 if (*priv == NULL) { 302 KASSERT(sc->nintvecs + 1 < nitems(sc->intvecs), 303 ("Too many XICP interrupts")); 304 mtx_lock(&sc->sc_mtx); 305 *priv = &sc->intvecs[sc->nintvecs++]; 306 mtx_unlock(&sc->sc_mtx); 307 } 308 309 return (*priv); 310 } 311 312 /* 313 * PIC I/F methods. 314 */ 315 316 static void 317 xicp_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv) 318 { 319 struct xicp_softc *sc = device_get_softc(dev); 320 struct xicp_intvec *iv; 321 cell_t status, cpu; 322 int ncpus, i, error; 323 324 /* Ignore IPIs */ 325 if (irq == MAX_XICP_IRQS) 326 return; 327 328 iv = xicp_setup_priv(sc, irq, priv); 329 330 /* 331 * This doesn't appear to actually support affinity groups, so pick a 332 * random CPU. 333 */ 334 ncpus = 0; 335 CPU_FOREACH(cpu) 336 if (CPU_ISSET(cpu, &cpumask)) ncpus++; 337 338 i = mftb() % ncpus; 339 ncpus = 0; 340 CPU_FOREACH(cpu) { 341 if (!CPU_ISSET(cpu, &cpumask)) 342 continue; 343 if (ncpus == i) 344 break; 345 ncpus++; 346 } 347 348 cpu = pcpu_find(cpu)->pc_hwref; 349 iv->cpu = cpu; 350 351 if (rtas_exists()) 352 error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu, 353 XICP_PRIORITY, &status); 354 #ifdef POWERNV 355 else 356 error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY); 357 #endif 358 359 if (error < 0) 360 panic("Cannot bind interrupt %d to CPU %d", irq, cpu); 361 } 362 363 static void 364 xicp_dispatch(device_t dev, struct trapframe *tf) 365 { 366 struct xicp_softc *sc; 367 struct resource *regs = NULL; 368 uint64_t xirr, junk; 369 int i; 370 371 sc = device_get_softc(dev); 372 #ifdef POWERNV 373 if ((mfmsr() & PSL_HV) && !sc->xics_emu) { 374 regs = xicp_mem_for_cpu(PCPU_GET(hwref)); 375 KASSERT(regs != NULL, 376 ("Can't find regs for CPU %ld", (uintptr_t)PCPU_GET(hwref))); 377 } 378 #endif 379 380 for (;;) { 381 /* Return value in R4, use the PFT call */ 382 if (regs) { 383 xirr = bus_read_4(regs, 4); 384 #ifdef POWERNV 385 } else if (sc->xics_emu) { 386 opal_call(OPAL_INT_GET_XIRR, &cpu_xirr[PCPU_GET(cpuid)], 387 false); 388 xirr = cpu_xirr[PCPU_GET(cpuid)]; 389 #endif 390 } else { 391 /* Return value in R4, use the PFT call */ 392 phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk); 393 } 394 xirr &= 0x00ffffff; 395 396 if (xirr == 0) /* No more pending interrupts? */ 397 break; 398 399 if (xirr == XICP_IPI) { /* Magic number for IPIs */ 400 xirr = MAX_XICP_IRQS; /* Map to FreeBSD magic */ 401 402 /* Clear IPI */ 403 if (regs) 404 bus_write_1(regs, 12, 0xff); 405 #ifdef POWERNV 406 else if (sc->xics_emu) 407 opal_call(OPAL_INT_SET_MFRR, 408 PCPU_GET(hwref), 0xff); 409 #endif 410 else 411 phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(hwref)), 412 0xff); 413 i = sc->ipi_vec; 414 } else { 415 416 /* XXX: super inefficient */ 417 for (i = 0; i < sc->nintvecs; i++) { 418 if (sc->intvecs[i].irq == xirr) 419 break; 420 } 421 KASSERT(i < sc->nintvecs, ("Unmapped XIRR")); 422 } 423 424 powerpc_dispatch_intr(sc->intvecs[i].vector, tf); 425 } 426 } 427 428 static void 429 xicp_enable(device_t dev, u_int irq, u_int vector, void **priv) 430 { 431 struct xicp_softc *sc; 432 struct xicp_intvec *intr; 433 cell_t status, cpu; 434 435 sc = device_get_softc(dev); 436 437 /* Bind to this CPU to start: distrib. ID is last entry in gserver# */ 438 cpu = PCPU_GET(hwref); 439 440 intr = xicp_setup_priv(sc, irq, priv); 441 442 intr->irq = irq; 443 intr->vector = vector; 444 intr->cpu = cpu; 445 mb(); 446 447 /* IPIs are also enabled. Stash off the vector index */ 448 if (irq == MAX_XICP_IRQS) { 449 sc->ipi_vec = intr - sc->intvecs; 450 return; 451 } 452 453 if (rtas_exists()) { 454 rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu, 455 XICP_PRIORITY, &status); 456 xicp_unmask(dev, irq, intr); 457 #ifdef POWERNV 458 } else { 459 status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY); 460 /* Unmask implicit for OPAL */ 461 462 if (status != 0) 463 panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq, 464 cpu, status); 465 #endif 466 } 467 } 468 469 static void 470 xicp_eoi(device_t dev, u_int irq, void *priv) 471 { 472 #ifdef POWERNV 473 struct xicp_softc *sc; 474 #endif 475 uint64_t xirr; 476 477 if (irq == MAX_XICP_IRQS) /* Remap IPI interrupt to internal value */ 478 irq = XICP_IPI; 479 xirr = irq | (0xff << 24); 480 481 #ifdef POWERNV 482 if (mfmsr() & PSL_HV) { 483 sc = device_get_softc(dev); 484 if (sc->xics_emu) 485 opal_call(OPAL_INT_EOI, xirr); 486 else 487 bus_write_4(xicp_mem_for_cpu(PCPU_GET(hwref)), 4, xirr); 488 } else 489 #endif 490 phyp_hcall(H_EOI, xirr); 491 } 492 493 static void 494 xicp_ipi(device_t dev, u_int cpu) 495 { 496 497 #ifdef POWERNV 498 struct xicp_softc *sc; 499 cpu = pcpu_find(cpu)->pc_hwref; 500 501 if (mfmsr() & PSL_HV) { 502 sc = device_get_softc(dev); 503 if (sc->xics_emu) { 504 int64_t rv; 505 rv = opal_call(OPAL_INT_SET_MFRR, cpu, XICP_PRIORITY); 506 if (rv != 0) 507 device_printf(dev, "IPI SET_MFRR result: %ld\n", rv); 508 } else 509 bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY); 510 } else 511 #endif 512 phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY); 513 } 514 515 static void 516 xicp_mask(device_t dev, u_int irq, void *priv) 517 { 518 struct xicp_softc *sc = device_get_softc(dev); 519 cell_t status; 520 521 if (irq == MAX_XICP_IRQS) 522 return; 523 524 if (rtas_exists()) { 525 rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status); 526 #ifdef POWERNV 527 } else { 528 struct xicp_intvec *ivec = priv; 529 530 KASSERT(ivec != NULL, ("Masking unconfigured interrupt")); 531 opal_call(OPAL_SET_XIVE, irq, ivec->cpu << 2, 0xff); 532 #endif 533 } 534 } 535 536 static void 537 xicp_unmask(device_t dev, u_int irq, void *priv) 538 { 539 struct xicp_softc *sc = device_get_softc(dev); 540 cell_t status; 541 542 if (irq == MAX_XICP_IRQS) 543 return; 544 545 if (rtas_exists()) { 546 rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status); 547 #ifdef POWERNV 548 } else { 549 struct xicp_intvec *ivec = priv; 550 551 KASSERT(ivec != NULL, ("Unmasking unconfigured interrupt")); 552 opal_call(OPAL_SET_XIVE, irq, ivec->cpu << 2, XICP_PRIORITY); 553 #endif 554 } 555 } 556 557 #ifdef POWERNV 558 /* This is only used on POWER9 systems with the XIVE's XICS emulation. */ 559 void 560 xicp_smp_cpu_startup(void) 561 { 562 struct xicp_softc *sc; 563 564 if (mfmsr() & PSL_HV) { 565 sc = device_get_softc(root_pic); 566 567 if (sc->xics_emu) 568 opal_call(OPAL_INT_SET_CPPR, 0xff); 569 } 570 } 571 #endif 572