xref: /freebsd/sys/powerpc/pseries/xics.c (revision ef6da5e5c76f1a858d1aeb4a8983a73aa02be479)
17a8d25c0SNathan Whitehorn /*-
271e3c308SPedro F. Giffuni  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
371e3c308SPedro F. Giffuni  *
47a8d25c0SNathan Whitehorn  * Copyright 2011 Nathan Whitehorn
57a8d25c0SNathan Whitehorn  *
67a8d25c0SNathan Whitehorn  * Redistribution and use in source and binary forms, with or without
77a8d25c0SNathan Whitehorn  * modification, are permitted provided that the following conditions
87a8d25c0SNathan Whitehorn  * are met:
97a8d25c0SNathan Whitehorn  * 1. Redistributions of source code must retain the above copyright
107a8d25c0SNathan Whitehorn  *    notice, this list of conditions and the following disclaimer.
117a8d25c0SNathan Whitehorn  * 2. Redistributions in binary form must reproduce the above copyright
127a8d25c0SNathan Whitehorn  *    notice, this list of conditions and the following disclaimer in the
137a8d25c0SNathan Whitehorn  *    documentation and/or other materials provided with the distribution.
147a8d25c0SNathan Whitehorn  *
157a8d25c0SNathan Whitehorn  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
167a8d25c0SNathan Whitehorn  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
177a8d25c0SNathan Whitehorn  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
187a8d25c0SNathan Whitehorn  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
197a8d25c0SNathan Whitehorn  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
207a8d25c0SNathan Whitehorn  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
217a8d25c0SNathan Whitehorn  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
227a8d25c0SNathan Whitehorn  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
237a8d25c0SNathan Whitehorn  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
247a8d25c0SNathan Whitehorn  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
257a8d25c0SNathan Whitehorn  * SUCH DAMAGE.
267a8d25c0SNathan Whitehorn  */
277a8d25c0SNathan Whitehorn 
287a8d25c0SNathan Whitehorn #include <sys/cdefs.h>
297a8d25c0SNathan Whitehorn __FBSDID("$FreeBSD$");
307a8d25c0SNathan Whitehorn 
318fc8068eSWojciech Macek #include "opt_platform.h"
328fc8068eSWojciech Macek 
337a8d25c0SNathan Whitehorn #include <sys/param.h>
347a8d25c0SNathan Whitehorn #include <sys/systm.h>
357a8d25c0SNathan Whitehorn #include <sys/module.h>
367a8d25c0SNathan Whitehorn #include <sys/bus.h>
377a8d25c0SNathan Whitehorn #include <sys/conf.h>
387a8d25c0SNathan Whitehorn #include <sys/kernel.h>
397a8d25c0SNathan Whitehorn #include <sys/malloc.h>
407a8d25c0SNathan Whitehorn #include <sys/smp.h>
417a8d25c0SNathan Whitehorn 
427a8d25c0SNathan Whitehorn #include <vm/vm.h>
437a8d25c0SNathan Whitehorn #include <vm/pmap.h>
447a8d25c0SNathan Whitehorn 
457a8d25c0SNathan Whitehorn #include <machine/bus.h>
467a8d25c0SNathan Whitehorn #include <machine/intr_machdep.h>
477a8d25c0SNathan Whitehorn #include <machine/md_var.h>
487a8d25c0SNathan Whitehorn #include <machine/rtas.h>
497a8d25c0SNathan Whitehorn 
507a8d25c0SNathan Whitehorn #include <dev/ofw/ofw_bus.h>
517a8d25c0SNathan Whitehorn #include <dev/ofw/ofw_bus_subr.h>
527a8d25c0SNathan Whitehorn 
538fc8068eSWojciech Macek #ifdef POWERNV
548fc8068eSWojciech Macek #include <powerpc/powernv/opal.h>
558fc8068eSWojciech Macek #endif
568fc8068eSWojciech Macek 
577a8d25c0SNathan Whitehorn #include "phyp-hvcall.h"
587a8d25c0SNathan Whitehorn #include "pic_if.h"
597a8d25c0SNathan Whitehorn 
607a8d25c0SNathan Whitehorn #define XICP_PRIORITY	5	/* Random non-zero number */
617a8d25c0SNathan Whitehorn #define XICP_IPI	2
627a8d25c0SNathan Whitehorn #define MAX_XICP_IRQS	(1<<24)	/* 24-bit XIRR field */
637a8d25c0SNathan Whitehorn 
64*ef6da5e5SJustin Hibbits #define	XIVE_XICS_MODE_EMU	0
65*ef6da5e5SJustin Hibbits #define	XIVE_XICS_MODE_EXP	1
66*ef6da5e5SJustin Hibbits 
677a8d25c0SNathan Whitehorn static int	xicp_probe(device_t);
687a8d25c0SNathan Whitehorn static int	xicp_attach(device_t);
697a8d25c0SNathan Whitehorn static int	xics_probe(device_t);
707a8d25c0SNathan Whitehorn static int	xics_attach(device_t);
717a8d25c0SNathan Whitehorn 
727a8d25c0SNathan Whitehorn static void	xicp_bind(device_t dev, u_int irq, cpuset_t cpumask);
737a8d25c0SNathan Whitehorn static void	xicp_dispatch(device_t, struct trapframe *);
747a8d25c0SNathan Whitehorn static void	xicp_enable(device_t, u_int, u_int);
757a8d25c0SNathan Whitehorn static void	xicp_eoi(device_t, u_int);
767a8d25c0SNathan Whitehorn static void	xicp_ipi(device_t, u_int);
777a8d25c0SNathan Whitehorn static void	xicp_mask(device_t, u_int);
787a8d25c0SNathan Whitehorn static void	xicp_unmask(device_t, u_int);
797a8d25c0SNathan Whitehorn 
80*ef6da5e5SJustin Hibbits #ifdef POWERNV
81*ef6da5e5SJustin Hibbits void	xicp_smp_cpu_startup(void);
82*ef6da5e5SJustin Hibbits #endif
83*ef6da5e5SJustin Hibbits 
847a8d25c0SNathan Whitehorn static device_method_t  xicp_methods[] = {
857a8d25c0SNathan Whitehorn 	/* Device interface */
867a8d25c0SNathan Whitehorn 	DEVMETHOD(device_probe,		xicp_probe),
877a8d25c0SNathan Whitehorn 	DEVMETHOD(device_attach,	xicp_attach),
887a8d25c0SNathan Whitehorn 
897a8d25c0SNathan Whitehorn 	/* PIC interface */
907a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_bind,		xicp_bind),
917a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_dispatch,		xicp_dispatch),
927a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_enable,		xicp_enable),
937a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_eoi,		xicp_eoi),
947a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_ipi,		xicp_ipi),
957a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_mask,		xicp_mask),
967a8d25c0SNathan Whitehorn 	DEVMETHOD(pic_unmask,		xicp_unmask),
977a8d25c0SNathan Whitehorn 
988fc8068eSWojciech Macek 	DEVMETHOD_END
997a8d25c0SNathan Whitehorn };
1007a8d25c0SNathan Whitehorn 
1017a8d25c0SNathan Whitehorn static device_method_t  xics_methods[] = {
1027a8d25c0SNathan Whitehorn 	/* Device interface */
1037a8d25c0SNathan Whitehorn 	DEVMETHOD(device_probe,		xics_probe),
1047a8d25c0SNathan Whitehorn 	DEVMETHOD(device_attach,	xics_attach),
1057a8d25c0SNathan Whitehorn 
1068fc8068eSWojciech Macek 	DEVMETHOD_END
1077a8d25c0SNathan Whitehorn };
1087a8d25c0SNathan Whitehorn 
1097a8d25c0SNathan Whitehorn struct xicp_softc {
1107a8d25c0SNathan Whitehorn 	struct mtx sc_mtx;
1118fc8068eSWojciech Macek 	struct resource *mem[MAXCPU];
1128fc8068eSWojciech Macek 
1138fc8068eSWojciech Macek 	int cpu_range[2];
1147a8d25c0SNathan Whitehorn 
1157a8d25c0SNathan Whitehorn 	int ibm_int_on;
1167a8d25c0SNathan Whitehorn 	int ibm_int_off;
1177a8d25c0SNathan Whitehorn 	int ibm_get_xive;
1187a8d25c0SNathan Whitehorn 	int ibm_set_xive;
1197a8d25c0SNathan Whitehorn 
1207a8d25c0SNathan Whitehorn 	/* XXX: inefficient -- hash table? tree? */
1217a8d25c0SNathan Whitehorn 	struct {
1227a8d25c0SNathan Whitehorn 		int irq;
1237a8d25c0SNathan Whitehorn 		int vector;
1248fc8068eSWojciech Macek 		int cpu;
1257a8d25c0SNathan Whitehorn 	} intvecs[256];
1267a8d25c0SNathan Whitehorn 	int nintvecs;
127*ef6da5e5SJustin Hibbits 	bool xics_emu;
1287a8d25c0SNathan Whitehorn };
1297a8d25c0SNathan Whitehorn 
1307a8d25c0SNathan Whitehorn static driver_t xicp_driver = {
1317a8d25c0SNathan Whitehorn 	"xicp",
1327a8d25c0SNathan Whitehorn 	xicp_methods,
1337a8d25c0SNathan Whitehorn 	sizeof(struct xicp_softc)
1347a8d25c0SNathan Whitehorn };
1357a8d25c0SNathan Whitehorn 
1367a8d25c0SNathan Whitehorn static driver_t xics_driver = {
1377a8d25c0SNathan Whitehorn 	"xics",
1387a8d25c0SNathan Whitehorn 	xics_methods,
1397a8d25c0SNathan Whitehorn 	0
1407a8d25c0SNathan Whitehorn };
1417a8d25c0SNathan Whitehorn 
142*ef6da5e5SJustin Hibbits static uint32_t cpu_xirr[MAXCPU];
143*ef6da5e5SJustin Hibbits 
1447a8d25c0SNathan Whitehorn static devclass_t xicp_devclass;
1457a8d25c0SNathan Whitehorn static devclass_t xics_devclass;
1467a8d25c0SNathan Whitehorn 
14765d08437SNathan Whitehorn EARLY_DRIVER_MODULE(xicp, ofwbus, xicp_driver, xicp_devclass, 0, 0,
1487a8d25c0SNathan Whitehorn     BUS_PASS_INTERRUPT-1);
14965d08437SNathan Whitehorn EARLY_DRIVER_MODULE(xics, ofwbus, xics_driver, xics_devclass, 0, 0,
1507a8d25c0SNathan Whitehorn     BUS_PASS_INTERRUPT);
1517a8d25c0SNathan Whitehorn 
1528fc8068eSWojciech Macek #ifdef POWERNV
1538fc8068eSWojciech Macek static struct resource *
1548fc8068eSWojciech Macek xicp_mem_for_cpu(int cpu)
1558fc8068eSWojciech Macek {
1568fc8068eSWojciech Macek 	device_t dev;
1578fc8068eSWojciech Macek 	struct xicp_softc *sc;
1588fc8068eSWojciech Macek 	int i;
1598fc8068eSWojciech Macek 
1608fc8068eSWojciech Macek 	for (i = 0; (dev = devclass_get_device(xicp_devclass, i)) != NULL; i++){
1618fc8068eSWojciech Macek 		sc = device_get_softc(dev);
1628fc8068eSWojciech Macek 		if (cpu >= sc->cpu_range[0] && cpu < sc->cpu_range[1])
1638fc8068eSWojciech Macek 			return (sc->mem[cpu - sc->cpu_range[0]]);
1648fc8068eSWojciech Macek 	}
1658fc8068eSWojciech Macek 
1668fc8068eSWojciech Macek 	return (NULL);
1678fc8068eSWojciech Macek }
1688fc8068eSWojciech Macek #endif
1698fc8068eSWojciech Macek 
1707a8d25c0SNathan Whitehorn static int
1717a8d25c0SNathan Whitehorn xicp_probe(device_t dev)
1727a8d25c0SNathan Whitehorn {
1737a8d25c0SNathan Whitehorn 
174*ef6da5e5SJustin Hibbits 	if (!ofw_bus_is_compatible(dev, "ibm,ppc-xicp") &&
175*ef6da5e5SJustin Hibbits 	    !ofw_bus_is_compatible(dev, "ibm,opal-intc"))
1767a8d25c0SNathan Whitehorn 		return (ENXIO);
1777a8d25c0SNathan Whitehorn 
1788fc8068eSWojciech Macek 	device_set_desc(dev, "External Interrupt Presentation Controller");
1797a8d25c0SNathan Whitehorn 	return (BUS_PROBE_GENERIC);
1807a8d25c0SNathan Whitehorn }
1817a8d25c0SNathan Whitehorn 
1827a8d25c0SNathan Whitehorn static int
1837a8d25c0SNathan Whitehorn xics_probe(device_t dev)
1847a8d25c0SNathan Whitehorn {
1857a8d25c0SNathan Whitehorn 
186*ef6da5e5SJustin Hibbits 	if (!ofw_bus_is_compatible(dev, "ibm,ppc-xics") &&
187*ef6da5e5SJustin Hibbits 	    !ofw_bus_is_compatible(dev, "IBM,opal-xics"))
1887a8d25c0SNathan Whitehorn 		return (ENXIO);
1897a8d25c0SNathan Whitehorn 
1908fc8068eSWojciech Macek 	device_set_desc(dev, "External Interrupt Source Controller");
1917a8d25c0SNathan Whitehorn 	return (BUS_PROBE_GENERIC);
1927a8d25c0SNathan Whitehorn }
1937a8d25c0SNathan Whitehorn 
1947a8d25c0SNathan Whitehorn static int
1957a8d25c0SNathan Whitehorn xicp_attach(device_t dev)
1967a8d25c0SNathan Whitehorn {
1977a8d25c0SNathan Whitehorn 	struct xicp_softc *sc = device_get_softc(dev);
1987a8d25c0SNathan Whitehorn 	phandle_t phandle = ofw_bus_get_node(dev);
1997a8d25c0SNathan Whitehorn 
2008fc8068eSWojciech Macek 	if (rtas_exists()) {
2017a8d25c0SNathan Whitehorn 		sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
2027a8d25c0SNathan Whitehorn 		sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
2037a8d25c0SNathan Whitehorn 		sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
2047a8d25c0SNathan Whitehorn 		sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
2058fc8068eSWojciech Macek #ifdef POWERNV
2068fc8068eSWojciech Macek 	} else if (opal_check() == 0) {
2078fc8068eSWojciech Macek 		/* No init needed */
2088fc8068eSWojciech Macek #endif
2098fc8068eSWojciech Macek 	} else {
2108fc8068eSWojciech Macek 		device_printf(dev, "Cannot attach without RTAS or OPAL\n");
2118fc8068eSWojciech Macek 		return (ENXIO);
2128fc8068eSWojciech Macek 	}
2138fc8068eSWojciech Macek 
2148fc8068eSWojciech Macek 	if (OF_hasprop(phandle, "ibm,interrupt-server-ranges")) {
2158fc8068eSWojciech Macek 		OF_getencprop(phandle, "ibm,interrupt-server-ranges",
2168fc8068eSWojciech Macek 		    sc->cpu_range, sizeof(sc->cpu_range));
2178fc8068eSWojciech Macek 		sc->cpu_range[1] += sc->cpu_range[0];
2188fc8068eSWojciech Macek 		device_printf(dev, "Handling CPUs %d-%d\n", sc->cpu_range[0],
2198fc8068eSWojciech Macek 		    sc->cpu_range[1]-1);
220*ef6da5e5SJustin Hibbits #ifdef POWERNV
221*ef6da5e5SJustin Hibbits 	} else if (ofw_bus_is_compatible(dev, "ibm,opal-intc")) {
222*ef6da5e5SJustin Hibbits 			/*
223*ef6da5e5SJustin Hibbits 			 * For now run POWER9 XIVE interrupt controller in XICS
224*ef6da5e5SJustin Hibbits 			 * compatibility mode.
225*ef6da5e5SJustin Hibbits 			 */
226*ef6da5e5SJustin Hibbits 			sc->xics_emu = true;
227*ef6da5e5SJustin Hibbits 			opal_call(OPAL_XIVE_RESET, XIVE_XICS_MODE_EMU);
228*ef6da5e5SJustin Hibbits #endif
2298fc8068eSWojciech Macek 	} else {
2308fc8068eSWojciech Macek 		sc->cpu_range[0] = 0;
2318fc8068eSWojciech Macek 		sc->cpu_range[1] = mp_ncpus;
2328fc8068eSWojciech Macek 	}
2338fc8068eSWojciech Macek 
2348fc8068eSWojciech Macek #ifdef POWERNV
2358fc8068eSWojciech Macek 	if (mfmsr() & PSL_HV) {
2368fc8068eSWojciech Macek 		int i;
2378fc8068eSWojciech Macek 
238*ef6da5e5SJustin Hibbits 		if (sc->xics_emu) {
239*ef6da5e5SJustin Hibbits 			opal_call(OPAL_INT_SET_CPPR, 0xff);
240*ef6da5e5SJustin Hibbits 			for (i = 0; i < mp_ncpus; i++) {
241*ef6da5e5SJustin Hibbits 				opal_call(OPAL_INT_SET_MFRR,
242*ef6da5e5SJustin Hibbits 				    pcpu_find(i)->pc_hwref, 0xff);
243*ef6da5e5SJustin Hibbits 			}
244*ef6da5e5SJustin Hibbits 		} else {
2458fc8068eSWojciech Macek 			for (i = 0; i < sc->cpu_range[1] - sc->cpu_range[0]; i++) {
2468fc8068eSWojciech Macek 				sc->mem[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2478fc8068eSWojciech Macek 				    &i, RF_ACTIVE);
2488fc8068eSWojciech Macek 				if (sc->mem[i] == NULL) {
2498fc8068eSWojciech Macek 					device_printf(dev, "Could not alloc mem "
2508fc8068eSWojciech Macek 					    "resource %d\n", i);
2518fc8068eSWojciech Macek 					return (ENXIO);
2528fc8068eSWojciech Macek 				}
2538fc8068eSWojciech Macek 
2548fc8068eSWojciech Macek 				/* Unmask interrupts on all cores */
2558fc8068eSWojciech Macek 				bus_write_1(sc->mem[i], 4, 0xff);
2568fc8068eSWojciech Macek 				bus_write_1(sc->mem[i], 12, 0xff);
2578fc8068eSWojciech Macek 			}
2588fc8068eSWojciech Macek 		}
259*ef6da5e5SJustin Hibbits 	}
2608fc8068eSWojciech Macek #endif
2618fc8068eSWojciech Macek 
2628fc8068eSWojciech Macek 	mtx_init(&sc->sc_mtx, "XICP", NULL, MTX_DEF);
2638fc8068eSWojciech Macek 	sc->nintvecs = 0;
2647a8d25c0SNathan Whitehorn 
26544d29d47SNathan Whitehorn 	powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XICP_IRQS,
2667a8d25c0SNathan Whitehorn 	    1 /* Number of IPIs */, FALSE);
2677a8d25c0SNathan Whitehorn 	root_pic = dev;
2687a8d25c0SNathan Whitehorn 
2697a8d25c0SNathan Whitehorn 	return (0);
2707a8d25c0SNathan Whitehorn }
2717a8d25c0SNathan Whitehorn 
2727a8d25c0SNathan Whitehorn static int
2737a8d25c0SNathan Whitehorn xics_attach(device_t dev)
2747a8d25c0SNathan Whitehorn {
2757a8d25c0SNathan Whitehorn 	phandle_t phandle = ofw_bus_get_node(dev);
2767a8d25c0SNathan Whitehorn 
2777a8d25c0SNathan Whitehorn 	/* The XICP (root PIC) will handle all our interrupts */
27844d29d47SNathan Whitehorn 	powerpc_register_pic(root_pic, OF_xref_from_node(phandle),
27944d29d47SNathan Whitehorn 	    MAX_XICP_IRQS, 1 /* Number of IPIs */, FALSE);
2807a8d25c0SNathan Whitehorn 
2817a8d25c0SNathan Whitehorn 	return (0);
2827a8d25c0SNathan Whitehorn }
2837a8d25c0SNathan Whitehorn 
2847a8d25c0SNathan Whitehorn /*
2857a8d25c0SNathan Whitehorn  * PIC I/F methods.
2867a8d25c0SNathan Whitehorn  */
2877a8d25c0SNathan Whitehorn 
2887a8d25c0SNathan Whitehorn static void
2897a8d25c0SNathan Whitehorn xicp_bind(device_t dev, u_int irq, cpuset_t cpumask)
2907a8d25c0SNathan Whitehorn {
2917a8d25c0SNathan Whitehorn 	struct xicp_softc *sc = device_get_softc(dev);
2927a8d25c0SNathan Whitehorn 	cell_t status, cpu;
293a4c6f6e5SNathan Whitehorn 	int ncpus, i, error;
2947a8d25c0SNathan Whitehorn 
295f0393bbfSWojciech Macek 	/* Ignore IPIs */
296f0393bbfSWojciech Macek 	if (irq == MAX_XICP_IRQS)
297f0393bbfSWojciech Macek 		return;
298f0393bbfSWojciech Macek 
2997a8d25c0SNathan Whitehorn 	/*
3000174acd4SNathan Whitehorn 	 * This doesn't appear to actually support affinity groups, so pick a
3010174acd4SNathan Whitehorn 	 * random CPU.
3027a8d25c0SNathan Whitehorn 	 */
303a4c6f6e5SNathan Whitehorn 	ncpus = 0;
3047a8d25c0SNathan Whitehorn 	CPU_FOREACH(cpu)
3050174acd4SNathan Whitehorn 		if (CPU_ISSET(cpu, &cpumask)) ncpus++;
3060174acd4SNathan Whitehorn 
3070174acd4SNathan Whitehorn 	i = mftb() % ncpus;
3080174acd4SNathan Whitehorn 	ncpus = 0;
3090174acd4SNathan Whitehorn 	CPU_FOREACH(cpu) {
3100174acd4SNathan Whitehorn 		if (!CPU_ISSET(cpu, &cpumask))
3110174acd4SNathan Whitehorn 			continue;
3120174acd4SNathan Whitehorn 		if (ncpus == i)
3130174acd4SNathan Whitehorn 			break;
3140174acd4SNathan Whitehorn 		ncpus++;
3150174acd4SNathan Whitehorn 	}
3160174acd4SNathan Whitehorn 
317f0393bbfSWojciech Macek 	cpu = pcpu_find(cpu)->pc_hwref;
318f0393bbfSWojciech Macek 
3198fc8068eSWojciech Macek 	/* XXX: super inefficient */
3208fc8068eSWojciech Macek 	for (i = 0; i < sc->nintvecs; i++) {
3218fc8068eSWojciech Macek 		if (sc->intvecs[i].irq == irq) {
3228fc8068eSWojciech Macek 			sc->intvecs[i].cpu = cpu;
3238fc8068eSWojciech Macek 			break;
3248fc8068eSWojciech Macek 		}
3258fc8068eSWojciech Macek 	}
3268fc8068eSWojciech Macek 	KASSERT(i < sc->nintvecs, ("Binding non-configured interrupt"));
3277a8d25c0SNathan Whitehorn 
3288fc8068eSWojciech Macek 	if (rtas_exists())
329a4c6f6e5SNathan Whitehorn 		error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
330a4c6f6e5SNathan Whitehorn 		    XICP_PRIORITY, &status);
3318fc8068eSWojciech Macek #ifdef POWERNV
3328fc8068eSWojciech Macek 	else
3338fc8068eSWojciech Macek 		error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
3348fc8068eSWojciech Macek #endif
3358fc8068eSWojciech Macek 
336a4c6f6e5SNathan Whitehorn 	if (error < 0)
337a4c6f6e5SNathan Whitehorn 		panic("Cannot bind interrupt %d to CPU %d", irq, cpu);
3387a8d25c0SNathan Whitehorn }
3397a8d25c0SNathan Whitehorn 
3407a8d25c0SNathan Whitehorn static void
3417a8d25c0SNathan Whitehorn xicp_dispatch(device_t dev, struct trapframe *tf)
3427a8d25c0SNathan Whitehorn {
3437a8d25c0SNathan Whitehorn 	struct xicp_softc *sc;
3448fc8068eSWojciech Macek 	struct resource *regs = NULL;
3457a8d25c0SNathan Whitehorn 	uint64_t xirr, junk;
3467a8d25c0SNathan Whitehorn 	int i;
3477a8d25c0SNathan Whitehorn 
348*ef6da5e5SJustin Hibbits 	sc = device_get_softc(dev);
3498fc8068eSWojciech Macek #ifdef POWERNV
350*ef6da5e5SJustin Hibbits 	if ((mfmsr() & PSL_HV) && !sc->xics_emu) {
351f0393bbfSWojciech Macek 		regs = xicp_mem_for_cpu(PCPU_GET(hwref));
3528fc8068eSWojciech Macek 		KASSERT(regs != NULL,
353f0393bbfSWojciech Macek 		    ("Can't find regs for CPU %ld", (uintptr_t)PCPU_GET(hwref)));
3548fc8068eSWojciech Macek 	}
3558fc8068eSWojciech Macek #endif
3568fc8068eSWojciech Macek 
3577a8d25c0SNathan Whitehorn 	for (;;) {
3587a8d25c0SNathan Whitehorn 		/* Return value in R4, use the PFT call */
3598fc8068eSWojciech Macek 		if (regs) {
3608fc8068eSWojciech Macek 			xirr = bus_read_4(regs, 4);
361*ef6da5e5SJustin Hibbits #ifdef POWERNV
362*ef6da5e5SJustin Hibbits 		} else if (sc->xics_emu) {
363*ef6da5e5SJustin Hibbits 			opal_call(OPAL_INT_GET_XIRR, &cpu_xirr[PCPU_GET(cpuid)],
364*ef6da5e5SJustin Hibbits 			    false);
365*ef6da5e5SJustin Hibbits 			xirr = cpu_xirr[PCPU_GET(cpuid)];
366*ef6da5e5SJustin Hibbits #endif
3678fc8068eSWojciech Macek 		} else {
3688fc8068eSWojciech Macek 			/* Return value in R4, use the PFT call */
3697a8d25c0SNathan Whitehorn 			phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
3708fc8068eSWojciech Macek 		}
3717a8d25c0SNathan Whitehorn 		xirr &= 0x00ffffff;
3727a8d25c0SNathan Whitehorn 
3737a8d25c0SNathan Whitehorn 		if (xirr == 0) { /* No more pending interrupts? */
3748fc8068eSWojciech Macek 			if (regs)
3758fc8068eSWojciech Macek 				bus_write_1(regs, 4, 0xff);
376*ef6da5e5SJustin Hibbits #ifdef POWERNV
377*ef6da5e5SJustin Hibbits 			else if (sc->xics_emu)
378*ef6da5e5SJustin Hibbits 				opal_call(OPAL_INT_SET_CPPR, 0xff);
379*ef6da5e5SJustin Hibbits #endif
3808fc8068eSWojciech Macek 			else
3817a8d25c0SNathan Whitehorn 				phyp_hcall(H_CPPR, (uint64_t)0xff);
3827a8d25c0SNathan Whitehorn 			break;
3837a8d25c0SNathan Whitehorn 		}
3847a8d25c0SNathan Whitehorn 		if (xirr == XICP_IPI) {		/* Magic number for IPIs */
3857a8d25c0SNathan Whitehorn 			xirr = MAX_XICP_IRQS;	/* Map to FreeBSD magic */
3868fc8068eSWojciech Macek 
3878fc8068eSWojciech Macek 			/* Clear IPI */
3888fc8068eSWojciech Macek 			if (regs)
3898fc8068eSWojciech Macek 				bus_write_1(regs, 12, 0xff);
390*ef6da5e5SJustin Hibbits #ifdef POWERNV
391*ef6da5e5SJustin Hibbits 			else if (sc->xics_emu)
392*ef6da5e5SJustin Hibbits 				opal_call(OPAL_INT_SET_MFRR,
393*ef6da5e5SJustin Hibbits 				    PCPU_GET(hwref), 0xff);
394*ef6da5e5SJustin Hibbits #endif
3958fc8068eSWojciech Macek 			else
396f0393bbfSWojciech Macek 				phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(hwref)),
3978fc8068eSWojciech Macek 				    0xff);
3987a8d25c0SNathan Whitehorn 		}
3997a8d25c0SNathan Whitehorn 
4007a8d25c0SNathan Whitehorn 		/* XXX: super inefficient */
4017a8d25c0SNathan Whitehorn 		for (i = 0; i < sc->nintvecs; i++) {
4027a8d25c0SNathan Whitehorn 			if (sc->intvecs[i].irq == xirr)
4037a8d25c0SNathan Whitehorn 				break;
4047a8d25c0SNathan Whitehorn 		}
4057a8d25c0SNathan Whitehorn 
4067a8d25c0SNathan Whitehorn 		KASSERT(i < sc->nintvecs, ("Unmapped XIRR"));
4077a8d25c0SNathan Whitehorn 		powerpc_dispatch_intr(sc->intvecs[i].vector, tf);
4087a8d25c0SNathan Whitehorn 	}
4097a8d25c0SNathan Whitehorn }
4107a8d25c0SNathan Whitehorn 
4117a8d25c0SNathan Whitehorn static void
4127a8d25c0SNathan Whitehorn xicp_enable(device_t dev, u_int irq, u_int vector)
4137a8d25c0SNathan Whitehorn {
4147a8d25c0SNathan Whitehorn 	struct xicp_softc *sc;
4157a8d25c0SNathan Whitehorn 	cell_t status, cpu;
4167a8d25c0SNathan Whitehorn 
4177a8d25c0SNathan Whitehorn 	sc = device_get_softc(dev);
4187a8d25c0SNathan Whitehorn 
41933495e5dSPedro F. Giffuni 	KASSERT(sc->nintvecs + 1 < nitems(sc->intvecs),
4207a8d25c0SNathan Whitehorn 		("Too many XICP interrupts"));
4217a8d25c0SNathan Whitehorn 
4228fc8068eSWojciech Macek 	/* Bind to this CPU to start: distrib. ID is last entry in gserver# */
423f0393bbfSWojciech Macek 	cpu = PCPU_GET(hwref);
4248fc8068eSWojciech Macek 
4257a8d25c0SNathan Whitehorn 	mtx_lock(&sc->sc_mtx);
4267a8d25c0SNathan Whitehorn 	sc->intvecs[sc->nintvecs].irq = irq;
4277a8d25c0SNathan Whitehorn 	sc->intvecs[sc->nintvecs].vector = vector;
4288fc8068eSWojciech Macek 	sc->intvecs[sc->nintvecs].cpu = cpu;
4297a8d25c0SNathan Whitehorn 	mb();
4307a8d25c0SNathan Whitehorn 	sc->nintvecs++;
4317a8d25c0SNathan Whitehorn 	mtx_unlock(&sc->sc_mtx);
4327a8d25c0SNathan Whitehorn 
4337a8d25c0SNathan Whitehorn 	/* IPIs are also enabled */
4347a8d25c0SNathan Whitehorn 	if (irq == MAX_XICP_IRQS)
4357a8d25c0SNathan Whitehorn 		return;
4367a8d25c0SNathan Whitehorn 
4378fc8068eSWojciech Macek 	if (rtas_exists()) {
4388fc8068eSWojciech Macek 		rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
4398fc8068eSWojciech Macek 		    XICP_PRIORITY, &status);
4407a8d25c0SNathan Whitehorn 		xicp_unmask(dev, irq);
4418fc8068eSWojciech Macek #ifdef POWERNV
4428fc8068eSWojciech Macek 	} else {
4438fc8068eSWojciech Macek 		status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
4448fc8068eSWojciech Macek 		/* Unmask implicit for OPAL */
4458fc8068eSWojciech Macek 
4468fc8068eSWojciech Macek 		if (status != 0)
4478fc8068eSWojciech Macek 			panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq,
4488fc8068eSWojciech Macek 			    cpu, status);
4498fc8068eSWojciech Macek #endif
4508fc8068eSWojciech Macek 	}
4517a8d25c0SNathan Whitehorn }
4527a8d25c0SNathan Whitehorn 
4537a8d25c0SNathan Whitehorn static void
4547a8d25c0SNathan Whitehorn xicp_eoi(device_t dev, u_int irq)
4557a8d25c0SNathan Whitehorn {
456*ef6da5e5SJustin Hibbits #ifdef POWERNV
457*ef6da5e5SJustin Hibbits 	struct xicp_softc *sc;
458*ef6da5e5SJustin Hibbits #endif
4597a8d25c0SNathan Whitehorn 	uint64_t xirr;
4607a8d25c0SNathan Whitehorn 
4617a8d25c0SNathan Whitehorn 	if (irq == MAX_XICP_IRQS) /* Remap IPI interrupt to internal value */
4627a8d25c0SNathan Whitehorn 		irq = XICP_IPI;
4637a8d25c0SNathan Whitehorn 	xirr = irq | (XICP_PRIORITY << 24);
4647a8d25c0SNathan Whitehorn 
4658fc8068eSWojciech Macek #ifdef POWERNV
466*ef6da5e5SJustin Hibbits 	if (mfmsr() & PSL_HV) {
467*ef6da5e5SJustin Hibbits 		sc = device_get_softc(dev);
468*ef6da5e5SJustin Hibbits 		if (sc->xics_emu)
469*ef6da5e5SJustin Hibbits 			opal_call(OPAL_INT_EOI, xirr);
4708fc8068eSWojciech Macek 		else
471*ef6da5e5SJustin Hibbits 			bus_write_4(xicp_mem_for_cpu(PCPU_GET(hwref)), 4, xirr);
472*ef6da5e5SJustin Hibbits 	} else
4738fc8068eSWojciech Macek #endif
4747a8d25c0SNathan Whitehorn 		phyp_hcall(H_EOI, xirr);
4757a8d25c0SNathan Whitehorn }
4767a8d25c0SNathan Whitehorn 
4777a8d25c0SNathan Whitehorn static void
4787a8d25c0SNathan Whitehorn xicp_ipi(device_t dev, u_int cpu)
4797a8d25c0SNathan Whitehorn {
4807a8d25c0SNathan Whitehorn 
4818fc8068eSWojciech Macek #ifdef POWERNV
482*ef6da5e5SJustin Hibbits 	struct xicp_softc *sc;
483f0393bbfSWojciech Macek 	cpu = pcpu_find(cpu)->pc_hwref;
484f0393bbfSWojciech Macek 
485*ef6da5e5SJustin Hibbits 	if (mfmsr() & PSL_HV) {
486*ef6da5e5SJustin Hibbits 		sc = device_get_softc(dev);
487*ef6da5e5SJustin Hibbits 		if (sc->xics_emu) {
488*ef6da5e5SJustin Hibbits 			int64_t rv;
489*ef6da5e5SJustin Hibbits 			rv = opal_call(OPAL_INT_SET_MFRR, cpu, XICP_PRIORITY);
490*ef6da5e5SJustin Hibbits 			if (rv != 0)
491*ef6da5e5SJustin Hibbits 			    device_printf(dev, "IPI SET_MFRR result: %ld\n", rv);
492*ef6da5e5SJustin Hibbits 		} else
4938fc8068eSWojciech Macek 			bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY);
494*ef6da5e5SJustin Hibbits 	} else
4958fc8068eSWojciech Macek #endif
4967a8d25c0SNathan Whitehorn 		phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
4977a8d25c0SNathan Whitehorn }
4987a8d25c0SNathan Whitehorn 
4997a8d25c0SNathan Whitehorn static void
5007a8d25c0SNathan Whitehorn xicp_mask(device_t dev, u_int irq)
5017a8d25c0SNathan Whitehorn {
5027a8d25c0SNathan Whitehorn 	struct xicp_softc *sc = device_get_softc(dev);
5037a8d25c0SNathan Whitehorn 	cell_t status;
5047a8d25c0SNathan Whitehorn 
5057a8d25c0SNathan Whitehorn 	if (irq == MAX_XICP_IRQS)
5067a8d25c0SNathan Whitehorn 		return;
5077a8d25c0SNathan Whitehorn 
5088fc8068eSWojciech Macek 	if (rtas_exists()) {
5097a8d25c0SNathan Whitehorn 		rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
5108fc8068eSWojciech Macek #ifdef POWERNV
5118fc8068eSWojciech Macek 	} else {
5128fc8068eSWojciech Macek 		int i;
5138fc8068eSWojciech Macek 
5148fc8068eSWojciech Macek 		for (i = 0; i < sc->nintvecs; i++) {
5158fc8068eSWojciech Macek 			if (sc->intvecs[i].irq == irq) {
5168fc8068eSWojciech Macek 				break;
5178fc8068eSWojciech Macek 			}
5188fc8068eSWojciech Macek 		}
5198fc8068eSWojciech Macek 		KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt"));
5208fc8068eSWojciech Macek 		opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff);
5218fc8068eSWojciech Macek #endif
5228fc8068eSWojciech Macek 	}
5237a8d25c0SNathan Whitehorn }
5247a8d25c0SNathan Whitehorn 
5257a8d25c0SNathan Whitehorn static void
5267a8d25c0SNathan Whitehorn xicp_unmask(device_t dev, u_int irq)
5277a8d25c0SNathan Whitehorn {
5287a8d25c0SNathan Whitehorn 	struct xicp_softc *sc = device_get_softc(dev);
5297a8d25c0SNathan Whitehorn 	cell_t status;
5307a8d25c0SNathan Whitehorn 
5317a8d25c0SNathan Whitehorn 	if (irq == MAX_XICP_IRQS)
5327a8d25c0SNathan Whitehorn 		return;
5337a8d25c0SNathan Whitehorn 
5348fc8068eSWojciech Macek 	if (rtas_exists()) {
5357a8d25c0SNathan Whitehorn 		rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
5368fc8068eSWojciech Macek #ifdef POWERNV
5378fc8068eSWojciech Macek 	} else {
5388fc8068eSWojciech Macek 		int i;
5398fc8068eSWojciech Macek 
5408fc8068eSWojciech Macek 		for (i = 0; i < sc->nintvecs; i++) {
5418fc8068eSWojciech Macek 			if (sc->intvecs[i].irq == irq) {
5428fc8068eSWojciech Macek 				break;
5438fc8068eSWojciech Macek 			}
5448fc8068eSWojciech Macek 		}
5458fc8068eSWojciech Macek 		KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt"));
5468fc8068eSWojciech Macek 		opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2,
5478fc8068eSWojciech Macek 		    XICP_PRIORITY);
5488fc8068eSWojciech Macek #endif
5498fc8068eSWojciech Macek 	}
5507a8d25c0SNathan Whitehorn }
5517a8d25c0SNathan Whitehorn 
552*ef6da5e5SJustin Hibbits #ifdef POWERNV
553*ef6da5e5SJustin Hibbits /* This is only used on POWER9 systems with the XIVE's XICS emulation. */
554*ef6da5e5SJustin Hibbits void
555*ef6da5e5SJustin Hibbits xicp_smp_cpu_startup(void)
556*ef6da5e5SJustin Hibbits {
557*ef6da5e5SJustin Hibbits 	struct xicp_softc *sc;
558*ef6da5e5SJustin Hibbits 
559*ef6da5e5SJustin Hibbits 	if (mfmsr() & PSL_HV) {
560*ef6da5e5SJustin Hibbits 		sc = device_get_softc(root_pic);
561*ef6da5e5SJustin Hibbits 
562*ef6da5e5SJustin Hibbits 		if (sc->xics_emu)
563*ef6da5e5SJustin Hibbits 			opal_call(OPAL_INT_SET_CPPR, 0xff);
564*ef6da5e5SJustin Hibbits 	}
565*ef6da5e5SJustin Hibbits }
566*ef6da5e5SJustin Hibbits #endif
567