1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2010 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/sockio.h> 33 #include <sys/endian.h> 34 #include <sys/lock.h> 35 #include <sys/mbuf.h> 36 #include <sys/module.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/if_dl.h> 52 53 #include <machine/pio.h> 54 #include <machine/bus.h> 55 #include <machine/platform.h> 56 #include <machine/resource.h> 57 #include <sys/bus.h> 58 #include <sys/rman.h> 59 60 #include "ps3bus.h" 61 #include "ps3-hvcall.h" 62 #include "if_glcreg.h" 63 64 static int glc_probe(device_t); 65 static int glc_attach(device_t); 66 static void glc_init(void *xsc); 67 static void glc_start(struct ifnet *ifp); 68 static int glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 69 static void glc_set_multicast(struct glc_softc *sc); 70 static int glc_add_rxbuf(struct glc_softc *sc, int idx); 71 static int glc_add_rxbuf_dma(struct glc_softc *sc, int idx); 72 static int glc_encap(struct glc_softc *sc, struct mbuf **m_head, 73 bus_addr_t *pktdesc); 74 static int glc_intr_filter(void *xsc); 75 static void glc_intr(void *xsc); 76 static void glc_tick(void *xsc); 77 static void glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr); 78 static int glc_media_change(struct ifnet *ifp); 79 80 static MALLOC_DEFINE(M_GLC, "gelic", "PS3 GELIC ethernet"); 81 82 static device_method_t glc_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_probe, glc_probe), 85 DEVMETHOD(device_attach, glc_attach), 86 { 0, 0 } 87 }; 88 89 static driver_t glc_driver = { 90 "glc", 91 glc_methods, 92 sizeof(struct glc_softc) 93 }; 94 95 static devclass_t glc_devclass; 96 97 DRIVER_MODULE(glc, ps3bus, glc_driver, glc_devclass, 0, 0); 98 99 static int 100 glc_probe(device_t dev) 101 { 102 103 if (ps3bus_get_bustype(dev) != PS3_BUSTYPE_SYSBUS || 104 ps3bus_get_devtype(dev) != PS3_DEVTYPE_GELIC) 105 return (ENXIO); 106 107 device_set_desc(dev, "Playstation 3 GELIC Network Controller"); 108 return (BUS_PROBE_SPECIFIC); 109 } 110 111 static void 112 glc_getphys(void *xaddr, bus_dma_segment_t *segs, int nsegs, int error) 113 { 114 if (error != 0) 115 return; 116 117 *(bus_addr_t *)xaddr = segs[0].ds_addr; 118 } 119 120 static int 121 glc_attach(device_t dev) 122 { 123 struct glc_softc *sc; 124 struct glc_txsoft *txs; 125 uint64_t mac64, val, junk; 126 int i, err; 127 128 sc = device_get_softc(dev); 129 130 sc->sc_bus = ps3bus_get_bus(dev); 131 sc->sc_dev = ps3bus_get_device(dev); 132 sc->sc_self = dev; 133 134 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 135 MTX_DEF); 136 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 137 sc->next_txdma_slot = 0; 138 sc->bsy_txdma_slots = 0; 139 sc->sc_next_rxdma_slot = 0; 140 sc->first_used_txdma_slot = -1; 141 142 /* 143 * Shut down existing tasks. 144 */ 145 146 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 147 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 148 149 sc->sc_ifp = if_alloc(IFT_ETHER); 150 sc->sc_ifp->if_softc = sc; 151 152 /* 153 * Get MAC address and VLAN id 154 */ 155 156 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_MAC_ADDRESS, 157 0, 0, 0, &mac64, &junk); 158 memcpy(sc->sc_enaddr, &((uint8_t *)&mac64)[2], sizeof(sc->sc_enaddr)); 159 sc->sc_tx_vlan = sc->sc_rx_vlan = -1; 160 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 161 GELIC_VLAN_TX_ETHERNET, 0, 0, &val, &junk); 162 if (err == 0) 163 sc->sc_tx_vlan = val; 164 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 165 GELIC_VLAN_RX_ETHERNET, 0, 0, &val, &junk); 166 if (err == 0) 167 sc->sc_rx_vlan = val; 168 169 /* 170 * Set up interrupt handler 171 */ 172 sc->sc_irqid = 0; 173 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqid, 174 RF_ACTIVE); 175 if (sc->sc_irq == NULL) { 176 device_printf(dev, "Could not allocate IRQ!\n"); 177 mtx_destroy(&sc->sc_mtx); 178 return (ENXIO); 179 } 180 181 bus_setup_intr(dev, sc->sc_irq, 182 INTR_TYPE_NET | INTR_MPSAFE | INTR_ENTROPY, 183 glc_intr_filter, glc_intr, sc, &sc->sc_irqctx); 184 sc->sc_hwirq_status = (uint64_t *)contigmalloc(8, M_GLC, M_ZERO, 0, 185 BUS_SPACE_MAXADDR_32BIT, 8, PAGE_SIZE); 186 lv1_net_set_interrupt_status_indicator(sc->sc_bus, sc->sc_dev, 187 vtophys(sc->sc_hwirq_status), 0); 188 lv1_net_set_interrupt_mask(sc->sc_bus, sc->sc_dev, 189 GELIC_INT_RXDONE | GELIC_INT_RXFRAME | GELIC_INT_PHY | 190 GELIC_INT_TX_CHAIN_END, 0); 191 192 /* 193 * Set up DMA. 194 */ 195 196 err = bus_dma_tag_create(bus_get_dma_tag(dev), 32, 0, 197 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 198 129*sizeof(struct glc_dmadesc), 1, 128*sizeof(struct glc_dmadesc), 199 0, NULL,NULL, &sc->sc_dmadesc_tag); 200 201 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_txdmadesc, 202 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 203 &sc->sc_txdmadesc_map); 204 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 205 sc->sc_txdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 206 &sc->sc_txdmadesc_phys, 0); 207 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_rxdmadesc, 208 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 209 &sc->sc_rxdmadesc_map); 210 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 211 sc->sc_rxdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 212 &sc->sc_rxdmadesc_phys, 0); 213 214 err = bus_dma_tag_create(bus_get_dma_tag(dev), 128, 0, 215 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 216 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 217 &sc->sc_rxdma_tag); 218 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 219 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 220 BUS_SPACE_MAXSIZE_32BIT, 16, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 221 &sc->sc_txdma_tag); 222 223 /* init transmit descriptors */ 224 STAILQ_INIT(&sc->sc_txfreeq); 225 STAILQ_INIT(&sc->sc_txdirtyq); 226 227 /* create TX DMA maps */ 228 err = ENOMEM; 229 for (i = 0; i < GLC_MAX_TX_PACKETS; i++) { 230 txs = &sc->sc_txsoft[i]; 231 txs->txs_mbuf = NULL; 232 err = bus_dmamap_create(sc->sc_txdma_tag, 0, &txs->txs_dmamap); 233 if (err) { 234 device_printf(dev, 235 "unable to create TX DMA map %d, error = %d\n", 236 i, err); 237 } 238 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 239 } 240 241 /* Create the receive buffer DMA maps. */ 242 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 243 err = bus_dmamap_create(sc->sc_rxdma_tag, 0, 244 &sc->sc_rxsoft[i].rxs_dmamap); 245 if (err) { 246 device_printf(dev, 247 "unable to create RX DMA map %d, error = %d\n", 248 i, err); 249 } 250 sc->sc_rxsoft[i].rxs_mbuf = NULL; 251 } 252 253 /* 254 * Attach to network stack 255 */ 256 257 if_initname(sc->sc_ifp, device_get_name(dev), device_get_unit(dev)); 258 sc->sc_ifp->if_mtu = ETHERMTU; 259 sc->sc_ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 sc->sc_ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 261 sc->sc_ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_RXCSUM; 262 sc->sc_ifp->if_capenable = IFCAP_HWCSUM | IFCAP_RXCSUM; 263 sc->sc_ifp->if_start = glc_start; 264 sc->sc_ifp->if_ioctl = glc_ioctl; 265 sc->sc_ifp->if_init = glc_init; 266 267 ifmedia_init(&sc->sc_media, IFM_IMASK, glc_media_change, 268 glc_media_status); 269 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 270 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 271 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 272 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 273 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 274 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 275 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 276 277 IFQ_SET_MAXLEN(&sc->sc_ifp->if_snd, GLC_MAX_TX_PACKETS); 278 sc->sc_ifp->if_snd.ifq_drv_maxlen = GLC_MAX_TX_PACKETS; 279 IFQ_SET_READY(&sc->sc_ifp->if_snd); 280 281 ether_ifattach(sc->sc_ifp, sc->sc_enaddr); 282 sc->sc_ifp->if_hwassist = 0; 283 284 return (0); 285 286 mtx_destroy(&sc->sc_mtx); 287 if_free(sc->sc_ifp); 288 return (ENXIO); 289 } 290 291 static void 292 glc_init_locked(struct glc_softc *sc) 293 { 294 int i, error; 295 struct glc_rxsoft *rxs; 296 struct glc_txsoft *txs; 297 298 mtx_assert(&sc->sc_mtx, MA_OWNED); 299 300 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 301 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 302 303 glc_set_multicast(sc); 304 305 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 306 rxs = &sc->sc_rxsoft[i]; 307 rxs->rxs_desc_slot = i; 308 309 if (rxs->rxs_mbuf == NULL) { 310 glc_add_rxbuf(sc, i); 311 312 if (rxs->rxs_mbuf == NULL) { 313 rxs->rxs_desc_slot = -1; 314 break; 315 } 316 } 317 318 glc_add_rxbuf_dma(sc, i); 319 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 320 BUS_DMASYNC_PREREAD); 321 } 322 323 /* Clear TX dirty queue */ 324 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 325 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 326 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 327 328 if (txs->txs_mbuf != NULL) { 329 m_freem(txs->txs_mbuf); 330 txs->txs_mbuf = NULL; 331 } 332 333 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 334 } 335 sc->first_used_txdma_slot = -1; 336 sc->bsy_txdma_slots = 0; 337 338 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 339 sc->sc_rxsoft[0].rxs_desc, 0); 340 if (error != 0) 341 device_printf(sc->sc_self, 342 "lv1_net_start_rx_dma error: %d\n", error); 343 344 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 345 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 346 sc->sc_ifpflags = sc->sc_ifp->if_flags; 347 348 sc->sc_wdog_timer = 0; 349 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 350 } 351 352 static void 353 glc_stop(void *xsc) 354 { 355 struct glc_softc *sc = xsc; 356 357 mtx_assert(&sc->sc_mtx, MA_OWNED); 358 359 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 360 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 361 } 362 363 static void 364 glc_init(void *xsc) 365 { 366 struct glc_softc *sc = xsc; 367 368 mtx_lock(&sc->sc_mtx); 369 glc_init_locked(sc); 370 mtx_unlock(&sc->sc_mtx); 371 } 372 373 static void 374 glc_tick(void *xsc) 375 { 376 struct glc_softc *sc = xsc; 377 378 mtx_assert(&sc->sc_mtx, MA_OWNED); 379 380 /* 381 * XXX: Sometimes the RX queue gets stuck. Poke it periodically until 382 * we figure out why. This will fail harmlessly if the RX queue is 383 * already running. 384 */ 385 lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 386 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 387 388 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 389 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 390 return; 391 } 392 393 /* Problems */ 394 device_printf(sc->sc_self, "device timeout\n"); 395 396 glc_init_locked(sc); 397 } 398 399 static void 400 glc_start_locked(struct ifnet *ifp) 401 { 402 struct glc_softc *sc = ifp->if_softc; 403 bus_addr_t first, pktdesc; 404 int kickstart = 0; 405 int error; 406 struct mbuf *mb_head; 407 408 mtx_assert(&sc->sc_mtx, MA_OWNED); 409 first = 0; 410 411 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 412 IFF_DRV_RUNNING) 413 return; 414 415 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 416 kickstart = 1; 417 418 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 419 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 420 421 if (mb_head == NULL) 422 break; 423 424 /* Check if the ring buffer is full */ 425 if (sc->bsy_txdma_slots > 125) { 426 /* Put the packet back and stop */ 427 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 428 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 429 break; 430 } 431 432 BPF_MTAP(ifp, mb_head); 433 434 if (sc->sc_tx_vlan >= 0) 435 mb_head = ether_vlanencap(mb_head, sc->sc_tx_vlan); 436 437 if (glc_encap(sc, &mb_head, &pktdesc)) { 438 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 439 break; 440 } 441 442 if (first == 0) 443 first = pktdesc; 444 } 445 446 if (kickstart && first != 0) { 447 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, first, 0); 448 if (error != 0) 449 device_printf(sc->sc_self, 450 "lv1_net_start_tx_dma error: %d\n", error); 451 sc->sc_wdog_timer = 5; 452 } 453 } 454 455 static void 456 glc_start(struct ifnet *ifp) 457 { 458 struct glc_softc *sc = ifp->if_softc; 459 460 mtx_lock(&sc->sc_mtx); 461 glc_start_locked(ifp); 462 mtx_unlock(&sc->sc_mtx); 463 } 464 465 static int 466 glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 467 { 468 struct glc_softc *sc = ifp->if_softc; 469 struct ifreq *ifr = (struct ifreq *)data; 470 int err = 0; 471 472 switch (cmd) { 473 case SIOCSIFFLAGS: 474 mtx_lock(&sc->sc_mtx); 475 if ((ifp->if_flags & IFF_UP) != 0) { 476 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 477 ((ifp->if_flags ^ sc->sc_ifpflags) & 478 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 479 glc_set_multicast(sc); 480 else 481 glc_init_locked(sc); 482 } 483 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 484 glc_stop(sc); 485 sc->sc_ifpflags = ifp->if_flags; 486 mtx_unlock(&sc->sc_mtx); 487 break; 488 case SIOCADDMULTI: 489 case SIOCDELMULTI: 490 mtx_lock(&sc->sc_mtx); 491 glc_set_multicast(sc); 492 mtx_unlock(&sc->sc_mtx); 493 break; 494 case SIOCGIFMEDIA: 495 case SIOCSIFMEDIA: 496 err = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 497 break; 498 default: 499 err = ether_ioctl(ifp, cmd, data); 500 break; 501 } 502 503 return (err); 504 } 505 506 static u_int 507 glc_add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 508 { 509 struct glc_softc *sc = arg; 510 uint64_t addr; 511 512 /* 513 * Filter can only hold 32 addresses, so fall back to 514 * the IFF_ALLMULTI case if we have too many. +1 is for 515 * broadcast. 516 */ 517 if (cnt + 1 == 32) 518 return (0); 519 520 addr = 0; 521 memcpy(&((uint8_t *)(&addr))[2], LLADDR(sdl), ETHER_ADDR_LEN); 522 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, addr, 0); 523 524 return (1); 525 } 526 527 static void 528 glc_set_multicast(struct glc_softc *sc) 529 { 530 struct ifnet *ifp = sc->sc_ifp; 531 int naddrs; 532 533 /* Clear multicast filter */ 534 lv1_net_remove_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 535 536 /* Add broadcast */ 537 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 538 0xffffffffffffL, 0); 539 540 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 541 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 542 } else { 543 naddrs = if_foreach_llmaddr(ifp, glc_add_maddr, sc); 544 if (naddrs + 1 == 32) 545 lv1_net_add_multicast_address(sc->sc_bus, 546 sc->sc_dev, 0, 1); 547 } 548 } 549 550 static int 551 glc_add_rxbuf(struct glc_softc *sc, int idx) 552 { 553 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 554 struct mbuf *m; 555 bus_dma_segment_t segs[1]; 556 int error, nsegs; 557 558 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 559 if (m == NULL) 560 return (ENOBUFS); 561 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 562 563 if (rxs->rxs_mbuf != NULL) { 564 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, 565 BUS_DMASYNC_POSTREAD); 566 bus_dmamap_unload(sc->sc_rxdma_tag, rxs->rxs_dmamap); 567 } 568 569 error = bus_dmamap_load_mbuf_sg(sc->sc_rxdma_tag, rxs->rxs_dmamap, m, 570 segs, &nsegs, BUS_DMA_NOWAIT); 571 if (error != 0) { 572 device_printf(sc->sc_self, 573 "cannot load RS DMA map %d, error = %d\n", idx, error); 574 m_freem(m); 575 return (error); 576 } 577 /* If nsegs is wrong then the stack is corrupt. */ 578 KASSERT(nsegs == 1, 579 ("%s: too many DMA segments (%d)", __func__, nsegs)); 580 rxs->rxs_mbuf = m; 581 rxs->segment = segs[0]; 582 583 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 584 585 return (0); 586 } 587 588 static int 589 glc_add_rxbuf_dma(struct glc_softc *sc, int idx) 590 { 591 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 592 593 bzero(&sc->sc_rxdmadesc[idx], sizeof(sc->sc_rxdmadesc[idx])); 594 sc->sc_rxdmadesc[idx].paddr = rxs->segment.ds_addr; 595 sc->sc_rxdmadesc[idx].len = rxs->segment.ds_len; 596 sc->sc_rxdmadesc[idx].next = sc->sc_rxdmadesc_phys + 597 ((idx + 1) % GLC_MAX_RX_PACKETS)*sizeof(sc->sc_rxdmadesc[idx]); 598 sc->sc_rxdmadesc[idx].cmd_stat = GELIC_DESCR_OWNED; 599 600 rxs->rxs_desc_slot = idx; 601 rxs->rxs_desc = sc->sc_rxdmadesc_phys + idx*sizeof(struct glc_dmadesc); 602 603 return (0); 604 } 605 606 static int 607 glc_encap(struct glc_softc *sc, struct mbuf **m_head, bus_addr_t *pktdesc) 608 { 609 bus_dma_segment_t segs[16]; 610 struct glc_txsoft *txs; 611 struct mbuf *m; 612 bus_addr_t firstslotphys; 613 int i, idx, nsegs, nsegs_max; 614 int err = 0; 615 616 /* Max number of segments is the number of free DMA slots */ 617 nsegs_max = 128 - sc->bsy_txdma_slots; 618 619 if (nsegs_max > 16 || sc->first_used_txdma_slot < 0) 620 nsegs_max = 16; 621 622 /* Get a work queue entry. */ 623 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 624 /* Ran out of descriptors. */ 625 return (ENOBUFS); 626 } 627 628 nsegs = 0; 629 for (m = *m_head; m != NULL; m = m->m_next) 630 nsegs++; 631 632 if (nsegs > nsegs_max) { 633 m = m_collapse(*m_head, M_NOWAIT, nsegs_max); 634 if (m == NULL) { 635 m_freem(*m_head); 636 *m_head = NULL; 637 return (ENOBUFS); 638 } 639 *m_head = m; 640 } 641 642 err = bus_dmamap_load_mbuf_sg(sc->sc_txdma_tag, txs->txs_dmamap, 643 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 644 if (err != 0) { 645 m_freem(*m_head); 646 *m_head = NULL; 647 return (err); 648 } 649 650 KASSERT(nsegs <= 128 - sc->bsy_txdma_slots, 651 ("GLC: Mapped too many (%d) DMA segments with %d available", 652 nsegs, 128 - sc->bsy_txdma_slots)); 653 654 if (nsegs == 0) { 655 m_freem(*m_head); 656 *m_head = NULL; 657 return (EIO); 658 } 659 660 txs->txs_ndescs = nsegs; 661 txs->txs_firstdesc = sc->next_txdma_slot; 662 663 idx = txs->txs_firstdesc; 664 firstslotphys = sc->sc_txdmadesc_phys + 665 txs->txs_firstdesc*sizeof(struct glc_dmadesc); 666 667 for (i = 0; i < nsegs; i++) { 668 bzero(&sc->sc_txdmadesc[idx], sizeof(sc->sc_txdmadesc[idx])); 669 sc->sc_txdmadesc[idx].paddr = segs[i].ds_addr; 670 sc->sc_txdmadesc[idx].len = segs[i].ds_len; 671 sc->sc_txdmadesc[idx].next = sc->sc_txdmadesc_phys + 672 ((idx + 1) % GLC_MAX_TX_PACKETS)*sizeof(struct glc_dmadesc); 673 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_NOIPSEC; 674 675 if (i+1 == nsegs) { 676 txs->txs_lastdesc = idx; 677 sc->sc_txdmadesc[idx].next = 0; 678 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_LAST; 679 } 680 681 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 682 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_TCP; 683 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 684 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_UDP; 685 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_DESCR_OWNED; 686 687 idx = (idx + 1) % GLC_MAX_TX_PACKETS; 688 } 689 sc->next_txdma_slot = idx; 690 sc->bsy_txdma_slots += nsegs; 691 if (txs->txs_firstdesc != 0) 692 idx = txs->txs_firstdesc - 1; 693 else 694 idx = GLC_MAX_TX_PACKETS - 1; 695 696 if (sc->first_used_txdma_slot < 0) 697 sc->first_used_txdma_slot = txs->txs_firstdesc; 698 699 bus_dmamap_sync(sc->sc_txdma_tag, txs->txs_dmamap, 700 BUS_DMASYNC_PREWRITE); 701 sc->sc_txdmadesc[idx].next = firstslotphys; 702 703 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 704 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 705 txs->txs_mbuf = *m_head; 706 *pktdesc = firstslotphys; 707 708 return (0); 709 } 710 711 static void 712 glc_rxintr(struct glc_softc *sc) 713 { 714 int i, restart_rxdma, error; 715 struct mbuf *m; 716 struct ifnet *ifp = sc->sc_ifp; 717 718 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 719 BUS_DMASYNC_POSTREAD); 720 721 restart_rxdma = 0; 722 while ((sc->sc_rxdmadesc[sc->sc_next_rxdma_slot].cmd_stat & 723 GELIC_DESCR_OWNED) == 0) { 724 i = sc->sc_next_rxdma_slot; 725 sc->sc_next_rxdma_slot++; 726 if (sc->sc_next_rxdma_slot >= GLC_MAX_RX_PACKETS) 727 sc->sc_next_rxdma_slot = 0; 728 729 if (sc->sc_rxdmadesc[i].cmd_stat & GELIC_CMDSTAT_CHAIN_END) 730 restart_rxdma = 1; 731 732 if (sc->sc_rxdmadesc[i].rxerror & GELIC_RXERRORS) { 733 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 734 goto requeue; 735 } 736 737 m = sc->sc_rxsoft[i].rxs_mbuf; 738 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_IPCSUM) { 739 m->m_pkthdr.csum_flags |= 740 CSUM_IP_CHECKED | CSUM_IP_VALID; 741 } 742 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_TCPUDPCSUM) { 743 m->m_pkthdr.csum_flags |= 744 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 745 m->m_pkthdr.csum_data = 0xffff; 746 } 747 748 if (glc_add_rxbuf(sc, i)) { 749 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 750 goto requeue; 751 } 752 753 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 754 m->m_pkthdr.rcvif = ifp; 755 m->m_len = sc->sc_rxdmadesc[i].valid_size; 756 m->m_pkthdr.len = m->m_len; 757 758 /* 759 * Remove VLAN tag. Even on early firmwares that do not allow 760 * multiple VLANs, the VLAN tag is still in place here. 761 */ 762 m_adj(m, 2); 763 764 mtx_unlock(&sc->sc_mtx); 765 (*ifp->if_input)(ifp, m); 766 mtx_lock(&sc->sc_mtx); 767 768 requeue: 769 glc_add_rxbuf_dma(sc, i); 770 } 771 772 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 773 BUS_DMASYNC_PREWRITE); 774 775 if (restart_rxdma) { 776 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 777 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 778 if (error != 0) 779 device_printf(sc->sc_self, 780 "lv1_net_start_rx_dma error: %d\n", error); 781 } 782 } 783 784 static void 785 glc_txintr(struct glc_softc *sc) 786 { 787 struct ifnet *ifp = sc->sc_ifp; 788 struct glc_txsoft *txs; 789 int progress = 0, kickstart = 0, error; 790 791 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 792 BUS_DMASYNC_POSTREAD); 793 794 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 795 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat 796 & GELIC_DESCR_OWNED) 797 break; 798 799 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 800 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 801 sc->bsy_txdma_slots -= txs->txs_ndescs; 802 803 if (txs->txs_mbuf != NULL) { 804 m_freem(txs->txs_mbuf); 805 txs->txs_mbuf = NULL; 806 } 807 808 if ((sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 0xf0000000) 809 != 0) { 810 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 811 kickstart = 1; 812 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 813 } 814 815 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 816 GELIC_CMDSTAT_CHAIN_END) 817 kickstart = 1; 818 819 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 820 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 821 progress = 1; 822 } 823 824 if (txs != NULL) 825 sc->first_used_txdma_slot = txs->txs_firstdesc; 826 else 827 sc->first_used_txdma_slot = -1; 828 829 if (kickstart || txs != NULL) { 830 /* Speculatively (or necessarily) start the TX queue again */ 831 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, 832 sc->sc_txdmadesc_phys + 833 ((txs == NULL) ? 0 : txs->txs_firstdesc)* 834 sizeof(struct glc_dmadesc), 0); 835 if (error != 0) 836 device_printf(sc->sc_self, 837 "lv1_net_start_tx_dma error: %d\n", error); 838 } 839 840 if (progress) { 841 /* 842 * We freed some descriptors, so reset IFF_DRV_OACTIVE 843 * and restart. 844 */ 845 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 846 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 847 848 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 849 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 850 glc_start_locked(ifp); 851 } 852 } 853 854 static int 855 glc_intr_filter(void *xsc) 856 { 857 struct glc_softc *sc = xsc; 858 859 powerpc_sync(); 860 atomic_set_64(&sc->sc_interrupt_status, *sc->sc_hwirq_status); 861 return (FILTER_SCHEDULE_THREAD); 862 } 863 864 static void 865 glc_intr(void *xsc) 866 { 867 struct glc_softc *sc = xsc; 868 uint64_t status, linkstat, junk; 869 870 mtx_lock(&sc->sc_mtx); 871 872 status = atomic_readandclear_64(&sc->sc_interrupt_status); 873 874 if (status == 0) { 875 mtx_unlock(&sc->sc_mtx); 876 return; 877 } 878 879 if (status & (GELIC_INT_RXDONE | GELIC_INT_RXFRAME)) 880 glc_rxintr(sc); 881 882 if (status & (GELIC_INT_TXDONE | GELIC_INT_TX_CHAIN_END)) 883 glc_txintr(sc); 884 885 if (status & GELIC_INT_PHY) { 886 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 887 GELIC_VLAN_TX_ETHERNET, 0, 0, &linkstat, &junk); 888 889 linkstat = (linkstat & GELIC_LINK_UP) ? 890 LINK_STATE_UP : LINK_STATE_DOWN; 891 if (linkstat != sc->sc_ifp->if_link_state) 892 if_link_state_change(sc->sc_ifp, linkstat); 893 } 894 895 mtx_unlock(&sc->sc_mtx); 896 } 897 898 static void 899 glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 900 { 901 struct glc_softc *sc = ifp->if_softc; 902 uint64_t status, junk; 903 904 ifmr->ifm_status = IFM_AVALID; 905 ifmr->ifm_active = IFM_ETHER; 906 907 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 908 GELIC_VLAN_TX_ETHERNET, 0, 0, &status, &junk); 909 910 if (status & GELIC_LINK_UP) 911 ifmr->ifm_status |= IFM_ACTIVE; 912 913 if (status & GELIC_SPEED_10) 914 ifmr->ifm_active |= IFM_10_T; 915 else if (status & GELIC_SPEED_100) 916 ifmr->ifm_active |= IFM_100_TX; 917 else if (status & GELIC_SPEED_1000) 918 ifmr->ifm_active |= IFM_1000_T; 919 920 if (status & GELIC_FULL_DUPLEX) 921 ifmr->ifm_active |= IFM_FDX; 922 else 923 ifmr->ifm_active |= IFM_HDX; 924 } 925 926 static int 927 glc_media_change(struct ifnet *ifp) 928 { 929 struct glc_softc *sc = ifp->if_softc; 930 uint64_t mode, junk; 931 int result; 932 933 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 934 return (EINVAL); 935 936 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { 937 case IFM_AUTO: 938 mode = GELIC_AUTO_NEG; 939 break; 940 case IFM_10_T: 941 mode = GELIC_SPEED_10; 942 break; 943 case IFM_100_TX: 944 mode = GELIC_SPEED_100; 945 break; 946 case IFM_1000_T: 947 mode = GELIC_SPEED_1000 | GELIC_FULL_DUPLEX; 948 break; 949 default: 950 return (EINVAL); 951 } 952 953 if (IFM_OPTIONS(sc->sc_media.ifm_media) & IFM_FDX) 954 mode |= GELIC_FULL_DUPLEX; 955 956 result = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_SET_LINK_MODE, 957 GELIC_VLAN_TX_ETHERNET, mode, 0, &junk, &junk); 958 959 return (result ? EIO : 0); 960 } 961