1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2010 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/sockio.h> 33 #include <sys/endian.h> 34 #include <sys/lock.h> 35 #include <sys/mbuf.h> 36 #include <sys/module.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/if_dl.h> 52 53 #include <machine/pio.h> 54 #include <machine/bus.h> 55 #include <machine/platform.h> 56 #include <machine/resource.h> 57 #include <sys/bus.h> 58 #include <sys/rman.h> 59 60 #include "ps3bus.h" 61 #include "ps3-hvcall.h" 62 #include "if_glcreg.h" 63 64 static int glc_probe(device_t); 65 static int glc_attach(device_t); 66 static void glc_init(void *xsc); 67 static void glc_start(struct ifnet *ifp); 68 static int glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 69 static void glc_set_multicast(struct glc_softc *sc); 70 static int glc_add_rxbuf(struct glc_softc *sc, int idx); 71 static int glc_add_rxbuf_dma(struct glc_softc *sc, int idx); 72 static int glc_encap(struct glc_softc *sc, struct mbuf **m_head, 73 bus_addr_t *pktdesc); 74 static int glc_intr_filter(void *xsc); 75 static void glc_intr(void *xsc); 76 static void glc_tick(void *xsc); 77 static void glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr); 78 static int glc_media_change(struct ifnet *ifp); 79 80 static MALLOC_DEFINE(M_GLC, "gelic", "PS3 GELIC ethernet"); 81 82 static device_method_t glc_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_probe, glc_probe), 85 DEVMETHOD(device_attach, glc_attach), 86 87 { 0, 0 } 88 }; 89 90 static driver_t glc_driver = { 91 "glc", 92 glc_methods, 93 sizeof(struct glc_softc) 94 }; 95 96 static devclass_t glc_devclass; 97 98 DRIVER_MODULE(glc, ps3bus, glc_driver, glc_devclass, 0, 0); 99 100 static int 101 glc_probe(device_t dev) 102 { 103 104 if (ps3bus_get_bustype(dev) != PS3_BUSTYPE_SYSBUS || 105 ps3bus_get_devtype(dev) != PS3_DEVTYPE_GELIC) 106 return (ENXIO); 107 108 device_set_desc(dev, "Playstation 3 GELIC Network Controller"); 109 return (BUS_PROBE_SPECIFIC); 110 } 111 112 static void 113 glc_getphys(void *xaddr, bus_dma_segment_t *segs, int nsegs, int error) 114 { 115 if (error != 0) 116 return; 117 118 *(bus_addr_t *)xaddr = segs[0].ds_addr; 119 } 120 121 static int 122 glc_attach(device_t dev) 123 { 124 struct glc_softc *sc; 125 struct glc_txsoft *txs; 126 uint64_t mac64, val, junk; 127 int i, err; 128 129 sc = device_get_softc(dev); 130 131 sc->sc_bus = ps3bus_get_bus(dev); 132 sc->sc_dev = ps3bus_get_device(dev); 133 sc->sc_self = dev; 134 135 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 136 MTX_DEF); 137 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 138 sc->next_txdma_slot = 0; 139 sc->bsy_txdma_slots = 0; 140 sc->sc_next_rxdma_slot = 0; 141 sc->first_used_txdma_slot = -1; 142 143 /* 144 * Shut down existing tasks. 145 */ 146 147 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 148 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 149 150 sc->sc_ifp = if_alloc(IFT_ETHER); 151 sc->sc_ifp->if_softc = sc; 152 153 /* 154 * Get MAC address and VLAN id 155 */ 156 157 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_MAC_ADDRESS, 158 0, 0, 0, &mac64, &junk); 159 memcpy(sc->sc_enaddr, &((uint8_t *)&mac64)[2], sizeof(sc->sc_enaddr)); 160 sc->sc_tx_vlan = sc->sc_rx_vlan = -1; 161 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 162 GELIC_VLAN_TX_ETHERNET, 0, 0, &val, &junk); 163 if (err == 0) 164 sc->sc_tx_vlan = val; 165 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 166 GELIC_VLAN_RX_ETHERNET, 0, 0, &val, &junk); 167 if (err == 0) 168 sc->sc_rx_vlan = val; 169 170 /* 171 * Set up interrupt handler 172 */ 173 sc->sc_irqid = 0; 174 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqid, 175 RF_ACTIVE); 176 if (sc->sc_irq == NULL) { 177 device_printf(dev, "Could not allocate IRQ!\n"); 178 mtx_destroy(&sc->sc_mtx); 179 return (ENXIO); 180 } 181 182 bus_setup_intr(dev, sc->sc_irq, 183 INTR_TYPE_NET | INTR_MPSAFE | INTR_ENTROPY, 184 glc_intr_filter, glc_intr, sc, &sc->sc_irqctx); 185 sc->sc_hwirq_status = (uint64_t *)contigmalloc(8, M_GLC, M_ZERO, 0, 186 BUS_SPACE_MAXADDR_32BIT, 8, PAGE_SIZE); 187 lv1_net_set_interrupt_status_indicator(sc->sc_bus, sc->sc_dev, 188 vtophys(sc->sc_hwirq_status), 0); 189 lv1_net_set_interrupt_mask(sc->sc_bus, sc->sc_dev, 190 GELIC_INT_RXDONE | GELIC_INT_RXFRAME | GELIC_INT_PHY | 191 GELIC_INT_TX_CHAIN_END, 0); 192 193 /* 194 * Set up DMA. 195 */ 196 197 err = bus_dma_tag_create(bus_get_dma_tag(dev), 32, 0, 198 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 199 129*sizeof(struct glc_dmadesc), 1, 128*sizeof(struct glc_dmadesc), 200 0, NULL,NULL, &sc->sc_dmadesc_tag); 201 202 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_txdmadesc, 203 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 204 &sc->sc_txdmadesc_map); 205 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 206 sc->sc_txdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 207 &sc->sc_txdmadesc_phys, 0); 208 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_rxdmadesc, 209 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 210 &sc->sc_rxdmadesc_map); 211 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 212 sc->sc_rxdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 213 &sc->sc_rxdmadesc_phys, 0); 214 215 err = bus_dma_tag_create(bus_get_dma_tag(dev), 128, 0, 216 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 217 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 218 &sc->sc_rxdma_tag); 219 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 220 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 221 BUS_SPACE_MAXSIZE_32BIT, 16, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 222 &sc->sc_txdma_tag); 223 224 /* init transmit descriptors */ 225 STAILQ_INIT(&sc->sc_txfreeq); 226 STAILQ_INIT(&sc->sc_txdirtyq); 227 228 /* create TX DMA maps */ 229 err = ENOMEM; 230 for (i = 0; i < GLC_MAX_TX_PACKETS; i++) { 231 txs = &sc->sc_txsoft[i]; 232 txs->txs_mbuf = NULL; 233 err = bus_dmamap_create(sc->sc_txdma_tag, 0, &txs->txs_dmamap); 234 if (err) { 235 device_printf(dev, 236 "unable to create TX DMA map %d, error = %d\n", 237 i, err); 238 } 239 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 240 } 241 242 /* Create the receive buffer DMA maps. */ 243 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 244 err = bus_dmamap_create(sc->sc_rxdma_tag, 0, 245 &sc->sc_rxsoft[i].rxs_dmamap); 246 if (err) { 247 device_printf(dev, 248 "unable to create RX DMA map %d, error = %d\n", 249 i, err); 250 } 251 sc->sc_rxsoft[i].rxs_mbuf = NULL; 252 } 253 254 /* 255 * Attach to network stack 256 */ 257 258 if_initname(sc->sc_ifp, device_get_name(dev), device_get_unit(dev)); 259 sc->sc_ifp->if_mtu = ETHERMTU; 260 sc->sc_ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 261 sc->sc_ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 262 sc->sc_ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_RXCSUM; 263 sc->sc_ifp->if_capenable = IFCAP_HWCSUM | IFCAP_RXCSUM; 264 sc->sc_ifp->if_start = glc_start; 265 sc->sc_ifp->if_ioctl = glc_ioctl; 266 sc->sc_ifp->if_init = glc_init; 267 268 ifmedia_init(&sc->sc_media, IFM_IMASK, glc_media_change, 269 glc_media_status); 270 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 271 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 272 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 273 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 274 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 275 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 276 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 277 278 IFQ_SET_MAXLEN(&sc->sc_ifp->if_snd, GLC_MAX_TX_PACKETS); 279 sc->sc_ifp->if_snd.ifq_drv_maxlen = GLC_MAX_TX_PACKETS; 280 IFQ_SET_READY(&sc->sc_ifp->if_snd); 281 282 ether_ifattach(sc->sc_ifp, sc->sc_enaddr); 283 sc->sc_ifp->if_hwassist = 0; 284 285 return (0); 286 287 mtx_destroy(&sc->sc_mtx); 288 if_free(sc->sc_ifp); 289 return (ENXIO); 290 } 291 292 static void 293 glc_init_locked(struct glc_softc *sc) 294 { 295 int i, error; 296 struct glc_rxsoft *rxs; 297 struct glc_txsoft *txs; 298 299 mtx_assert(&sc->sc_mtx, MA_OWNED); 300 301 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 302 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 303 304 glc_set_multicast(sc); 305 306 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 307 rxs = &sc->sc_rxsoft[i]; 308 rxs->rxs_desc_slot = i; 309 310 if (rxs->rxs_mbuf == NULL) { 311 glc_add_rxbuf(sc, i); 312 313 if (rxs->rxs_mbuf == NULL) { 314 rxs->rxs_desc_slot = -1; 315 break; 316 } 317 } 318 319 glc_add_rxbuf_dma(sc, i); 320 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 321 BUS_DMASYNC_PREREAD); 322 } 323 324 /* Clear TX dirty queue */ 325 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 326 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 327 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 328 329 if (txs->txs_mbuf != NULL) { 330 m_freem(txs->txs_mbuf); 331 txs->txs_mbuf = NULL; 332 } 333 334 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 335 } 336 sc->first_used_txdma_slot = -1; 337 sc->bsy_txdma_slots = 0; 338 339 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 340 sc->sc_rxsoft[0].rxs_desc, 0); 341 if (error != 0) 342 device_printf(sc->sc_self, 343 "lv1_net_start_rx_dma error: %d\n", error); 344 345 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 346 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 347 sc->sc_ifpflags = sc->sc_ifp->if_flags; 348 349 sc->sc_wdog_timer = 0; 350 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 351 } 352 353 static void 354 glc_stop(void *xsc) 355 { 356 struct glc_softc *sc = xsc; 357 358 mtx_assert(&sc->sc_mtx, MA_OWNED); 359 360 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 361 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 362 } 363 364 static void 365 glc_init(void *xsc) 366 { 367 struct glc_softc *sc = xsc; 368 369 mtx_lock(&sc->sc_mtx); 370 glc_init_locked(sc); 371 mtx_unlock(&sc->sc_mtx); 372 } 373 374 static void 375 glc_tick(void *xsc) 376 { 377 struct glc_softc *sc = xsc; 378 379 mtx_assert(&sc->sc_mtx, MA_OWNED); 380 381 /* 382 * XXX: Sometimes the RX queue gets stuck. Poke it periodically until 383 * we figure out why. This will fail harmlessly if the RX queue is 384 * already running. 385 */ 386 lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 387 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 388 389 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 390 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 391 return; 392 } 393 394 /* Problems */ 395 device_printf(sc->sc_self, "device timeout\n"); 396 397 glc_init_locked(sc); 398 } 399 400 static void 401 glc_start_locked(struct ifnet *ifp) 402 { 403 struct glc_softc *sc = ifp->if_softc; 404 bus_addr_t first, pktdesc; 405 int kickstart = 0; 406 int error; 407 struct mbuf *mb_head; 408 409 mtx_assert(&sc->sc_mtx, MA_OWNED); 410 first = 0; 411 412 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 413 IFF_DRV_RUNNING) 414 return; 415 416 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 417 kickstart = 1; 418 419 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 420 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 421 422 if (mb_head == NULL) 423 break; 424 425 /* Check if the ring buffer is full */ 426 if (sc->bsy_txdma_slots > 125) { 427 /* Put the packet back and stop */ 428 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 429 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 430 break; 431 } 432 433 BPF_MTAP(ifp, mb_head); 434 435 if (sc->sc_tx_vlan >= 0) 436 mb_head = ether_vlanencap(mb_head, sc->sc_tx_vlan); 437 438 if (glc_encap(sc, &mb_head, &pktdesc)) { 439 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 440 break; 441 } 442 443 if (first == 0) 444 first = pktdesc; 445 } 446 447 if (kickstart && first != 0) { 448 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, first, 0); 449 if (error != 0) 450 device_printf(sc->sc_self, 451 "lv1_net_start_tx_dma error: %d\n", error); 452 sc->sc_wdog_timer = 5; 453 } 454 } 455 456 static void 457 glc_start(struct ifnet *ifp) 458 { 459 struct glc_softc *sc = ifp->if_softc; 460 461 mtx_lock(&sc->sc_mtx); 462 glc_start_locked(ifp); 463 mtx_unlock(&sc->sc_mtx); 464 } 465 466 static int 467 glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 468 { 469 struct glc_softc *sc = ifp->if_softc; 470 struct ifreq *ifr = (struct ifreq *)data; 471 int err = 0; 472 473 switch (cmd) { 474 case SIOCSIFFLAGS: 475 mtx_lock(&sc->sc_mtx); 476 if ((ifp->if_flags & IFF_UP) != 0) { 477 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 478 ((ifp->if_flags ^ sc->sc_ifpflags) & 479 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 480 glc_set_multicast(sc); 481 else 482 glc_init_locked(sc); 483 } 484 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 485 glc_stop(sc); 486 sc->sc_ifpflags = ifp->if_flags; 487 mtx_unlock(&sc->sc_mtx); 488 break; 489 case SIOCADDMULTI: 490 case SIOCDELMULTI: 491 mtx_lock(&sc->sc_mtx); 492 glc_set_multicast(sc); 493 mtx_unlock(&sc->sc_mtx); 494 break; 495 case SIOCGIFMEDIA: 496 case SIOCSIFMEDIA: 497 err = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 498 break; 499 default: 500 err = ether_ioctl(ifp, cmd, data); 501 break; 502 } 503 504 return (err); 505 } 506 507 static void 508 glc_set_multicast(struct glc_softc *sc) 509 { 510 struct ifnet *ifp = sc->sc_ifp; 511 struct ifmultiaddr *inm; 512 uint64_t addr; 513 int naddrs; 514 515 /* Clear multicast filter */ 516 lv1_net_remove_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 517 518 /* Add broadcast */ 519 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 520 0xffffffffffffL, 0); 521 522 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 523 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 524 } else { 525 if_maddr_rlock(ifp); 526 naddrs = 1; /* Include broadcast */ 527 CK_STAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 528 if (inm->ifma_addr->sa_family != AF_LINK) 529 continue; 530 addr = 0; 531 memcpy(&((uint8_t *)(&addr))[2], 532 LLADDR((struct sockaddr_dl *)inm->ifma_addr), 533 ETHER_ADDR_LEN); 534 535 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 536 addr, 0); 537 538 /* 539 * Filter can only hold 32 addresses, so fall back to 540 * the IFF_ALLMULTI case if we have too many. 541 */ 542 if (++naddrs >= 32) { 543 lv1_net_add_multicast_address(sc->sc_bus, 544 sc->sc_dev, 0, 1); 545 break; 546 } 547 } 548 if_maddr_runlock(ifp); 549 } 550 } 551 552 static int 553 glc_add_rxbuf(struct glc_softc *sc, int idx) 554 { 555 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 556 struct mbuf *m; 557 bus_dma_segment_t segs[1]; 558 int error, nsegs; 559 560 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 561 if (m == NULL) 562 return (ENOBUFS); 563 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 564 565 if (rxs->rxs_mbuf != NULL) { 566 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, 567 BUS_DMASYNC_POSTREAD); 568 bus_dmamap_unload(sc->sc_rxdma_tag, rxs->rxs_dmamap); 569 } 570 571 error = bus_dmamap_load_mbuf_sg(sc->sc_rxdma_tag, rxs->rxs_dmamap, m, 572 segs, &nsegs, BUS_DMA_NOWAIT); 573 if (error != 0) { 574 device_printf(sc->sc_self, 575 "cannot load RS DMA map %d, error = %d\n", idx, error); 576 m_freem(m); 577 return (error); 578 } 579 /* If nsegs is wrong then the stack is corrupt. */ 580 KASSERT(nsegs == 1, 581 ("%s: too many DMA segments (%d)", __func__, nsegs)); 582 rxs->rxs_mbuf = m; 583 rxs->segment = segs[0]; 584 585 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 586 587 return (0); 588 } 589 590 static int 591 glc_add_rxbuf_dma(struct glc_softc *sc, int idx) 592 { 593 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 594 595 bzero(&sc->sc_rxdmadesc[idx], sizeof(sc->sc_rxdmadesc[idx])); 596 sc->sc_rxdmadesc[idx].paddr = rxs->segment.ds_addr; 597 sc->sc_rxdmadesc[idx].len = rxs->segment.ds_len; 598 sc->sc_rxdmadesc[idx].next = sc->sc_rxdmadesc_phys + 599 ((idx + 1) % GLC_MAX_RX_PACKETS)*sizeof(sc->sc_rxdmadesc[idx]); 600 sc->sc_rxdmadesc[idx].cmd_stat = GELIC_DESCR_OWNED; 601 602 rxs->rxs_desc_slot = idx; 603 rxs->rxs_desc = sc->sc_rxdmadesc_phys + idx*sizeof(struct glc_dmadesc); 604 605 return (0); 606 } 607 608 static int 609 glc_encap(struct glc_softc *sc, struct mbuf **m_head, bus_addr_t *pktdesc) 610 { 611 bus_dma_segment_t segs[16]; 612 struct glc_txsoft *txs; 613 struct mbuf *m; 614 bus_addr_t firstslotphys; 615 int i, idx, nsegs, nsegs_max; 616 int err = 0; 617 618 /* Max number of segments is the number of free DMA slots */ 619 nsegs_max = 128 - sc->bsy_txdma_slots; 620 621 if (nsegs_max > 16 || sc->first_used_txdma_slot < 0) 622 nsegs_max = 16; 623 624 /* Get a work queue entry. */ 625 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 626 /* Ran out of descriptors. */ 627 return (ENOBUFS); 628 } 629 630 nsegs = 0; 631 for (m = *m_head; m != NULL; m = m->m_next) 632 nsegs++; 633 634 if (nsegs > nsegs_max) { 635 m = m_collapse(*m_head, M_NOWAIT, nsegs_max); 636 if (m == NULL) { 637 m_freem(*m_head); 638 *m_head = NULL; 639 return (ENOBUFS); 640 } 641 *m_head = m; 642 } 643 644 err = bus_dmamap_load_mbuf_sg(sc->sc_txdma_tag, txs->txs_dmamap, 645 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 646 if (err != 0) { 647 m_freem(*m_head); 648 *m_head = NULL; 649 return (err); 650 } 651 652 KASSERT(nsegs <= 128 - sc->bsy_txdma_slots, 653 ("GLC: Mapped too many (%d) DMA segments with %d available", 654 nsegs, 128 - sc->bsy_txdma_slots)); 655 656 if (nsegs == 0) { 657 m_freem(*m_head); 658 *m_head = NULL; 659 return (EIO); 660 } 661 662 txs->txs_ndescs = nsegs; 663 txs->txs_firstdesc = sc->next_txdma_slot; 664 665 idx = txs->txs_firstdesc; 666 firstslotphys = sc->sc_txdmadesc_phys + 667 txs->txs_firstdesc*sizeof(struct glc_dmadesc); 668 669 for (i = 0; i < nsegs; i++) { 670 bzero(&sc->sc_txdmadesc[idx], sizeof(sc->sc_txdmadesc[idx])); 671 sc->sc_txdmadesc[idx].paddr = segs[i].ds_addr; 672 sc->sc_txdmadesc[idx].len = segs[i].ds_len; 673 sc->sc_txdmadesc[idx].next = sc->sc_txdmadesc_phys + 674 ((idx + 1) % GLC_MAX_TX_PACKETS)*sizeof(struct glc_dmadesc); 675 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_NOIPSEC; 676 677 if (i+1 == nsegs) { 678 txs->txs_lastdesc = idx; 679 sc->sc_txdmadesc[idx].next = 0; 680 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_LAST; 681 } 682 683 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 684 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_TCP; 685 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 686 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_UDP; 687 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_DESCR_OWNED; 688 689 idx = (idx + 1) % GLC_MAX_TX_PACKETS; 690 } 691 sc->next_txdma_slot = idx; 692 sc->bsy_txdma_slots += nsegs; 693 if (txs->txs_firstdesc != 0) 694 idx = txs->txs_firstdesc - 1; 695 else 696 idx = GLC_MAX_TX_PACKETS - 1; 697 698 if (sc->first_used_txdma_slot < 0) 699 sc->first_used_txdma_slot = txs->txs_firstdesc; 700 701 bus_dmamap_sync(sc->sc_txdma_tag, txs->txs_dmamap, 702 BUS_DMASYNC_PREWRITE); 703 sc->sc_txdmadesc[idx].next = firstslotphys; 704 705 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 706 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 707 txs->txs_mbuf = *m_head; 708 *pktdesc = firstslotphys; 709 710 return (0); 711 } 712 713 static void 714 glc_rxintr(struct glc_softc *sc) 715 { 716 int i, restart_rxdma, error; 717 struct mbuf *m; 718 struct ifnet *ifp = sc->sc_ifp; 719 720 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 721 BUS_DMASYNC_POSTREAD); 722 723 restart_rxdma = 0; 724 while ((sc->sc_rxdmadesc[sc->sc_next_rxdma_slot].cmd_stat & 725 GELIC_DESCR_OWNED) == 0) { 726 i = sc->sc_next_rxdma_slot; 727 sc->sc_next_rxdma_slot++; 728 if (sc->sc_next_rxdma_slot >= GLC_MAX_RX_PACKETS) 729 sc->sc_next_rxdma_slot = 0; 730 731 if (sc->sc_rxdmadesc[i].cmd_stat & GELIC_CMDSTAT_CHAIN_END) 732 restart_rxdma = 1; 733 734 if (sc->sc_rxdmadesc[i].rxerror & GELIC_RXERRORS) { 735 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 736 goto requeue; 737 } 738 739 m = sc->sc_rxsoft[i].rxs_mbuf; 740 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_IPCSUM) { 741 m->m_pkthdr.csum_flags |= 742 CSUM_IP_CHECKED | CSUM_IP_VALID; 743 } 744 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_TCPUDPCSUM) { 745 m->m_pkthdr.csum_flags |= 746 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 747 m->m_pkthdr.csum_data = 0xffff; 748 } 749 750 if (glc_add_rxbuf(sc, i)) { 751 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 752 goto requeue; 753 } 754 755 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 756 m->m_pkthdr.rcvif = ifp; 757 m->m_len = sc->sc_rxdmadesc[i].valid_size; 758 m->m_pkthdr.len = m->m_len; 759 760 /* 761 * Remove VLAN tag. Even on early firmwares that do not allow 762 * multiple VLANs, the VLAN tag is still in place here. 763 */ 764 m_adj(m, 2); 765 766 mtx_unlock(&sc->sc_mtx); 767 (*ifp->if_input)(ifp, m); 768 mtx_lock(&sc->sc_mtx); 769 770 requeue: 771 glc_add_rxbuf_dma(sc, i); 772 } 773 774 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 775 BUS_DMASYNC_PREWRITE); 776 777 if (restart_rxdma) { 778 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 779 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 780 if (error != 0) 781 device_printf(sc->sc_self, 782 "lv1_net_start_rx_dma error: %d\n", error); 783 } 784 } 785 786 static void 787 glc_txintr(struct glc_softc *sc) 788 { 789 struct ifnet *ifp = sc->sc_ifp; 790 struct glc_txsoft *txs; 791 int progress = 0, kickstart = 0, error; 792 793 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 794 BUS_DMASYNC_POSTREAD); 795 796 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 797 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat 798 & GELIC_DESCR_OWNED) 799 break; 800 801 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 802 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 803 sc->bsy_txdma_slots -= txs->txs_ndescs; 804 805 if (txs->txs_mbuf != NULL) { 806 m_freem(txs->txs_mbuf); 807 txs->txs_mbuf = NULL; 808 } 809 810 if ((sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 0xf0000000) 811 != 0) { 812 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 813 kickstart = 1; 814 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 815 } 816 817 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 818 GELIC_CMDSTAT_CHAIN_END) 819 kickstart = 1; 820 821 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 822 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 823 progress = 1; 824 } 825 826 if (txs != NULL) 827 sc->first_used_txdma_slot = txs->txs_firstdesc; 828 else 829 sc->first_used_txdma_slot = -1; 830 831 if (kickstart || txs != NULL) { 832 /* Speculatively (or necessarily) start the TX queue again */ 833 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, 834 sc->sc_txdmadesc_phys + 835 ((txs == NULL) ? 0 : txs->txs_firstdesc)* 836 sizeof(struct glc_dmadesc), 0); 837 if (error != 0) 838 device_printf(sc->sc_self, 839 "lv1_net_start_tx_dma error: %d\n", error); 840 } 841 842 if (progress) { 843 /* 844 * We freed some descriptors, so reset IFF_DRV_OACTIVE 845 * and restart. 846 */ 847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 848 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 849 850 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 851 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 852 glc_start_locked(ifp); 853 } 854 } 855 856 static int 857 glc_intr_filter(void *xsc) 858 { 859 struct glc_softc *sc = xsc; 860 861 powerpc_sync(); 862 atomic_set_64(&sc->sc_interrupt_status, *sc->sc_hwirq_status); 863 return (FILTER_SCHEDULE_THREAD); 864 } 865 866 static void 867 glc_intr(void *xsc) 868 { 869 struct glc_softc *sc = xsc; 870 uint64_t status, linkstat, junk; 871 872 mtx_lock(&sc->sc_mtx); 873 874 status = atomic_readandclear_64(&sc->sc_interrupt_status); 875 876 if (status == 0) { 877 mtx_unlock(&sc->sc_mtx); 878 return; 879 } 880 881 if (status & (GELIC_INT_RXDONE | GELIC_INT_RXFRAME)) 882 glc_rxintr(sc); 883 884 if (status & (GELIC_INT_TXDONE | GELIC_INT_TX_CHAIN_END)) 885 glc_txintr(sc); 886 887 if (status & GELIC_INT_PHY) { 888 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 889 GELIC_VLAN_TX_ETHERNET, 0, 0, &linkstat, &junk); 890 891 linkstat = (linkstat & GELIC_LINK_UP) ? 892 LINK_STATE_UP : LINK_STATE_DOWN; 893 if (linkstat != sc->sc_ifp->if_link_state) 894 if_link_state_change(sc->sc_ifp, linkstat); 895 } 896 897 mtx_unlock(&sc->sc_mtx); 898 } 899 900 static void 901 glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 902 { 903 struct glc_softc *sc = ifp->if_softc; 904 uint64_t status, junk; 905 906 ifmr->ifm_status = IFM_AVALID; 907 ifmr->ifm_active = IFM_ETHER; 908 909 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 910 GELIC_VLAN_TX_ETHERNET, 0, 0, &status, &junk); 911 912 if (status & GELIC_LINK_UP) 913 ifmr->ifm_status |= IFM_ACTIVE; 914 915 if (status & GELIC_SPEED_10) 916 ifmr->ifm_active |= IFM_10_T; 917 else if (status & GELIC_SPEED_100) 918 ifmr->ifm_active |= IFM_100_TX; 919 else if (status & GELIC_SPEED_1000) 920 ifmr->ifm_active |= IFM_1000_T; 921 922 if (status & GELIC_FULL_DUPLEX) 923 ifmr->ifm_active |= IFM_FDX; 924 else 925 ifmr->ifm_active |= IFM_HDX; 926 } 927 928 static int 929 glc_media_change(struct ifnet *ifp) 930 { 931 struct glc_softc *sc = ifp->if_softc; 932 uint64_t mode, junk; 933 int result; 934 935 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 936 return (EINVAL); 937 938 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { 939 case IFM_AUTO: 940 mode = GELIC_AUTO_NEG; 941 break; 942 case IFM_10_T: 943 mode = GELIC_SPEED_10; 944 break; 945 case IFM_100_TX: 946 mode = GELIC_SPEED_100; 947 break; 948 case IFM_1000_T: 949 mode = GELIC_SPEED_1000 | GELIC_FULL_DUPLEX; 950 break; 951 default: 952 return (EINVAL); 953 } 954 955 if (IFM_OPTIONS(sc->sc_media.ifm_media) & IFM_FDX) 956 mode |= GELIC_FULL_DUPLEX; 957 958 result = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_SET_LINK_MODE, 959 GELIC_VLAN_TX_ETHERNET, mode, 0, &junk, &junk); 960 961 return (result ? EIO : 0); 962 } 963 964