1 /*- 2 * Copyright (c) 2015 Nathan Whitehorn 3 * Copyright (c) 2017-2018 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/pcpu.h> 36 #include <sys/proc.h> 37 #include <sys/smp.h> 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/bus.h> 42 #include <machine/cpu.h> 43 #include <machine/hid.h> 44 #include <machine/platformvar.h> 45 #include <machine/pmap.h> 46 #include <machine/rtas.h> 47 #include <machine/smp.h> 48 #include <machine/spr.h> 49 #include <machine/trap.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 #include <machine/ofw_machdep.h> 55 #include <powerpc/aim/mmu_oea64.h> 56 57 #include "platform_if.h" 58 #include "opal.h" 59 60 #ifdef SMP 61 extern void *ap_pcpu; 62 #endif 63 64 void (*powernv_smp_ap_extra_init)(void); 65 66 static int powernv_probe(platform_t); 67 static int powernv_attach(platform_t); 68 void powernv_mem_regions(platform_t, struct mem_region *phys, int *physsz, 69 struct mem_region *avail, int *availsz); 70 static void powernv_numa_mem_regions(platform_t plat, struct numa_mem_region *phys, int *physsz); 71 static u_long powernv_timebase_freq(platform_t, struct cpuref *cpuref); 72 static int powernv_smp_first_cpu(platform_t, struct cpuref *cpuref); 73 static int powernv_smp_next_cpu(platform_t, struct cpuref *cpuref); 74 static int powernv_smp_get_bsp(platform_t, struct cpuref *cpuref); 75 static void powernv_smp_ap_init(platform_t); 76 #ifdef SMP 77 static int powernv_smp_start_cpu(platform_t, struct pcpu *cpu); 78 static void powernv_smp_probe_threads(platform_t); 79 static struct cpu_group *powernv_smp_topo(platform_t plat); 80 #endif 81 static void powernv_reset(platform_t); 82 static void powernv_cpu_idle(sbintime_t sbt); 83 static int powernv_cpuref_init(void); 84 static int powernv_node_numa_domain(platform_t platform, phandle_t node); 85 86 static platform_method_t powernv_methods[] = { 87 PLATFORMMETHOD(platform_probe, powernv_probe), 88 PLATFORMMETHOD(platform_attach, powernv_attach), 89 PLATFORMMETHOD(platform_mem_regions, powernv_mem_regions), 90 PLATFORMMETHOD(platform_numa_mem_regions, powernv_numa_mem_regions), 91 PLATFORMMETHOD(platform_timebase_freq, powernv_timebase_freq), 92 93 PLATFORMMETHOD(platform_smp_ap_init, powernv_smp_ap_init), 94 PLATFORMMETHOD(platform_smp_first_cpu, powernv_smp_first_cpu), 95 PLATFORMMETHOD(platform_smp_next_cpu, powernv_smp_next_cpu), 96 PLATFORMMETHOD(platform_smp_get_bsp, powernv_smp_get_bsp), 97 #ifdef SMP 98 PLATFORMMETHOD(platform_smp_start_cpu, powernv_smp_start_cpu), 99 PLATFORMMETHOD(platform_smp_probe_threads, powernv_smp_probe_threads), 100 PLATFORMMETHOD(platform_smp_topo, powernv_smp_topo), 101 #endif 102 PLATFORMMETHOD(platform_node_numa_domain, powernv_node_numa_domain), 103 104 PLATFORMMETHOD(platform_reset, powernv_reset), 105 { 0, 0 } 106 }; 107 108 static platform_def_t powernv_platform = { 109 "powernv", 110 powernv_methods, 111 0 112 }; 113 114 static struct cpuref platform_cpuref[MAXCPU]; 115 static int platform_cpuref_cnt; 116 static int platform_cpuref_valid; 117 static int platform_associativity; 118 119 PLATFORM_DEF(powernv_platform); 120 121 static uint64_t powernv_boot_pir; 122 123 static int 124 powernv_probe(platform_t plat) 125 { 126 if (opal_check() == 0) 127 return (BUS_PROBE_SPECIFIC); 128 129 return (ENXIO); 130 } 131 132 static int 133 powernv_attach(platform_t plat) 134 { 135 uint32_t nptlp, shift = 0, slb_encoding = 0; 136 int32_t lp_size, lp_encoding; 137 char buf[255]; 138 pcell_t refpoints[3]; 139 pcell_t prop; 140 phandle_t cpu; 141 phandle_t opal; 142 int res, len, idx; 143 register_t msr; 144 145 /* Ping OPAL again just to make sure */ 146 opal_check(); 147 148 #if BYTE_ORDER == LITTLE_ENDIAN 149 opal_call(OPAL_REINIT_CPUS, 2 /* Little endian */); 150 #else 151 opal_call(OPAL_REINIT_CPUS, 1 /* Big endian */); 152 #endif 153 opal = OF_finddevice("/ibm,opal"); 154 155 platform_associativity = 4; /* Skiboot default. */ 156 if (OF_getencprop(opal, "ibm,associativity-reference-points", refpoints, 157 sizeof(refpoints)) > 0) { 158 platform_associativity = refpoints[0]; 159 } 160 161 if (cpu_idle_hook == NULL) 162 cpu_idle_hook = powernv_cpu_idle; 163 164 powernv_boot_pir = mfspr(SPR_PIR); 165 166 /* LPID must not be altered when PSL_DR or PSL_IR is set */ 167 msr = mfmsr(); 168 mtmsr(msr & ~(PSL_DR | PSL_IR)); 169 170 /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */ 171 mtspr(SPR_LPID, 0); 172 isync(); 173 174 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) 175 lpcr |= LPCR_HVICE; 176 177 mtspr(SPR_LPCR, lpcr); 178 isync(); 179 180 mtmsr(msr); 181 182 powernv_cpuref_init(); 183 184 /* Set SLB count from device tree */ 185 cpu = OF_peer(0); 186 cpu = OF_child(cpu); 187 while (cpu != 0) { 188 res = OF_getprop(cpu, "name", buf, sizeof(buf)); 189 if (res > 0 && strcmp(buf, "cpus") == 0) 190 break; 191 cpu = OF_peer(cpu); 192 } 193 if (cpu == 0) 194 goto out; 195 196 cpu = OF_child(cpu); 197 while (cpu != 0) { 198 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 199 if (res > 0 && strcmp(buf, "cpu") == 0) 200 break; 201 cpu = OF_peer(cpu); 202 } 203 if (cpu == 0) 204 goto out; 205 206 res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop)); 207 if (res > 0) 208 n_slbs = prop; 209 210 /* 211 * Scan the large page size property for PAPR compatible machines. 212 * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties' 213 * for the encoding of the property. 214 */ 215 216 len = OF_getproplen(cpu, "ibm,segment-page-sizes"); 217 if (len > 0) { 218 /* 219 * We have to use a variable length array on the stack 220 * since we have very limited stack space. 221 */ 222 pcell_t arr[len/sizeof(cell_t)]; 223 res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr, 224 sizeof(arr)); 225 len /= 4; 226 idx = 0; 227 while (len > 0) { 228 shift = arr[idx]; 229 slb_encoding = arr[idx + 1]; 230 nptlp = arr[idx + 2]; 231 idx += 3; 232 len -= 3; 233 while (len > 0 && nptlp) { 234 lp_size = arr[idx]; 235 lp_encoding = arr[idx+1]; 236 if (slb_encoding == SLBV_L && lp_encoding == 0) 237 break; 238 239 idx += 2; 240 len -= 2; 241 nptlp--; 242 } 243 if (nptlp && slb_encoding == SLBV_L && lp_encoding == 0) 244 break; 245 } 246 247 if (len == 0) 248 panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) " 249 "not supported by this system."); 250 251 moea64_large_page_shift = shift; 252 moea64_large_page_size = 1ULL << lp_size; 253 } 254 255 out: 256 return (0); 257 } 258 259 void 260 powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz, 261 struct mem_region *avail, int *availsz) 262 { 263 264 ofw_mem_regions(phys, physsz, avail, availsz); 265 } 266 267 static void 268 powernv_numa_mem_regions(platform_t plat, struct numa_mem_region *phys, int *physsz) 269 { 270 271 ofw_numa_mem_regions(phys, physsz); 272 } 273 274 static u_long 275 powernv_timebase_freq(platform_t plat, struct cpuref *cpuref) 276 { 277 char buf[8]; 278 phandle_t cpu, dev, root; 279 int res; 280 int32_t ticks = -1; 281 282 root = OF_peer(0); 283 dev = OF_child(root); 284 while (dev != 0) { 285 res = OF_getprop(dev, "name", buf, sizeof(buf)); 286 if (res > 0 && strcmp(buf, "cpus") == 0) 287 break; 288 dev = OF_peer(dev); 289 } 290 291 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { 292 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 293 if (res > 0 && strcmp(buf, "cpu") == 0) 294 break; 295 } 296 if (cpu == 0) 297 return (512000000); 298 299 OF_getencprop(cpu, "timebase-frequency", &ticks, sizeof(ticks)); 300 301 if (ticks <= 0) 302 panic("Unable to determine timebase frequency!"); 303 304 return (ticks); 305 306 } 307 308 static int 309 powernv_cpuref_init(void) 310 { 311 phandle_t cpu, dev; 312 char buf[32]; 313 int a, res, tmp_cpuref_cnt; 314 static struct cpuref tmp_cpuref[MAXCPU]; 315 cell_t interrupt_servers[32]; 316 uint64_t bsp; 317 318 if (platform_cpuref_valid) 319 return (0); 320 321 dev = OF_peer(0); 322 dev = OF_child(dev); 323 while (dev != 0) { 324 res = OF_getprop(dev, "name", buf, sizeof(buf)); 325 if (res > 0 && strcmp(buf, "cpus") == 0) 326 break; 327 dev = OF_peer(dev); 328 } 329 330 bsp = 0; 331 tmp_cpuref_cnt = 0; 332 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { 333 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 334 if (res > 0 && strcmp(buf, "cpu") == 0) { 335 if (!ofw_bus_node_status_okay(cpu)) 336 continue; 337 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s"); 338 if (res > 0) { 339 OF_getencprop(cpu, "ibm,ppc-interrupt-server#s", 340 interrupt_servers, res); 341 342 for (a = 0; a < res/sizeof(cell_t); a++) { 343 tmp_cpuref[tmp_cpuref_cnt].cr_hwref = interrupt_servers[a]; 344 tmp_cpuref[tmp_cpuref_cnt].cr_cpuid = tmp_cpuref_cnt; 345 tmp_cpuref[tmp_cpuref_cnt].cr_domain = 346 powernv_node_numa_domain(NULL, cpu); 347 if (interrupt_servers[a] == (uint32_t)powernv_boot_pir) 348 bsp = tmp_cpuref_cnt; 349 350 tmp_cpuref_cnt++; 351 } 352 } 353 } 354 } 355 356 /* Map IDs, so BSP has CPUID 0 regardless of hwref */ 357 for (a = bsp; a < tmp_cpuref_cnt; a++) { 358 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref; 359 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt; 360 platform_cpuref[platform_cpuref_cnt].cr_domain = tmp_cpuref[a].cr_domain; 361 platform_cpuref_cnt++; 362 } 363 for (a = 0; a < bsp; a++) { 364 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref; 365 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt; 366 platform_cpuref[platform_cpuref_cnt].cr_domain = tmp_cpuref[a].cr_domain; 367 platform_cpuref_cnt++; 368 } 369 370 platform_cpuref_valid = 1; 371 372 return (0); 373 } 374 375 static int 376 powernv_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 377 { 378 if (platform_cpuref_valid == 0) 379 return (EINVAL); 380 381 cpuref->cr_cpuid = 0; 382 cpuref->cr_hwref = platform_cpuref[0].cr_hwref; 383 cpuref->cr_domain = platform_cpuref[0].cr_domain; 384 385 return (0); 386 } 387 388 static int 389 powernv_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 390 { 391 int id; 392 393 if (platform_cpuref_valid == 0) 394 return (EINVAL); 395 396 id = cpuref->cr_cpuid + 1; 397 if (id >= platform_cpuref_cnt) 398 return (ENOENT); 399 400 cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid; 401 cpuref->cr_hwref = platform_cpuref[id].cr_hwref; 402 cpuref->cr_domain = platform_cpuref[id].cr_domain; 403 404 return (0); 405 } 406 407 static int 408 powernv_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 409 { 410 411 cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid; 412 cpuref->cr_hwref = platform_cpuref[0].cr_hwref; 413 cpuref->cr_domain = platform_cpuref[0].cr_domain; 414 return (0); 415 } 416 417 #ifdef SMP 418 static int 419 powernv_smp_start_cpu(platform_t plat, struct pcpu *pc) 420 { 421 int result; 422 423 ap_pcpu = pc; 424 powerpc_sync(); 425 426 result = opal_call(OPAL_START_CPU, pc->pc_hwref, EXC_RST); 427 if (result != OPAL_SUCCESS) { 428 printf("OPAL error (%d): unable to start AP %d\n", 429 result, (int)pc->pc_hwref); 430 return (ENXIO); 431 } 432 433 return (0); 434 } 435 436 static void 437 powernv_smp_probe_threads(platform_t plat) 438 { 439 char buf[8]; 440 phandle_t cpu, dev, root; 441 int res, nthreads; 442 443 root = OF_peer(0); 444 445 dev = OF_child(root); 446 while (dev != 0) { 447 res = OF_getprop(dev, "name", buf, sizeof(buf)); 448 if (res > 0 && strcmp(buf, "cpus") == 0) 449 break; 450 dev = OF_peer(dev); 451 } 452 453 nthreads = 1; 454 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { 455 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 456 if (res <= 0 || strcmp(buf, "cpu") != 0) 457 continue; 458 459 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s"); 460 461 if (res >= 0) 462 nthreads = res / sizeof(cell_t); 463 else 464 nthreads = 1; 465 break; 466 } 467 468 smp_threads_per_core = nthreads; 469 if (mp_ncpus % nthreads == 0) 470 mp_ncores = mp_ncpus / nthreads; 471 } 472 473 static struct cpu_group * 474 powernv_smp_topo(platform_t plat) 475 { 476 if (mp_ncpus % smp_threads_per_core != 0) { 477 printf("WARNING: Irregular SMP topology. Performance may be " 478 "suboptimal (%d threads, %d on first core)\n", 479 mp_ncpus, smp_threads_per_core); 480 return (smp_topo_none()); 481 } 482 483 /* Don't do anything fancier for non-threaded SMP */ 484 if (smp_threads_per_core == 1) 485 return (smp_topo_none()); 486 487 return (smp_topo_1level(CG_SHARE_L1, smp_threads_per_core, 488 CG_FLAG_SMT)); 489 } 490 491 #endif 492 493 static void 494 powernv_reset(platform_t platform) 495 { 496 497 opal_call(OPAL_CEC_REBOOT); 498 } 499 500 static void 501 powernv_smp_ap_init(platform_t platform) 502 { 503 504 if (powernv_smp_ap_extra_init != NULL) 505 powernv_smp_ap_extra_init(); 506 } 507 508 static void 509 powernv_cpu_idle(sbintime_t sbt) 510 { 511 } 512 513 static int 514 powernv_node_numa_domain(platform_t platform, phandle_t node) 515 { 516 /* XXX: Is locking necessary in here? */ 517 static int numa_domains[MAXMEMDOM]; 518 static int numa_max_domain; 519 cell_t associativity[5]; 520 int i, res; 521 522 #ifndef NUMA 523 return (0); 524 #endif 525 if (vm_ndomains == 1) 526 return (0); 527 528 res = OF_getencprop(node, "ibm,associativity", 529 associativity, sizeof(associativity)); 530 531 /* 532 * If this node doesn't have associativity, or if there are not 533 * enough elements in it, check its parent. 534 */ 535 if (res < (int)(sizeof(cell_t) * (platform_associativity + 1))) { 536 node = OF_parent(node); 537 /* If already at the root, use default domain. */ 538 if (node == 0) 539 return (0); 540 return (powernv_node_numa_domain(platform, node)); 541 } 542 543 for (i = 0; i < numa_max_domain; i++) { 544 if (numa_domains[i] == associativity[platform_associativity]) 545 return (i); 546 } 547 if (i < MAXMEMDOM) 548 numa_domains[numa_max_domain++] = 549 associativity[platform_associativity]; 550 else 551 i = 0; 552 553 return (i); 554 } 555 556 /* Set up the Nest MMU on POWER9 relatively early, but after pmap is setup. */ 557 static void 558 powernv_setup_nmmu(void *unused) 559 { 560 if (opal_check() != 0) 561 return; 562 opal_call(OPAL_NMMU_SET_PTCR, -1, mfspr(SPR_PTCR)); 563 } 564 565 SYSINIT(powernv_setup_nmmu, SI_SUB_CPU, SI_ORDER_ANY, powernv_setup_nmmu, NULL); 566