1 /*- 2 * Copyright (c) 2017-2018 QCM Technologies. 3 * Copyright (c) 2017-2018 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/endian.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <machine/bus.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #include <dev/iicbus/iiconf.h> 51 #include <dev/iicbus/iicbus.h> 52 #include "iicbus_if.h" 53 54 #include "opal.h" 55 56 #ifdef FDT 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 #endif 60 61 struct opal_i2c_softc 62 { 63 device_t dev; 64 device_t iicbus; 65 uint32_t opal_id; 66 struct mtx sc_mtx; 67 }; 68 69 /* OPAL I2C request */ 70 struct opal_i2c_request { 71 uint8_t type; 72 #define OPAL_I2C_RAW_READ 0 73 #define OPAL_I2C_RAW_WRITE 1 74 #define OPAL_I2C_SM_READ 2 75 #define OPAL_I2C_SM_WRITE 3 76 uint8_t flags; 77 uint8_t subaddr_sz; /* Max 4 */ 78 uint8_t reserved; 79 uint16_t addr; /* 7 or 10 bit address */ 80 uint16_t reserved2; 81 uint32_t subaddr; /* Sub-address if any */ 82 uint32_t size; /* Data size */ 83 uint64_t buffer_pa; /* Buffer real address */ 84 }; 85 86 static int opal_i2c_attach(device_t); 87 static int opal_i2c_callback(device_t, int, caddr_t); 88 static int opal_i2c_probe(device_t); 89 static int opal_i2c_transfer(device_t, struct iic_msg *, uint32_t); 90 static int i2c_opal_send_request(uint32_t, struct opal_i2c_request *); 91 static phandle_t opal_i2c_get_node(device_t bus, device_t dev); 92 93 static device_method_t opal_i2c_methods[] = { 94 /* Device interface */ 95 DEVMETHOD(device_probe, opal_i2c_probe), 96 DEVMETHOD(device_attach, opal_i2c_attach), 97 98 /* iicbus interface */ 99 DEVMETHOD(iicbus_callback, opal_i2c_callback), 100 DEVMETHOD(iicbus_transfer, opal_i2c_transfer), 101 DEVMETHOD(ofw_bus_get_node, opal_i2c_get_node), 102 DEVMETHOD_END 103 }; 104 105 #define I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 106 #define I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 107 #define I2C_LOCK_INIT(_sc) \ 108 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 109 "i2c", MTX_DEF) 110 111 static driver_t opal_i2c_driver = { 112 "iichb", 113 opal_i2c_methods, 114 sizeof(struct opal_i2c_softc), 115 }; 116 117 static int 118 opal_i2c_probe(device_t dev) 119 { 120 121 if (!(ofw_bus_is_compatible(dev, "ibm,opal-i2c"))) 122 return (ENXIO); 123 124 device_set_desc(dev, "opal-i2c"); 125 126 return (0); 127 } 128 129 static int 130 opal_i2c_attach(device_t dev) 131 { 132 struct opal_i2c_softc *sc; 133 int len; 134 135 sc = device_get_softc(dev); 136 sc->dev = dev; 137 138 len = OF_getproplen(ofw_bus_get_node(dev), "ibm,opal-id"); 139 if (len <= 0) 140 return (EINVAL); 141 OF_getencprop(ofw_bus_get_node(dev), "ibm,opal-id", &sc->opal_id, len); 142 143 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 144 device_printf(dev, "could not allocate iicbus instance\n"); 145 return (EINVAL); 146 } 147 148 I2C_LOCK_INIT(sc); 149 150 return (bus_generic_attach(dev)); 151 } 152 153 static int 154 opal_get_async_rc(struct opal_msg msg) 155 { 156 if (msg.msg_type != OPAL_MSG_ASYNC_COMP) 157 return OPAL_PARAMETER; 158 else 159 return htobe64(msg.params[1]); 160 } 161 162 static int 163 i2c_opal_send_request(uint32_t bus_id, struct opal_i2c_request *req) 164 { 165 struct opal_msg msg; 166 uint64_t token; 167 int rc; 168 169 token = opal_alloc_async_token(); 170 171 memset(&msg, 0, sizeof(msg)); 172 173 rc = opal_call(OPAL_I2C_REQUEST, token, bus_id, 174 vtophys(req)); 175 if (rc != OPAL_ASYNC_COMPLETION) 176 goto out; 177 178 rc = opal_wait_completion(&msg, sizeof(msg), token); 179 180 if (rc != OPAL_SUCCESS) 181 goto out; 182 183 rc = opal_get_async_rc(msg); 184 185 out: 186 opal_free_async_token(token); 187 188 return (rc); 189 } 190 191 static int 192 opal_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 193 { 194 struct opal_i2c_softc *sc; 195 int i, err = 0; 196 struct opal_i2c_request req; 197 198 sc = device_get_softc(dev); 199 200 memset(&req, 0, sizeof(req)); 201 202 I2C_LOCK(sc); 203 for (i = 0; i < nmsgs; i++) { 204 req.type = (msgs[i].flags & IIC_M_RD) ? 205 OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE; 206 req.addr = htobe16(msgs[i].slave >> 1); 207 req.size = htobe32(msgs[i].len); 208 req.buffer_pa = htobe64(pmap_kextract((uint64_t)msgs[i].buf)); 209 210 err = i2c_opal_send_request(sc->opal_id, &req); 211 } 212 I2C_UNLOCK(sc); 213 214 return (err); 215 } 216 217 static int 218 opal_i2c_callback(device_t dev, int index, caddr_t data) 219 { 220 int error = 0; 221 222 switch (index) { 223 case IIC_REQUEST_BUS: 224 break; 225 226 case IIC_RELEASE_BUS: 227 break; 228 229 default: 230 error = EINVAL; 231 } 232 233 return (error); 234 } 235 236 static phandle_t 237 opal_i2c_get_node(device_t bus, device_t dev) 238 { 239 240 /* Share controller node with iibus device. */ 241 return (ofw_bus_get_node(bus)); 242 } 243 244 DRIVER_MODULE(opal_i2c, opal_i2cm, opal_i2c_driver, NULL, NULL); 245 DRIVER_MODULE(iicbus, opal_i2c, iicbus_driver, NULL, NULL); 246 MODULE_DEPEND(opal_i2c, iicbus, 1, 1, 1); 247