1 /*- 2 * Copyright (c) 2017-2018 QCM Technologies. 3 * Copyright (c) 2017-2018 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include "opt_platform.h" 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <machine/bus.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 52 #include <dev/iicbus/iiconf.h> 53 #include <dev/iicbus/iicbus.h> 54 #include "iicbus_if.h" 55 56 #include "opal.h" 57 58 #ifdef FDT 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #endif 62 63 struct opal_i2c_softc 64 { 65 device_t dev; 66 device_t iicbus; 67 uint32_t opal_id; 68 struct mtx sc_mtx; 69 }; 70 71 /* OPAL I2C request */ 72 struct opal_i2c_request { 73 uint8_t type; 74 #define OPAL_I2C_RAW_READ 0 75 #define OPAL_I2C_RAW_WRITE 1 76 #define OPAL_I2C_SM_READ 2 77 #define OPAL_I2C_SM_WRITE 3 78 uint8_t flags; 79 uint8_t subaddr_sz; /* Max 4 */ 80 uint8_t reserved; 81 uint16_t addr; /* 7 or 10 bit address */ 82 uint16_t reserved2; 83 uint32_t subaddr; /* Sub-address if any */ 84 uint32_t size; /* Data size */ 85 uint64_t buffer_pa; /* Buffer real address */ 86 }; 87 88 static int opal_i2c_attach(device_t); 89 static int opal_i2c_callback(device_t, int, caddr_t); 90 static int opal_i2c_probe(device_t); 91 static int opal_i2c_transfer(device_t, struct iic_msg *, uint32_t); 92 static int i2c_opal_send_request(uint32_t, struct opal_i2c_request *); 93 94 static device_method_t opal_i2c_methods[] = { 95 /* Device interface */ 96 DEVMETHOD(device_probe, opal_i2c_probe), 97 DEVMETHOD(device_attach, opal_i2c_attach), 98 99 /* iicbus interface */ 100 DEVMETHOD(iicbus_callback, opal_i2c_callback), 101 DEVMETHOD(iicbus_transfer, opal_i2c_transfer), 102 DEVMETHOD_END 103 }; 104 105 #define I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 106 #define I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 107 #define I2C_LOCK_INIT(_sc) \ 108 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 109 "i2c", MTX_DEF) 110 111 static devclass_t opal_i2c_devclass; 112 113 static driver_t opal_i2c_driver = { 114 "i2c", 115 opal_i2c_methods, 116 sizeof(struct opal_i2c_softc), 117 }; 118 119 static int 120 opal_i2c_probe(device_t dev) 121 { 122 123 #ifdef FDT 124 if (!(ofw_bus_is_compatible(dev, "ibm,opal-i2c"))) 125 #endif 126 return (ENXIO); 127 128 device_set_desc(dev, "opal-i2c"); 129 130 return (0); 131 } 132 133 static int 134 opal_i2c_attach(device_t dev) 135 { 136 #ifdef FDT 137 struct opal_i2c_softc *sc; 138 int len; 139 140 sc = device_get_softc(dev); 141 sc->dev = dev; 142 143 len = OF_getproplen(ofw_bus_get_node(dev), "ibm,opal-id"); 144 if (len <= 0) 145 return (EINVAL); 146 OF_getencprop(ofw_bus_get_node(dev), "ibm,opal-id", &sc->opal_id, len); 147 148 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 149 device_printf(dev, "could not allocate iicbus instance\n"); 150 return (EINVAL); 151 } 152 153 I2C_LOCK_INIT(sc); 154 155 return (bus_generic_attach(dev)); 156 #else 157 return (ENXIO); 158 #endif 159 } 160 161 static int 162 opal_get_async_rc(struct opal_msg msg) 163 { 164 if (msg.msg_type != OPAL_MSG_ASYNC_COMP) 165 return OPAL_PARAMETER; 166 else 167 return htobe64(msg.params[1]); 168 } 169 170 static int 171 i2c_opal_send_request(uint32_t bus_id, struct opal_i2c_request *req) 172 { 173 struct opal_msg msg; 174 int token, rc; 175 176 /* 177 * XXX: 178 * Async tokens should be managed globally. Since there is 179 * only one place now, use hardcoded value. 180 */ 181 token = 0x112233; 182 183 memset(&msg, 0, sizeof(msg)); 184 185 rc = opal_call(OPAL_I2C_REQUEST, token, bus_id, 186 pmap_kextract((uint64_t)req)); 187 if (rc != OPAL_ASYNC_COMPLETION) 188 return (rc); 189 190 do { 191 rc = opal_call(OPAL_CHECK_ASYNC_COMPLETION, 192 pmap_kextract((uint64_t)&msg), sizeof(msg), token); 193 } while (rc == OPAL_BUSY); 194 195 if (rc != OPAL_SUCCESS) 196 return (rc); 197 198 rc = opal_get_async_rc(msg); 199 200 return rc; 201 } 202 203 static int 204 opal_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 205 { 206 struct opal_i2c_softc *sc; 207 int i, err = 0; 208 struct opal_i2c_request req; 209 210 sc = device_get_softc(dev); 211 212 memset(&req, 0, sizeof(req)); 213 214 /* XXX: Currently OPAL can parse only 1 message */ 215 if (nmsgs > 1) { 216 device_printf(dev, 217 "trying to parse %d messages, while only 1 is supported\n", nmsgs); 218 return (ENOMEM); 219 } 220 221 I2C_LOCK(sc); 222 for (i = 0; i < nmsgs; i++) { 223 req.type = (msgs[i].flags & IIC_M_RD) ? 224 OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE; 225 req.addr = htobe16(msgs[0].slave); 226 req.size = htobe32(msgs[0].len); 227 req.buffer_pa = htobe64(pmap_kextract((uint64_t)msgs[0].buf)); 228 229 err = i2c_opal_send_request(sc->opal_id, &req); 230 } 231 I2C_UNLOCK(sc); 232 233 return (err); 234 } 235 236 static int 237 opal_i2c_callback(device_t dev, int index, caddr_t data) 238 { 239 int error = 0; 240 241 switch (index) { 242 case IIC_REQUEST_BUS: 243 break; 244 245 case IIC_RELEASE_BUS: 246 break; 247 248 default: 249 error = EINVAL; 250 } 251 252 return (error); 253 } 254 255 DRIVER_MODULE(opal_i2c, opal_i2cm, opal_i2c_driver, opal_i2c_devclass, NULL, 256 NULL); 257 DRIVER_MODULE(iicbus, opal_i2c, iicbus_driver, iicbus_devclass, NULL, NULL); 258 MODULE_DEPEND(opal_i2c, iicbus, 1, 1, 1); 259