1 /*- 2 * Copyright (C) 2002 Benno Rice. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_ 29 #define _POWERPC_POWERMAC_UNINORTHVAR_H_ 30 31 struct uninorth_range { 32 u_int32_t pci_hi; 33 u_int32_t pci_mid; 34 u_int32_t pci_lo; 35 u_int32_t host; 36 u_int32_t size_hi; 37 u_int32_t size_lo; 38 }; 39 40 struct uninorth_range64 { 41 u_int32_t pci_hi; 42 u_int32_t pci_mid; 43 u_int32_t pci_lo; 44 u_int32_t host_hi; 45 u_int32_t host_lo; 46 u_int32_t size_hi; 47 u_int32_t size_lo; 48 }; 49 50 struct uninorth_softc { 51 device_t sc_dev; 52 phandle_t sc_node; 53 vm_offset_t sc_addr; 54 vm_offset_t sc_data; 55 int sc_bus; 56 struct uninorth_range sc_range[7]; 57 int sc_nrange; 58 int sc_iostart; 59 struct rman sc_io_rman; 60 struct rman sc_mem_rman; 61 bus_space_tag_t sc_iot; 62 bus_space_tag_t sc_memt; 63 bus_dma_tag_t sc_dmat; 64 struct ofw_bus_iinfo sc_pci_iinfo; 65 66 int sc_ver; 67 }; 68 69 struct unin_chip_softc { 70 u_int32_t sc_physaddr; 71 vm_offset_t sc_addr; 72 u_int32_t sc_size; 73 struct rman sc_mem_rman; 74 int sc_version; 75 }; 76 77 /* 78 * Format of a unin reg property entry. 79 */ 80 struct unin_chip_reg { 81 u_int32_t mr_base; 82 u_int32_t mr_size; 83 }; 84 85 /* 86 * Per unin device structure. 87 */ 88 struct unin_chip_devinfo { 89 int udi_interrupts[6]; 90 int udi_ninterrupts; 91 int udi_base; 92 struct ofw_bus_devinfo udi_obdinfo; 93 struct resource_list udi_resources; 94 }; 95 96 /* 97 * Version register 98 */ 99 #define UNIN_VERS 0x0 100 101 /* 102 * Clock-control register 103 */ 104 #define UNIN_CLOCKCNTL 0x20 105 #define UNIN_CLOCKCNTL_GMAC 0x2 106 107 /* 108 * Toggle registers 109 */ 110 #define UNIN_TOGGLE_REG 0xe0 111 #define UNIN_MPIC_RESET 0x2 112 #define UNIN_MPIC_OUTPUT_ENABLE 0x4 113 114 #endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */ 115