1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2002 Benno Rice. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/rman.h> 38 39 #include <dev/ofw/openfirm.h> 40 #include <dev/ofw/ofw_pci.h> 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 #include <dev/ofw/ofwpci.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr_machdep.h> 50 #include <machine/md_var.h> 51 #include <machine/pio.h> 52 #include <machine/resource.h> 53 54 #include <powerpc/powermac/uninorthvar.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include "pcib_if.h" 60 61 #define UNINORTH_DEBUG 0 62 63 /* 64 * Device interface. 65 */ 66 static int uninorth_probe(device_t); 67 static int uninorth_attach(device_t); 68 69 /* 70 * pcib interface. 71 */ 72 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int, 73 u_int, int); 74 static void uninorth_write_config(device_t, u_int, u_int, u_int, 75 u_int, u_int32_t, int); 76 77 /* 78 * Local routines. 79 */ 80 static int uninorth_enable_config(struct uninorth_softc *, u_int, 81 u_int, u_int, u_int); 82 83 /* 84 * Driver methods. 85 */ 86 static device_method_t uninorth_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_probe, uninorth_probe), 89 DEVMETHOD(device_attach, uninorth_attach), 90 91 /* pcib interface */ 92 DEVMETHOD(pcib_read_config, uninorth_read_config), 93 DEVMETHOD(pcib_write_config, uninorth_write_config), 94 95 DEVMETHOD_END 96 }; 97 98 static devclass_t uninorth_devclass; 99 100 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods, 101 sizeof(struct uninorth_softc), ofw_pci_driver); 102 DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0); 103 104 static int 105 uninorth_probe(device_t dev) 106 { 107 const char *type, *compatible; 108 109 type = ofw_bus_get_type(dev); 110 compatible = ofw_bus_get_compat(dev); 111 112 if (type == NULL || compatible == NULL) 113 return (ENXIO); 114 115 if (strcmp(type, "pci") != 0) 116 return (ENXIO); 117 118 if (strcmp(compatible, "uni-north") == 0) { 119 device_set_desc(dev, "Apple UniNorth Host-PCI bridge"); 120 return (0); 121 } else if (strcmp(compatible, "u3-agp") == 0) { 122 device_set_desc(dev, "Apple U3 Host-AGP bridge"); 123 return (0); 124 } else if (strcmp(compatible, "u4-pcie") == 0) { 125 device_set_desc(dev, "IBM CPC945 PCI Express Root"); 126 return (0); 127 } 128 129 return (ENXIO); 130 } 131 132 static int 133 uninorth_attach(device_t dev) 134 { 135 struct uninorth_softc *sc; 136 const char *compatible; 137 phandle_t node; 138 uint32_t reg[3]; 139 uint64_t regbase; 140 cell_t acells; 141 142 node = ofw_bus_get_node(dev); 143 sc = device_get_softc(dev); 144 145 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 146 return (ENXIO); 147 148 sc->sc_ver = 0; 149 compatible = ofw_bus_get_compat(dev); 150 if (strcmp(compatible, "u3-agp") == 0) 151 sc->sc_ver = 3; 152 if (strcmp(compatible, "u4-pcie") == 0) 153 sc->sc_ver = 4; 154 155 acells = 1; 156 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells)); 157 158 regbase = reg[0]; 159 if (acells == 2) { 160 regbase <<= 32; 161 regbase |= reg[1]; 162 } 163 164 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE); 165 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE); 166 167 return (ofw_pci_attach(dev)); 168 } 169 170 static u_int32_t 171 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 172 int width) 173 { 174 struct uninorth_softc *sc; 175 vm_offset_t caoff; 176 177 sc = device_get_softc(dev); 178 caoff = sc->sc_data + (reg & 0x07); 179 180 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) { 181 switch (width) { 182 case 1: 183 return (in8rb(caoff)); 184 break; 185 case 2: 186 return (in16rb(caoff)); 187 break; 188 case 4: 189 return (in32rb(caoff)); 190 break; 191 } 192 } 193 194 return (0xffffffff); 195 } 196 197 static void 198 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func, 199 u_int reg, u_int32_t val, int width) 200 { 201 struct uninorth_softc *sc; 202 vm_offset_t caoff; 203 204 sc = device_get_softc(dev); 205 caoff = sc->sc_data + (reg & 0x07); 206 207 if (uninorth_enable_config(sc, bus, slot, func, reg)) { 208 switch (width) { 209 case 1: 210 out8rb(caoff, val); 211 break; 212 case 2: 213 out16rb(caoff, val); 214 break; 215 case 4: 216 out32rb(caoff, val); 217 break; 218 } 219 } 220 } 221 222 static int 223 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot, 224 u_int func, u_int reg) 225 { 226 uint32_t cfgval; 227 uint32_t pass; 228 229 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev), 230 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) { 231 if (pass == slot) 232 return (0); 233 } 234 235 /* 236 * Issue type 0 configuration space accesses for the root bus. 237 * 238 * NOTE: On U4, issue only type 1 accesses. There is a secret 239 * PCI Express <-> PCI Express bridge not present in the device tree, 240 * and we need to route all of our configuration space through it. 241 */ 242 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) { 243 /* 244 * No slots less than 11 on the primary bus on U3 and lower 245 */ 246 if (slot < 11) 247 return (0); 248 249 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc); 250 } else { 251 cfgval = (bus << 16) | (slot << 11) | (func << 8) | 252 (reg & 0xfc) | 1; 253 } 254 255 /* Set extended register bits on U4 */ 256 if (sc->sc_ver == 4) 257 cfgval |= (reg >> 8) << 28; 258 259 do { 260 out32rb(sc->sc_addr, cfgval); 261 } while (in32rb(sc->sc_addr) != cfgval); 262 263 return (1); 264 } 265 266