1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2002 Benno Rice. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 41 #include <dev/ofw/openfirm.h> 42 #include <dev/ofw/ofw_pci.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #include <dev/ofw/ofwpci.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr_machdep.h> 52 #include <machine/md_var.h> 53 #include <machine/pio.h> 54 #include <machine/resource.h> 55 56 #include <powerpc/powermac/uninorthvar.h> 57 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 61 #include "pcib_if.h" 62 63 #define UNINORTH_DEBUG 0 64 65 /* 66 * Device interface. 67 */ 68 static int uninorth_probe(device_t); 69 static int uninorth_attach(device_t); 70 71 /* 72 * pcib interface. 73 */ 74 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int, 75 u_int, int); 76 static void uninorth_write_config(device_t, u_int, u_int, u_int, 77 u_int, u_int32_t, int); 78 79 /* 80 * Local routines. 81 */ 82 static int uninorth_enable_config(struct uninorth_softc *, u_int, 83 u_int, u_int, u_int); 84 85 /* 86 * Driver methods. 87 */ 88 static device_method_t uninorth_methods[] = { 89 /* Device interface */ 90 DEVMETHOD(device_probe, uninorth_probe), 91 DEVMETHOD(device_attach, uninorth_attach), 92 93 /* pcib interface */ 94 DEVMETHOD(pcib_read_config, uninorth_read_config), 95 DEVMETHOD(pcib_write_config, uninorth_write_config), 96 97 DEVMETHOD_END 98 }; 99 100 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods, 101 sizeof(struct uninorth_softc), ofw_pcib_driver); 102 EARLY_DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, 0, 0, BUS_PASS_BUS); 103 104 static int 105 uninorth_probe(device_t dev) 106 { 107 const char *type, *compatible; 108 109 type = ofw_bus_get_type(dev); 110 compatible = ofw_bus_get_compat(dev); 111 112 if (type == NULL || compatible == NULL) 113 return (ENXIO); 114 115 if (strcmp(type, "pci") != 0) 116 return (ENXIO); 117 118 if (strcmp(compatible, "uni-north") == 0) { 119 device_set_desc(dev, "Apple UniNorth Host-PCI bridge"); 120 return (0); 121 } else if (strcmp(compatible, "u3-agp") == 0) { 122 device_set_desc(dev, "Apple U3 Host-AGP bridge"); 123 return (0); 124 } else if (strcmp(compatible, "u4-pcie") == 0) { 125 device_set_desc(dev, "IBM CPC945 PCI Express Root"); 126 return (0); 127 } 128 129 return (ENXIO); 130 } 131 132 static int 133 uninorth_attach(device_t dev) 134 { 135 struct uninorth_softc *sc; 136 const char *compatible; 137 const char *name; 138 phandle_t node; 139 uint32_t reg[3]; 140 uint64_t regbase; 141 cell_t acells; 142 int unit; 143 144 node = ofw_bus_get_node(dev); 145 sc = device_get_softc(dev); 146 name = device_get_name(dev); 147 unit = device_get_unit(dev); 148 149 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 150 return (ENXIO); 151 152 sc->sc_ver = 0; 153 compatible = ofw_bus_get_compat(dev); 154 if (strcmp(compatible, "u3-agp") == 0) 155 sc->sc_ver = 3; 156 if (strcmp(compatible, "u4-pcie") == 0) 157 sc->sc_ver = 4; 158 159 acells = 1; 160 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells)); 161 162 regbase = reg[0]; 163 if (acells == 2) { 164 regbase <<= 32; 165 regbase |= reg[1]; 166 } 167 168 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE); 169 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE); 170 171 if (resource_int_value(name, unit, "skipslot", &sc->sc_skipslot) != 0) 172 sc->sc_skipslot = -1; 173 174 mtx_init(&sc->sc_cfg_mtx, "uninorth pcicfg", NULL, MTX_SPIN); 175 176 return (ofw_pcib_attach(dev)); 177 } 178 179 static u_int32_t 180 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 181 int width) 182 { 183 struct uninorth_softc *sc; 184 vm_offset_t caoff; 185 u_int32_t val; 186 187 sc = device_get_softc(dev); 188 caoff = sc->sc_data + (reg & 0x07); 189 val = 0xffffffff; 190 191 mtx_lock_spin(&sc->sc_cfg_mtx); 192 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) { 193 switch (width) { 194 case 1: 195 val = in8rb(caoff); 196 break; 197 case 2: 198 val = in16rb(caoff); 199 break; 200 case 4: 201 val = in32rb(caoff); 202 break; 203 } 204 } 205 mtx_unlock_spin(&sc->sc_cfg_mtx); 206 207 return (val); 208 } 209 210 static void 211 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func, 212 u_int reg, u_int32_t val, int width) 213 { 214 struct uninorth_softc *sc; 215 vm_offset_t caoff; 216 217 sc = device_get_softc(dev); 218 caoff = sc->sc_data + (reg & 0x07); 219 220 mtx_lock_spin(&sc->sc_cfg_mtx); 221 if (uninorth_enable_config(sc, bus, slot, func, reg)) { 222 switch (width) { 223 case 1: 224 out8rb(caoff, val); 225 break; 226 case 2: 227 out16rb(caoff, val); 228 break; 229 case 4: 230 out32rb(caoff, val); 231 break; 232 } 233 } 234 mtx_unlock_spin(&sc->sc_cfg_mtx); 235 } 236 237 static int 238 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot, 239 u_int func, u_int reg) 240 { 241 uint32_t cfgval; 242 243 mtx_assert(&sc->sc_cfg_mtx, MA_OWNED); 244 245 if (sc->sc_skipslot == slot) 246 return (0); 247 248 /* 249 * Issue type 0 configuration space accesses for the root bus. 250 * 251 * NOTE: On U4, issue only type 1 accesses. There is a secret 252 * PCI Express <-> PCI Express bridge not present in the device tree, 253 * and we need to route all of our configuration space through it. 254 */ 255 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) { 256 /* 257 * No slots less than 11 on the primary bus on U3 and lower 258 */ 259 if (slot < 11) 260 return (0); 261 262 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc); 263 } else { 264 cfgval = (bus << 16) | (slot << 11) | (func << 8) | 265 (reg & 0xfc) | 1; 266 } 267 268 /* Set extended register bits on U4 */ 269 if (sc->sc_ver == 4) 270 cfgval |= (reg >> 8) << 28; 271 272 do { 273 out32rb(sc->sc_addr, cfgval); 274 } while (in32rb(sc->sc_addr) != cfgval); 275 276 return (1); 277 } 278