1 /*- 2 * Copyright (C) 2002 Benno Rice. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/module.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/rman.h> 36 37 #include <dev/ofw/openfirm.h> 38 #include <dev/ofw/ofw_pci.h> 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 #include <dev/ofw/ofwpci.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcireg.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr_machdep.h> 48 #include <machine/md_var.h> 49 #include <machine/pio.h> 50 #include <machine/resource.h> 51 52 #include <powerpc/powermac/uninorthvar.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include "pcib_if.h" 58 59 #define UNINORTH_DEBUG 0 60 61 /* 62 * Device interface. 63 */ 64 static int uninorth_probe(device_t); 65 static int uninorth_attach(device_t); 66 67 /* 68 * pcib interface. 69 */ 70 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int, 71 u_int, int); 72 static void uninorth_write_config(device_t, u_int, u_int, u_int, 73 u_int, u_int32_t, int); 74 75 /* 76 * Local routines. 77 */ 78 static int uninorth_enable_config(struct uninorth_softc *, u_int, 79 u_int, u_int, u_int); 80 81 /* 82 * Driver methods. 83 */ 84 static device_method_t uninorth_methods[] = { 85 /* Device interface */ 86 DEVMETHOD(device_probe, uninorth_probe), 87 DEVMETHOD(device_attach, uninorth_attach), 88 89 /* pcib interface */ 90 DEVMETHOD(pcib_read_config, uninorth_read_config), 91 DEVMETHOD(pcib_write_config, uninorth_write_config), 92 93 DEVMETHOD_END 94 }; 95 96 static devclass_t uninorth_devclass; 97 98 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods, 99 sizeof(struct uninorth_softc), ofw_pci_driver); 100 DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0); 101 102 static int 103 uninorth_probe(device_t dev) 104 { 105 const char *type, *compatible; 106 107 type = ofw_bus_get_type(dev); 108 compatible = ofw_bus_get_compat(dev); 109 110 if (type == NULL || compatible == NULL) 111 return (ENXIO); 112 113 if (strcmp(type, "pci") != 0) 114 return (ENXIO); 115 116 if (strcmp(compatible, "uni-north") == 0) { 117 device_set_desc(dev, "Apple UniNorth Host-PCI bridge"); 118 return (0); 119 } else if (strcmp(compatible, "u3-agp") == 0) { 120 device_set_desc(dev, "Apple U3 Host-AGP bridge"); 121 return (0); 122 } else if (strcmp(compatible, "u4-pcie") == 0) { 123 device_set_desc(dev, "IBM CPC945 PCI Express Root"); 124 return (0); 125 } 126 127 return (ENXIO); 128 } 129 130 static int 131 uninorth_attach(device_t dev) 132 { 133 struct uninorth_softc *sc; 134 const char *compatible; 135 phandle_t node; 136 uint32_t reg[3]; 137 uint64_t regbase; 138 cell_t acells; 139 140 node = ofw_bus_get_node(dev); 141 sc = device_get_softc(dev); 142 143 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 144 return (ENXIO); 145 146 sc->sc_ver = 0; 147 compatible = ofw_bus_get_compat(dev); 148 if (strcmp(compatible, "u3-agp") == 0) 149 sc->sc_ver = 3; 150 if (strcmp(compatible, "u4-pcie") == 0) 151 sc->sc_ver = 4; 152 153 acells = 1; 154 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells)); 155 156 regbase = reg[0]; 157 if (acells == 2) { 158 regbase <<= 32; 159 regbase |= reg[1]; 160 } 161 162 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE); 163 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE); 164 165 return (ofw_pci_attach(dev)); 166 } 167 168 static u_int32_t 169 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 170 int width) 171 { 172 struct uninorth_softc *sc; 173 vm_offset_t caoff; 174 175 sc = device_get_softc(dev); 176 caoff = sc->sc_data + (reg & 0x07); 177 178 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) { 179 switch (width) { 180 case 1: 181 return (in8rb(caoff)); 182 break; 183 case 2: 184 return (in16rb(caoff)); 185 break; 186 case 4: 187 return (in32rb(caoff)); 188 break; 189 } 190 } 191 192 return (0xffffffff); 193 } 194 195 static void 196 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func, 197 u_int reg, u_int32_t val, int width) 198 { 199 struct uninorth_softc *sc; 200 vm_offset_t caoff; 201 202 sc = device_get_softc(dev); 203 caoff = sc->sc_data + (reg & 0x07); 204 205 if (uninorth_enable_config(sc, bus, slot, func, reg)) { 206 switch (width) { 207 case 1: 208 out8rb(caoff, val); 209 break; 210 case 2: 211 out16rb(caoff, val); 212 break; 213 case 4: 214 out32rb(caoff, val); 215 break; 216 } 217 } 218 } 219 220 static int 221 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot, 222 u_int func, u_int reg) 223 { 224 uint32_t cfgval; 225 uint32_t pass; 226 227 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev), 228 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) { 229 if (pass == slot) 230 return (0); 231 } 232 233 /* 234 * Issue type 0 configuration space accesses for the root bus. 235 * 236 * NOTE: On U4, issue only type 1 accesses. There is a secret 237 * PCI Express <-> PCI Express bridge not present in the device tree, 238 * and we need to route all of our configuration space through it. 239 */ 240 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) { 241 /* 242 * No slots less than 11 on the primary bus on U3 and lower 243 */ 244 if (slot < 11) 245 return (0); 246 247 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc); 248 } else { 249 cfgval = (bus << 16) | (slot << 11) | (func << 8) | 250 (reg & 0xfc) | 1; 251 } 252 253 /* Set extended register bits on U4 */ 254 if (sc->sc_ver == 4) 255 cfgval |= (reg >> 8) << 28; 256 257 do { 258 out32rb(sc->sc_addr, cfgval); 259 } while (in32rb(sc->sc_addr) != cfgval); 260 261 return (1); 262 } 263 264