1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2002 Benno Rice.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/module.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/mutex.h>
36 #include <sys/rman.h>
37
38 #include <dev/ofw/openfirm.h>
39 #include <dev/ofw/ofw_pci.h>
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42 #include <dev/ofw/ofwpci.h>
43
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46
47 #include <machine/bus.h>
48 #include <machine/intr_machdep.h>
49 #include <machine/md_var.h>
50 #include <machine/pio.h>
51 #include <machine/resource.h>
52
53 #include <powerpc/powermac/uninorthvar.h>
54
55 #include <vm/vm.h>
56 #include <vm/pmap.h>
57
58 #include "pcib_if.h"
59
60 #define UNINORTH_DEBUG 0
61
62 /*
63 * Device interface.
64 */
65 static int uninorth_probe(device_t);
66 static int uninorth_attach(device_t);
67
68 /*
69 * pcib interface.
70 */
71 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
72 u_int, int);
73 static void uninorth_write_config(device_t, u_int, u_int, u_int,
74 u_int, u_int32_t, int);
75
76 /*
77 * Local routines.
78 */
79 static int uninorth_enable_config(struct uninorth_softc *, u_int,
80 u_int, u_int, u_int);
81
82 /*
83 * Driver methods.
84 */
85 static device_method_t uninorth_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_probe, uninorth_probe),
88 DEVMETHOD(device_attach, uninorth_attach),
89
90 /* pcib interface */
91 DEVMETHOD(pcib_read_config, uninorth_read_config),
92 DEVMETHOD(pcib_write_config, uninorth_write_config),
93
94 DEVMETHOD_END
95 };
96
97 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
98 sizeof(struct uninorth_softc), ofw_pcib_driver);
99 EARLY_DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, 0, 0, BUS_PASS_BUS);
100
101 static int
uninorth_probe(device_t dev)102 uninorth_probe(device_t dev)
103 {
104 const char *type, *compatible;
105
106 type = ofw_bus_get_type(dev);
107 compatible = ofw_bus_get_compat(dev);
108
109 if (type == NULL || compatible == NULL)
110 return (ENXIO);
111
112 if (strcmp(type, "pci") != 0)
113 return (ENXIO);
114
115 if (strcmp(compatible, "uni-north") == 0) {
116 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
117 return (0);
118 } else if (strcmp(compatible, "u3-agp") == 0) {
119 device_set_desc(dev, "Apple U3 Host-AGP bridge");
120 return (0);
121 } else if (strcmp(compatible, "u4-pcie") == 0) {
122 device_set_desc(dev, "IBM CPC945 PCI Express Root");
123 return (0);
124 }
125
126 return (ENXIO);
127 }
128
129 static int
uninorth_attach(device_t dev)130 uninorth_attach(device_t dev)
131 {
132 struct uninorth_softc *sc;
133 const char *compatible;
134 const char *name;
135 phandle_t node;
136 uint32_t reg[3];
137 uint64_t regbase;
138 cell_t acells;
139 int unit;
140
141 node = ofw_bus_get_node(dev);
142 sc = device_get_softc(dev);
143 name = device_get_name(dev);
144 unit = device_get_unit(dev);
145
146 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
147 return (ENXIO);
148
149 sc->sc_ver = 0;
150 compatible = ofw_bus_get_compat(dev);
151 if (strcmp(compatible, "u3-agp") == 0)
152 sc->sc_ver = 3;
153 if (strcmp(compatible, "u4-pcie") == 0)
154 sc->sc_ver = 4;
155
156 acells = 1;
157 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells));
158
159 regbase = reg[0];
160 if (acells == 2) {
161 regbase <<= 32;
162 regbase |= reg[1];
163 }
164
165 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE);
166 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE);
167
168 if (resource_int_value(name, unit, "skipslot", &sc->sc_skipslot) != 0)
169 sc->sc_skipslot = -1;
170
171 mtx_init(&sc->sc_cfg_mtx, "uninorth pcicfg", NULL, MTX_SPIN);
172
173 return (ofw_pcib_attach(dev));
174 }
175
176 static u_int32_t
uninorth_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int width)177 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
178 int width)
179 {
180 struct uninorth_softc *sc;
181 vm_offset_t caoff;
182 u_int32_t val;
183
184 sc = device_get_softc(dev);
185 caoff = sc->sc_data + (reg & 0x07);
186 val = 0xffffffff;
187
188 mtx_lock_spin(&sc->sc_cfg_mtx);
189 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
190 switch (width) {
191 case 1:
192 val = in8rb(caoff);
193 break;
194 case 2:
195 val = in16rb(caoff);
196 break;
197 case 4:
198 val = in32rb(caoff);
199 break;
200 }
201 }
202 mtx_unlock_spin(&sc->sc_cfg_mtx);
203
204 return (val);
205 }
206
207 static void
uninorth_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,u_int32_t val,int width)208 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
209 u_int reg, u_int32_t val, int width)
210 {
211 struct uninorth_softc *sc;
212 vm_offset_t caoff;
213
214 sc = device_get_softc(dev);
215 caoff = sc->sc_data + (reg & 0x07);
216
217 mtx_lock_spin(&sc->sc_cfg_mtx);
218 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
219 switch (width) {
220 case 1:
221 out8rb(caoff, val);
222 break;
223 case 2:
224 out16rb(caoff, val);
225 break;
226 case 4:
227 out32rb(caoff, val);
228 break;
229 }
230 }
231 mtx_unlock_spin(&sc->sc_cfg_mtx);
232 }
233
234 static int
uninorth_enable_config(struct uninorth_softc * sc,u_int bus,u_int slot,u_int func,u_int reg)235 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
236 u_int func, u_int reg)
237 {
238 uint32_t cfgval;
239
240 mtx_assert(&sc->sc_cfg_mtx, MA_OWNED);
241
242 if (sc->sc_skipslot == slot)
243 return (0);
244
245 /*
246 * Issue type 0 configuration space accesses for the root bus.
247 *
248 * NOTE: On U4, issue only type 1 accesses. There is a secret
249 * PCI Express <-> PCI Express bridge not present in the device tree,
250 * and we need to route all of our configuration space through it.
251 */
252 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
253 /*
254 * No slots less than 11 on the primary bus on U3 and lower
255 */
256 if (slot < 11)
257 return (0);
258
259 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
260 } else {
261 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
262 (reg & 0xfc) | 1;
263 }
264
265 /* Set extended register bits on U4 */
266 if (sc->sc_ver == 4)
267 cfgval |= (reg >> 8) << 28;
268
269 do {
270 out32rb(sc->sc_addr, cfgval);
271 } while (in32rb(sc->sc_addr) != cfgval);
272
273 return (1);
274 }
275