xref: /freebsd/sys/powerpc/powermac/uninorth.c (revision d2f1e0e4a589fb49f3ac9488def99497465b39ac) 
1 /*-
2  * Copyright (C) 2002 Benno Rice.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/module.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 
35 #include <dev/ofw/openfirm.h>
36 #include <dev/ofw/ofw_pci.h>
37 #include <dev/ofw/ofw_bus.h>
38 #include <dev/ofw/ofw_bus_subr.h>
39 
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42 
43 #include <machine/bus.h>
44 #include <machine/md_var.h>
45 #include <machine/pio.h>
46 #include <machine/resource.h>
47 
48 #include <sys/rman.h>
49 
50 #include <powerpc/powermac/uninorthvar.h>
51 
52 #include <vm/vm.h>
53 #include <vm/pmap.h>
54 
55 #include "pcib_if.h"
56 
57 #define	UNINORTH_DEBUG	0
58 
59 /*
60  * Device interface.
61  */
62 static int		uninorth_probe(device_t);
63 static int		uninorth_attach(device_t);
64 
65 /*
66  * Bus interface.
67  */
68 static int		uninorth_read_ivar(device_t, device_t, int,
69 			    uintptr_t *);
70 static struct		resource * uninorth_alloc_resource(device_t bus,
71 			    device_t child, int type, int *rid, u_long start,
72 			    u_long end, u_long count, u_int flags);
73 static int		uninorth_activate_resource(device_t bus, device_t child,
74 			    int type, int rid, struct resource *res);
75 
76 /*
77  * pcib interface.
78  */
79 static int		uninorth_maxslots(device_t);
80 static u_int32_t	uninorth_read_config(device_t, u_int, u_int, u_int,
81 			    u_int, int);
82 static void		uninorth_write_config(device_t, u_int, u_int, u_int,
83 			    u_int, u_int32_t, int);
84 static int		uninorth_route_interrupt(device_t, device_t, int);
85 
86 /*
87  * OFW Bus interface
88  */
89 
90 static phandle_t	 uninorth_get_node(device_t bus, device_t dev);
91 
92 /*
93  * Local routines.
94  */
95 static int		uninorth_enable_config(struct uninorth_softc *, u_int,
96 			    u_int, u_int, u_int);
97 static void		unin_enable_gmac(void);
98 
99 /*
100  * Driver methods.
101  */
102 static device_method_t	uninorth_methods[] = {
103 	/* Device interface */
104 	DEVMETHOD(device_probe,		uninorth_probe),
105 	DEVMETHOD(device_attach,	uninorth_attach),
106 
107 	/* Bus interface */
108 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
109 	DEVMETHOD(bus_read_ivar,	uninorth_read_ivar),
110 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
111 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
112 	DEVMETHOD(bus_alloc_resource,	uninorth_alloc_resource),
113 	DEVMETHOD(bus_activate_resource,	uninorth_activate_resource),
114 
115 	/* pcib interface */
116 	DEVMETHOD(pcib_maxslots,	uninorth_maxslots),
117 	DEVMETHOD(pcib_read_config,	uninorth_read_config),
118 	DEVMETHOD(pcib_write_config,	uninorth_write_config),
119 	DEVMETHOD(pcib_route_interrupt,	uninorth_route_interrupt),
120 
121 	/* ofw_bus interface */
122 	DEVMETHOD(ofw_bus_get_node,     uninorth_get_node),
123 
124 	{ 0, 0 }
125 };
126 
127 static driver_t	uninorth_driver = {
128 	"pcib",
129 	uninorth_methods,
130 	sizeof(struct uninorth_softc)
131 };
132 
133 static devclass_t	uninorth_devclass;
134 
135 DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
136 
137 static int
138 uninorth_probe(device_t dev)
139 {
140 	const char	*type, *compatible;
141 
142 	type = ofw_bus_get_type(dev);
143 	compatible = ofw_bus_get_compat(dev);
144 
145 	if (type == NULL || compatible == NULL)
146 		return (ENXIO);
147 
148 	if (strcmp(type, "pci") != 0)
149 		return (ENXIO);
150 
151 	if (strcmp(compatible, "uni-north") == 0) {
152 		device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
153 		return (0);
154 	} else if (strcmp(compatible,"u3-agp") == 0) {
155 		device_set_desc(dev, "Apple U3 Host-AGP bridge");
156 		return (0);
157 	}
158 
159 	return (ENXIO);
160 }
161 
162 static int
163 uninorth_attach(device_t dev)
164 {
165 	struct		uninorth_softc *sc;
166 	const char	*compatible;
167 	phandle_t	node, child;
168 	u_int32_t	reg[2], busrange[2];
169 	struct		uninorth_range *rp, *io, *mem[2];
170 	int		nmem, i, error;
171 
172 	node = ofw_bus_get_node(dev);
173 	sc = device_get_softc(dev);
174 
175 	if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
176 		return (ENXIO);
177 
178 	if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
179 		return (ENXIO);
180 
181 	sc->sc_u3 = 0;
182 	compatible = ofw_bus_get_compat(dev);
183 	if (strcmp(compatible,"u3-agp") == 0)
184 		sc->sc_u3 = 1;
185 
186 	sc->sc_dev = dev;
187 	sc->sc_node = node;
188 	if (sc->sc_u3) {
189 	   sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
190 	   sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
191 	} else {
192 	   sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
193 	   sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
194 	}
195 	sc->sc_bus = busrange[0];
196 
197 	bzero(sc->sc_range, sizeof(sc->sc_range));
198 	if (sc->sc_u3) {
199 		/*
200 		 * On Apple U3 systems, we have an otherwise standard
201 		 * Uninorth controller driving AGP. The one difference
202 		 * is that it uses a new PCI ranges format, so do the
203 		 * translation.
204 		 */
205 
206 		struct uninorth_range64 range64[6];
207 		bzero(range64, sizeof(range64));
208 
209 		sc->sc_nrange = OF_getprop(node, "ranges", range64,
210 		    sizeof(range64));
211 		for (i = 0; range64[i].pci_hi != 0; i++) {
212 			sc->sc_range[i].pci_hi = range64[i].pci_hi;
213 			sc->sc_range[i].pci_mid = range64[i].pci_mid;
214 			sc->sc_range[i].pci_lo = range64[i].pci_lo;
215 			sc->sc_range[i].host = range64[i].host_lo;
216 			sc->sc_range[i].size_hi = range64[i].size_hi;
217 			sc->sc_range[i].size_lo = range64[i].size_lo;
218 		}
219 	} else {
220 		sc->sc_nrange = OF_getprop(node, "ranges", sc->sc_range,
221 		    sizeof(sc->sc_range));
222 	}
223 
224 	if (sc->sc_nrange == -1) {
225 		device_printf(dev, "could not get ranges\n");
226 		return (ENXIO);
227 	}
228 
229 	sc->sc_range[6].pci_hi = 0;
230 	io = NULL;
231 	nmem = 0;
232 
233 	for (rp = sc->sc_range; rp->pci_hi != 0; rp++) {
234 		switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
235 		case OFW_PCI_PHYS_HI_SPACE_CONFIG:
236 			break;
237 		case OFW_PCI_PHYS_HI_SPACE_IO:
238 			io = rp;
239 			break;
240 		case OFW_PCI_PHYS_HI_SPACE_MEM32:
241 			mem[nmem] = rp;
242 			nmem++;
243 			break;
244 		case OFW_PCI_PHYS_HI_SPACE_MEM64:
245 			break;
246 		}
247 	}
248 
249 	if (io == NULL) {
250 		device_printf(dev, "can't find io range\n");
251 		return (ENXIO);
252 	}
253 	sc->sc_io_rman.rm_type = RMAN_ARRAY;
254 	sc->sc_io_rman.rm_descr = "UniNorth PCI I/O Ports";
255 	sc->sc_iostart = io->host;
256 	if (rman_init(&sc->sc_io_rman) != 0 ||
257 	    rman_manage_region(&sc->sc_io_rman, io->pci_lo,
258 	    io->pci_lo + io->size_lo - 1) != 0) {
259 		panic("uninorth_attach: failed to set up I/O rman");
260 	}
261 
262 	if (nmem == 0) {
263 		device_printf(dev, "can't find mem ranges\n");
264 		return (ENXIO);
265 	}
266 	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
267 	sc->sc_mem_rman.rm_descr = "UniNorth PCI Memory";
268 	error = rman_init(&sc->sc_mem_rman);
269 	if (error) {
270 		device_printf(dev, "rman_init() failed. error = %d\n", error);
271 		return (error);
272 	}
273 	for (i = 0; i < nmem; i++) {
274 		error = rman_manage_region(&sc->sc_mem_rman, mem[i]->pci_lo,
275 		    mem[i]->pci_lo + mem[i]->size_lo - 1);
276 		if (error) {
277 			device_printf(dev,
278 			    "rman_manage_region() failed. error = %d\n", error);
279 			return (error);
280 		}
281 	}
282 
283 	/*
284 	 * Enable the GMAC Ethernet cell if Open Firmware says it is
285 	 * used.
286 	 */
287 	for (child = OF_child(node); child; child = OF_peer(child)) {
288 		char compat[32];
289 
290 		memset(compat, 0, sizeof(compat));
291 		OF_getprop(child, "compatible", compat, sizeof(compat));
292 		if (strcmp(compat, "gmac") == 0) {
293 			unin_enable_gmac();
294 		}
295 	}
296 
297 	ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(cell_t));
298 
299 	device_add_child(dev, "pci", device_get_unit(dev));
300 	return (bus_generic_attach(dev));
301 }
302 
303 static int
304 uninorth_maxslots(device_t dev)
305 {
306 
307 	return (PCI_SLOTMAX);
308 }
309 
310 static u_int32_t
311 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
312     int width)
313 {
314 	struct		uninorth_softc *sc;
315 	vm_offset_t	caoff;
316 
317 	sc = device_get_softc(dev);
318 	caoff = sc->sc_data + (reg & 0x07);
319 
320 	if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
321 		switch (width) {
322 		case 1:
323 			return (in8rb(caoff));
324 			break;
325 		case 2:
326 			return (in16rb(caoff));
327 			break;
328 		case 4:
329 			return (in32rb(caoff));
330 			break;
331 		}
332 	}
333 
334 	return (0xffffffff);
335 }
336 
337 static void
338 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
339     u_int reg, u_int32_t val, int width)
340 {
341 	struct		uninorth_softc *sc;
342 	vm_offset_t	caoff;
343 
344 	sc = device_get_softc(dev);
345 	caoff = sc->sc_data + (reg & 0x07);
346 
347 	if (uninorth_enable_config(sc, bus, slot, func, reg)) {
348 		switch (width) {
349 		case 1:
350 			out8rb(caoff, val);
351 			break;
352 		case 2:
353 			out16rb(caoff, val);
354 			break;
355 		case 4:
356 			out32rb(caoff, val);
357 			break;
358 		}
359 	}
360 }
361 
362 static int
363 uninorth_route_interrupt(device_t bus, device_t dev, int pin)
364 {
365 	struct uninorth_softc *sc;
366 	struct ofw_pci_register reg;
367 	uint32_t pintr, mintr;
368 	uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
369 
370 	sc = device_get_softc(bus);
371 	pintr = pin;
372 	if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
373 	    sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
374 		return (mintr);
375 
376 	/* Maybe it's a real interrupt, not an intpin */
377 	if (pin > 4)
378 		return (pin);
379 
380 	device_printf(bus, "could not route pin %d for device %d.%d\n",
381 	    pin, pci_get_slot(dev), pci_get_function(dev));
382 	return (PCI_INVALID_IRQ);
383 }
384 
385 static int
386 uninorth_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
387 {
388 	struct	uninorth_softc *sc;
389 
390 	sc = device_get_softc(dev);
391 
392 	switch (which) {
393 	case PCIB_IVAR_DOMAIN:
394 		*result = device_get_unit(dev);
395 		return (0);
396 	case PCIB_IVAR_BUS:
397 		*result = sc->sc_bus;
398 		return (0);
399 	}
400 
401 	return (ENOENT);
402 }
403 
404 static struct resource *
405 uninorth_alloc_resource(device_t bus, device_t child, int type, int *rid,
406     u_long start, u_long end, u_long count, u_int flags)
407 {
408 	struct			uninorth_softc *sc;
409 	struct			resource *rv;
410 	struct			rman *rm;
411 	int			needactivate;
412 
413 	needactivate = flags & RF_ACTIVE;
414 	flags &= ~RF_ACTIVE;
415 
416 	sc = device_get_softc(bus);
417 
418 	switch (type) {
419 	case SYS_RES_MEMORY:
420 		rm = &sc->sc_mem_rman;
421 		break;
422 
423 	case SYS_RES_IOPORT:
424 		rm = &sc->sc_io_rman;
425 		break;
426 
427 	case SYS_RES_IRQ:
428 		return (bus_alloc_resource(bus, type, rid, start, end, count,
429 		    flags));
430 
431 	default:
432 		device_printf(bus, "unknown resource request from %s\n",
433 		    device_get_nameunit(child));
434 		return (NULL);
435 	}
436 
437 	rv = rman_reserve_resource(rm, start, end, count, flags, child);
438 	if (rv == NULL) {
439 		device_printf(bus, "failed to reserve resource for %s\n",
440 		    device_get_nameunit(child));
441 		return (NULL);
442 	}
443 
444 	rman_set_rid(rv, *rid);
445 
446 	if (needactivate) {
447 		if (bus_activate_resource(child, type, *rid, rv) != 0) {
448 			device_printf(bus,
449 			    "failed to activate resource for %s\n",
450 			    device_get_nameunit(child));
451 			rman_release_resource(rv);
452 			return (NULL);
453 		}
454 	}
455 
456 	return (rv);
457 }
458 
459 static int
460 uninorth_activate_resource(device_t bus, device_t child, int type, int rid,
461     struct resource *res)
462 {
463 	void	*p;
464 	struct	uninorth_softc *sc;
465 
466 	sc = device_get_softc(bus);
467 
468 	if (type == SYS_RES_IRQ)
469 		return (bus_activate_resource(bus, type, rid, res));
470 
471 	if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
472 		vm_offset_t start;
473 
474 		start = (vm_offset_t)rman_get_start(res);
475 		/*
476 		 * For i/o-ports, convert the start address to the
477 		 * uninorth PCI i/o window
478 		 */
479 		if (type == SYS_RES_IOPORT)
480 			start += sc->sc_iostart;
481 
482 		if (bootverbose)
483 			printf("uninorth mapdev: start %x, len %ld\n", start,
484 			    rman_get_size(res));
485 
486 		p = pmap_mapdev(start, (vm_size_t)rman_get_size(res));
487 		if (p == NULL)
488 			return (ENOMEM);
489 		rman_set_virtual(res, p);
490 		rman_set_bustag(res, &bs_le_tag);
491 		rman_set_bushandle(res, (u_long)p);
492 	}
493 
494 	return (rman_activate_resource(res));
495 }
496 
497 static int
498 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
499     u_int func, u_int reg)
500 {
501 	uint32_t	cfgval;
502 	uint32_t	pass;
503 
504 	if (resource_int_value(device_get_name(sc->sc_dev),
505 	        device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
506 		if (pass == slot)
507 			return (0);
508 	}
509 
510 	if (sc->sc_bus == bus) {
511 		/*
512 		 * No slots less than 11 on the primary bus
513 		 */
514 		if (slot < 11)
515 			return (0);
516 
517 		cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
518 	} else {
519 		cfgval = (bus << 16) | (slot << 11) | (func << 8) |
520 		    (reg & 0xfc) | 1;
521 	}
522 
523 	do {
524 		out32rb(sc->sc_addr, cfgval);
525 	} while (in32rb(sc->sc_addr) != cfgval);
526 
527 	return (1);
528 }
529 
530 static phandle_t
531 uninorth_get_node(device_t bus, device_t dev)
532 {
533 	struct uninorth_softc *sc;
534 
535 	sc = device_get_softc(bus);
536 	/* We only have one child, the PCI bus, which needs our own node. */
537 
538 	return sc->sc_node;
539 }
540 
541 /*
542  * Driver to swallow UniNorth host bridges from the PCI bus side.
543  */
544 static int
545 unhb_probe(device_t dev)
546 {
547 
548 	if (pci_get_class(dev) == PCIC_BRIDGE &&
549 	    pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
550 		device_set_desc(dev, "Host to PCI bridge");
551 		device_quiet(dev);
552 		return (-10000);
553 	}
554 
555 	return (ENXIO);
556 }
557 
558 static int
559 unhb_attach(device_t dev)
560 {
561 
562 	return (0);
563 }
564 
565 static device_method_t unhb_methods[] = {
566 	/* Device interface */
567 	DEVMETHOD(device_probe,         unhb_probe),
568 	DEVMETHOD(device_attach,        unhb_attach),
569 
570 	{ 0, 0 }
571 };
572 
573 static driver_t unhb_driver = {
574 	"unhb",
575 	unhb_methods,
576 	1,
577 };
578 static devclass_t unhb_devclass;
579 
580 DRIVER_MODULE(unhb, pci, unhb_driver, unhb_devclass, 0, 0);
581 
582 
583 /*
584  * Small stub driver for the Uninorth chip itself, to allow setting
585  * of various parameters and cell enables
586  */
587 static struct unin_chip_softc *uncsc;
588 
589 static void
590 unin_enable_gmac(void)
591 {
592 	volatile u_int *clkreg;
593 	u_int32_t tmpl;
594 
595 	if (uncsc == NULL)
596 		panic("unin_enable_gmac: device not found");
597 
598 	clkreg = (void *)(uncsc->sc_addr + UNIN_CLOCKCNTL);
599 	tmpl = inl(clkreg);
600 	tmpl |= UNIN_CLOCKCNTL_GMAC;
601 	outl(clkreg, tmpl);
602 }
603 
604 static int
605 unin_chip_probe(device_t dev)
606 {
607 	const char	*name;
608 
609 	name = ofw_bus_get_name(dev);
610 
611 	if (name == NULL)
612 		return (ENXIO);
613 
614 	if (strcmp(name, "uni-n") != 0 && strcmp(name, "u3") != 0)
615 		return (ENXIO);
616 
617 	device_set_desc(dev, "Apple UniNorth System Controller");
618 	return (0);
619 }
620 
621 static int
622 unin_chip_attach(device_t dev)
623 {
624 	phandle_t node;
625 	u_int reg[3];
626 	int i = 0;
627 
628 	uncsc = device_get_softc(dev);
629 	node = ofw_bus_get_node(dev);
630 
631 	if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
632 		return (ENXIO);
633 
634 	if (strcmp(ofw_bus_get_name(dev), "u3") == 0)
635 		i = 1; /* #address-cells lies */
636 
637 	uncsc->sc_physaddr = reg[i];
638 	uncsc->sc_size = reg[i+1];
639 
640 	/*
641 	 * Only map the first page, since that is where the registers
642 	 * of interest lie.
643 	 */
644 	uncsc->sc_addr = (vm_offset_t) pmap_mapdev(uncsc->sc_physaddr,
645 	    PAGE_SIZE);
646 
647 	uncsc->sc_version = *(u_int *)uncsc->sc_addr;
648 	device_printf(dev, "Version %d\n", uncsc->sc_version);
649 
650 	return (0);
651 }
652 
653 static device_method_t unin_chip_methods[] = {
654 	/* Device interface */
655 	DEVMETHOD(device_probe,         unin_chip_probe),
656 	DEVMETHOD(device_attach,        unin_chip_attach),
657 
658 	{ 0, 0 }
659 };
660 
661 static driver_t	unin_chip_driver = {
662 	"unin",
663 	unin_chip_methods,
664 	sizeof(struct unin_chip_softc)
665 };
666 
667 static devclass_t	unin_chip_devclass;
668 
669 DRIVER_MODULE(unin, nexus, unin_chip_driver, unin_chip_devclass, 0, 0);
670 
671 
672 
673 
674