1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2002 by Peter Grehan. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for KeyLargo/Pangea, the MacPPC south bridge ASIC. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/rman.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr_machdep.h> 47 #include <machine/resource.h> 48 #include <machine/vmparam.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/ofw/openfirm.h> 53 54 #include <powerpc/powermac/maciovar.h> 55 #include <powerpc/powermac/platform_powermac.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 60 /* 61 * Macio softc 62 */ 63 struct macio_softc { 64 phandle_t sc_node; 65 vm_offset_t sc_base; 66 vm_offset_t sc_size; 67 struct rman sc_mem_rman; 68 69 /* FCR registers */ 70 int sc_memrid; 71 struct resource *sc_memr; 72 73 /* GPIO offsets */ 74 int sc_timebase; 75 }; 76 77 static MALLOC_DEFINE(M_MACIO, "macio", "macio device information"); 78 79 static int macio_probe(device_t); 80 static int macio_attach(device_t); 81 static int macio_print_child(device_t dev, device_t child); 82 static void macio_probe_nomatch(device_t, device_t); 83 static struct resource *macio_alloc_resource(device_t, device_t, int, int *, 84 rman_res_t, rman_res_t, rman_res_t, 85 u_int); 86 static int macio_activate_resource(device_t, device_t, int, int, 87 struct resource *); 88 static int macio_deactivate_resource(device_t, device_t, int, int, 89 struct resource *); 90 static int macio_release_resource(device_t, device_t, int, int, 91 struct resource *); 92 static struct resource_list *macio_get_resource_list (device_t, device_t); 93 static ofw_bus_get_devinfo_t macio_get_devinfo; 94 #if !defined(__powerpc64__) && defined(SMP) 95 static void macio_freeze_timebase(device_t, bool); 96 #endif 97 98 /* 99 * Bus interface definition 100 */ 101 static device_method_t macio_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, macio_probe), 104 DEVMETHOD(device_attach, macio_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, bus_generic_suspend), 108 DEVMETHOD(device_resume, bus_generic_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, macio_print_child), 112 DEVMETHOD(bus_probe_nomatch, macio_probe_nomatch), 113 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 114 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 115 116 DEVMETHOD(bus_alloc_resource, macio_alloc_resource), 117 DEVMETHOD(bus_release_resource, macio_release_resource), 118 DEVMETHOD(bus_activate_resource, macio_activate_resource), 119 DEVMETHOD(bus_deactivate_resource, macio_deactivate_resource), 120 DEVMETHOD(bus_get_resource_list, macio_get_resource_list), 121 122 DEVMETHOD(bus_child_pnpinfo, ofw_bus_gen_child_pnpinfo), 123 124 /* ofw_bus interface */ 125 DEVMETHOD(ofw_bus_get_devinfo, macio_get_devinfo), 126 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 127 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 128 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 129 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 130 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 131 { 0, 0 } 132 }; 133 134 static driver_t macio_pci_driver = { 135 "macio", 136 macio_methods, 137 sizeof(struct macio_softc) 138 }; 139 140 EARLY_DRIVER_MODULE(macio, pci, macio_pci_driver, 0, 0, BUS_PASS_BUS); 141 142 /* 143 * PCI ID search table 144 */ 145 static struct macio_pci_dev { 146 u_int32_t mpd_devid; 147 char *mpd_desc; 148 } macio_pci_devlist[] = { 149 { 0x0017106b, "Paddington I/O Controller" }, 150 { 0x0022106b, "KeyLargo I/O Controller" }, 151 { 0x0025106b, "Pangea I/O Controller" }, 152 { 0x003e106b, "Intrepid I/O Controller" }, 153 { 0x0041106b, "K2 KeyLargo I/O Controller" }, 154 { 0x004f106b, "Shasta I/O Controller" }, 155 { 0, NULL } 156 }; 157 158 /* 159 * Devices to exclude from the probe 160 * XXX some of these may be required in the future... 161 */ 162 #define MACIO_QUIRK_IGNORE 0x00000001 163 #define MACIO_QUIRK_CHILD_HAS_INTR 0x00000002 164 #define MACIO_QUIRK_USE_CHILD_REG 0x00000004 165 166 struct macio_quirk_entry { 167 const char *mq_name; 168 int mq_quirks; 169 }; 170 171 static struct macio_quirk_entry macio_quirks[] = { 172 { "escc-legacy", MACIO_QUIRK_IGNORE }, 173 { "timer", MACIO_QUIRK_IGNORE }, 174 { "escc", MACIO_QUIRK_CHILD_HAS_INTR }, 175 { "i2s", MACIO_QUIRK_CHILD_HAS_INTR | 176 MACIO_QUIRK_USE_CHILD_REG }, 177 { NULL, 0 } 178 }; 179 180 static int 181 macio_get_quirks(const char *name) 182 { 183 struct macio_quirk_entry *mqe; 184 185 for (mqe = macio_quirks; mqe->mq_name != NULL; mqe++) 186 if (strcmp(name, mqe->mq_name) == 0) 187 return (mqe->mq_quirks); 188 return (0); 189 } 190 191 /* 192 * Add an interrupt to the dev's resource list if present 193 */ 194 static void 195 macio_add_intr(phandle_t devnode, struct macio_devinfo *dinfo) 196 { 197 phandle_t iparent; 198 int *intr; 199 int i, nintr; 200 int icells; 201 202 if (dinfo->mdi_ninterrupts >= 6) { 203 printf("macio: device has more than 6 interrupts\n"); 204 return; 205 } 206 207 nintr = OF_getprop_alloc_multi(devnode, "interrupts", sizeof(*intr), 208 (void **)&intr); 209 if (nintr == -1) { 210 nintr = OF_getprop_alloc_multi(devnode, "AAPL,interrupts", 211 sizeof(*intr), (void **)&intr); 212 if (nintr == -1) 213 return; 214 } 215 216 if (intr[0] == -1) 217 return; 218 219 if (OF_getprop(devnode, "interrupt-parent", &iparent, sizeof(iparent)) 220 <= 0) 221 panic("Interrupt but no interrupt parent!\n"); 222 223 if (OF_getprop(OF_node_from_xref(iparent), "#interrupt-cells", &icells, 224 sizeof(icells)) <= 0) 225 icells = 1; 226 227 for (i = 0; i < nintr; i+=icells) { 228 u_int irq = MAP_IRQ(iparent, intr[i]); 229 230 resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, 231 dinfo->mdi_ninterrupts, irq, irq, 1); 232 233 dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = irq; 234 dinfo->mdi_ninterrupts++; 235 } 236 } 237 238 static void 239 macio_add_reg(phandle_t devnode, struct macio_devinfo *dinfo) 240 { 241 struct macio_reg *reg, *regp; 242 phandle_t child; 243 char buf[8]; 244 int i, layout_id = 0, nreg, res; 245 246 nreg = OF_getprop_alloc_multi(devnode, "reg", sizeof(*reg), (void **)®); 247 if (nreg == -1) 248 return; 249 250 /* 251 * Some G5's have broken properties in the i2s-a area. If so we try 252 * to fix it. Right now we know of two different cases, one for 253 * sound layout-id 36 and the other one for sound layout-id 76. 254 * What is missing is the base address for the memory addresses. 255 * We take them from the parent node (i2s) and use the size 256 * information from the child. 257 */ 258 259 if (reg[0].mr_base == 0) { 260 child = OF_child(devnode); 261 while (child != 0) { 262 res = OF_getprop(child, "name", buf, sizeof(buf)); 263 if (res > 0 && strcmp(buf, "sound") == 0) 264 break; 265 child = OF_peer(child); 266 } 267 268 res = OF_getprop(child, "layout-id", &layout_id, 269 sizeof(layout_id)); 270 271 if (res > 0 && (layout_id == 36 || layout_id == 76)) { 272 res = OF_getprop_alloc_multi(OF_parent(devnode), "reg", 273 sizeof(*regp), (void **)®p); 274 reg[0] = regp[0]; 275 reg[1].mr_base = regp[1].mr_base; 276 reg[2].mr_base = regp[1].mr_base + reg[1].mr_size; 277 } 278 } 279 280 for (i = 0; i < nreg; i++) { 281 resource_list_add(&dinfo->mdi_resources, SYS_RES_MEMORY, i, 282 reg[i].mr_base, reg[i].mr_base + reg[i].mr_size, 283 reg[i].mr_size); 284 } 285 } 286 287 /* 288 * PCI probe 289 */ 290 static int 291 macio_probe(device_t dev) 292 { 293 int i; 294 u_int32_t devid; 295 296 devid = pci_get_devid(dev); 297 for (i = 0; macio_pci_devlist[i].mpd_desc != NULL; i++) { 298 if (devid == macio_pci_devlist[i].mpd_devid) { 299 device_set_desc(dev, macio_pci_devlist[i].mpd_desc); 300 return (0); 301 } 302 } 303 304 return (ENXIO); 305 } 306 307 /* 308 * PCI attach: scan Open Firmware child nodes, and attach these as children 309 * of the macio bus 310 */ 311 static int 312 macio_attach(device_t dev) 313 { 314 struct macio_softc *sc; 315 struct macio_devinfo *dinfo; 316 phandle_t root; 317 phandle_t child; 318 phandle_t subchild; 319 device_t cdev; 320 u_int reg[3]; 321 char compat[32]; 322 int error, quirks; 323 324 sc = device_get_softc(dev); 325 root = sc->sc_node = ofw_bus_get_node(dev); 326 327 /* 328 * Locate the device node and it's base address 329 */ 330 if (OF_getprop(root, "assigned-addresses", 331 reg, sizeof(reg)) < (ssize_t)sizeof(reg)) { 332 return (ENXIO); 333 } 334 335 /* Used later to see if we have to enable the I2S part. */ 336 OF_getprop(root, "compatible", compat, sizeof(compat)); 337 338 sc->sc_base = reg[2]; 339 sc->sc_size = MACIO_REG_SIZE; 340 341 sc->sc_memrid = PCIR_BAR(0); 342 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 343 &sc->sc_memrid, RF_ACTIVE); 344 345 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 346 sc->sc_mem_rman.rm_descr = "MacIO Device Memory"; 347 error = rman_init(&sc->sc_mem_rman); 348 if (error) { 349 device_printf(dev, "rman_init() failed. error = %d\n", error); 350 return (error); 351 } 352 error = rman_manage_region(&sc->sc_mem_rman, 0, sc->sc_size); 353 if (error) { 354 device_printf(dev, 355 "rman_manage_region() failed. error = %d\n", error); 356 return (error); 357 } 358 359 /* 360 * Iterate through the sub-devices 361 */ 362 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 363 dinfo = malloc(sizeof(*dinfo), M_MACIO, M_WAITOK | M_ZERO); 364 if (ofw_bus_gen_setup_devinfo(&dinfo->mdi_obdinfo, child) != 365 0) { 366 free(dinfo, M_MACIO); 367 continue; 368 } 369 quirks = macio_get_quirks(dinfo->mdi_obdinfo.obd_name); 370 if ((quirks & MACIO_QUIRK_IGNORE) != 0) { 371 ofw_bus_gen_destroy_devinfo(&dinfo->mdi_obdinfo); 372 free(dinfo, M_MACIO); 373 continue; 374 } 375 resource_list_init(&dinfo->mdi_resources); 376 dinfo->mdi_ninterrupts = 0; 377 macio_add_intr(child, dinfo); 378 if ((quirks & MACIO_QUIRK_USE_CHILD_REG) != 0) 379 macio_add_reg(OF_child(child), dinfo); 380 else 381 macio_add_reg(child, dinfo); 382 if ((quirks & MACIO_QUIRK_CHILD_HAS_INTR) != 0) 383 for (subchild = OF_child(child); subchild != 0; 384 subchild = OF_peer(subchild)) 385 macio_add_intr(subchild, dinfo); 386 cdev = device_add_child(dev, NULL, -1); 387 if (cdev == NULL) { 388 device_printf(dev, "<%s>: device_add_child failed\n", 389 dinfo->mdi_obdinfo.obd_name); 390 resource_list_free(&dinfo->mdi_resources); 391 ofw_bus_gen_destroy_devinfo(&dinfo->mdi_obdinfo); 392 free(dinfo, M_MACIO); 393 continue; 394 } 395 device_set_ivars(cdev, dinfo); 396 397 /* Set FCRs to enable some devices */ 398 if (sc->sc_memr == NULL) 399 continue; 400 401 if (strcmp(ofw_bus_get_name(cdev), "bmac") == 0 || 402 (ofw_bus_get_compat(cdev) != NULL && 403 strcmp(ofw_bus_get_compat(cdev), "bmac+") == 0)) { 404 uint32_t fcr; 405 406 fcr = bus_read_4(sc->sc_memr, HEATHROW_FCR); 407 408 fcr |= FCR_ENET_ENABLE & ~FCR_ENET_RESET; 409 bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); 410 DELAY(50000); 411 fcr |= FCR_ENET_RESET; 412 bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); 413 DELAY(50000); 414 fcr &= ~FCR_ENET_RESET; 415 bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); 416 DELAY(50000); 417 418 bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); 419 } 420 421 /* 422 * Make sure the I2S0 and the I2S0_CLK are enabled. 423 * On certain G5's they are not. 424 */ 425 if ((strcmp(ofw_bus_get_name(cdev), "i2s") == 0) && 426 (strcmp(compat, "K2-Keylargo") == 0)) { 427 uint32_t fcr1; 428 429 fcr1 = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); 430 fcr1 |= FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE; 431 bus_write_4(sc->sc_memr, KEYLARGO_FCR1, fcr1); 432 } 433 } 434 435 #if !defined(__powerpc64__) && defined(SMP) 436 /* 437 * Detect an SMP G4 machine. 438 * 439 * On SMP G4, timebase freeze is via a GPIO on macio. 440 * 441 * When we are on an SMP G4, we need to install a handler to 442 * perform timebase freeze/unfreeze on behalf of the platform. 443 */ 444 if ((child = OF_finddevice("/cpus/PowerPC,G4@0")) != -1 && 445 OF_peer(child) != -1) { 446 if (OF_getprop(child, "timebase-enable", &sc->sc_timebase, 447 sizeof(sc->sc_timebase)) <= 0) 448 sc->sc_timebase = KEYLARGO_GPIO_BASE + 0x09; 449 powermac_register_timebase(dev, macio_freeze_timebase); 450 device_printf(dev, "GPIO timebase control at 0x%x\n", 451 sc->sc_timebase); 452 } 453 #endif 454 455 return (bus_generic_attach(dev)); 456 } 457 458 static int 459 macio_print_child(device_t dev, device_t child) 460 { 461 struct macio_devinfo *dinfo; 462 struct resource_list *rl; 463 int retval = 0; 464 465 dinfo = device_get_ivars(child); 466 rl = &dinfo->mdi_resources; 467 468 retval += bus_print_child_header(dev, child); 469 470 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 471 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 472 473 retval += bus_print_child_footer(dev, child); 474 475 return (retval); 476 } 477 478 static void 479 macio_probe_nomatch(device_t dev, device_t child) 480 { 481 struct macio_devinfo *dinfo; 482 struct resource_list *rl; 483 const char *type; 484 485 if (bootverbose) { 486 dinfo = device_get_ivars(child); 487 rl = &dinfo->mdi_resources; 488 489 if ((type = ofw_bus_get_type(child)) == NULL) 490 type = "(unknown)"; 491 device_printf(dev, "<%s, %s>", type, ofw_bus_get_name(child)); 492 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 493 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 494 printf(" (no driver attached)\n"); 495 } 496 } 497 498 static struct resource * 499 macio_alloc_resource(device_t bus, device_t child, int type, int *rid, 500 rman_res_t start, rman_res_t end, rman_res_t count, 501 u_int flags) 502 { 503 struct macio_softc *sc; 504 int needactivate; 505 struct resource *rv; 506 struct rman *rm; 507 u_long adjstart, adjend, adjcount; 508 struct macio_devinfo *dinfo; 509 struct resource_list_entry *rle; 510 511 sc = device_get_softc(bus); 512 dinfo = device_get_ivars(child); 513 514 needactivate = flags & RF_ACTIVE; 515 flags &= ~RF_ACTIVE; 516 517 switch (type) { 518 case SYS_RES_MEMORY: 519 case SYS_RES_IOPORT: 520 rle = resource_list_find(&dinfo->mdi_resources, SYS_RES_MEMORY, 521 *rid); 522 if (rle == NULL) { 523 device_printf(bus, "no rle for %s memory %d\n", 524 device_get_nameunit(child), *rid); 525 return (NULL); 526 } 527 528 if (start < rle->start) 529 adjstart = rle->start; 530 else if (start > rle->end) 531 adjstart = rle->end; 532 else 533 adjstart = start; 534 535 if (end < rle->start) 536 adjend = rle->start; 537 else if (end > rle->end) 538 adjend = rle->end; 539 else 540 adjend = end; 541 542 adjcount = adjend - adjstart; 543 544 rm = &sc->sc_mem_rman; 545 break; 546 547 case SYS_RES_IRQ: 548 /* Check for passthrough from subattachments like macgpio */ 549 if (device_get_parent(child) != bus) 550 return BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 551 type, rid, start, end, count, flags); 552 553 rle = resource_list_find(&dinfo->mdi_resources, SYS_RES_IRQ, 554 *rid); 555 if (rle == NULL) { 556 if (dinfo->mdi_ninterrupts >= 6) { 557 device_printf(bus, 558 "%s has more than 6 interrupts\n", 559 device_get_nameunit(child)); 560 return (NULL); 561 } 562 resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, 563 dinfo->mdi_ninterrupts, start, start, 1); 564 565 dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = start; 566 dinfo->mdi_ninterrupts++; 567 } 568 569 return (resource_list_alloc(&dinfo->mdi_resources, bus, child, 570 type, rid, start, end, count, flags)); 571 572 default: 573 device_printf(bus, "unknown resource request from %s\n", 574 device_get_nameunit(child)); 575 return (NULL); 576 } 577 578 rv = rman_reserve_resource(rm, adjstart, adjend, adjcount, flags, 579 child); 580 if (rv == NULL) { 581 device_printf(bus, 582 "failed to reserve resource %#lx - %#lx (%#lx) for %s\n", 583 adjstart, adjend, adjcount, device_get_nameunit(child)); 584 return (NULL); 585 } 586 587 rman_set_rid(rv, *rid); 588 589 if (needactivate) { 590 if (bus_activate_resource(child, type, *rid, rv) != 0) { 591 device_printf(bus, 592 "failed to activate resource for %s\n", 593 device_get_nameunit(child)); 594 rman_release_resource(rv); 595 return (NULL); 596 } 597 } 598 599 return (rv); 600 } 601 602 static int 603 macio_release_resource(device_t bus, device_t child, int type, int rid, 604 struct resource *res) 605 { 606 if (rman_get_flags(res) & RF_ACTIVE) { 607 int error = bus_deactivate_resource(child, type, rid, res); 608 if (error) 609 return error; 610 } 611 612 return (rman_release_resource(res)); 613 } 614 615 static int 616 macio_activate_resource(device_t bus, device_t child, int type, int rid, 617 struct resource *res) 618 { 619 struct macio_softc *sc; 620 void *p; 621 622 sc = device_get_softc(bus); 623 624 if (type == SYS_RES_IRQ) 625 return (bus_activate_resource(bus, type, rid, res)); 626 627 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { 628 p = pmap_mapdev((vm_paddr_t)rman_get_start(res) + sc->sc_base, 629 (vm_size_t)rman_get_size(res)); 630 if (p == NULL) 631 return (ENOMEM); 632 rman_set_virtual(res, p); 633 rman_set_bustag(res, &bs_le_tag); 634 rman_set_bushandle(res, (u_long)p); 635 } 636 637 return (rman_activate_resource(res)); 638 } 639 640 static int 641 macio_deactivate_resource(device_t bus, device_t child, int type, int rid, 642 struct resource *res) 643 { 644 /* 645 * If this is a memory resource, unmap it. 646 */ 647 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { 648 u_int32_t psize; 649 650 psize = rman_get_size(res); 651 pmap_unmapdev(rman_get_virtual(res), psize); 652 } 653 654 return (rman_deactivate_resource(res)); 655 } 656 657 static struct resource_list * 658 macio_get_resource_list (device_t dev, device_t child) 659 { 660 struct macio_devinfo *dinfo; 661 662 dinfo = device_get_ivars(child); 663 return (&dinfo->mdi_resources); 664 } 665 666 static const struct ofw_bus_devinfo * 667 macio_get_devinfo(device_t dev, device_t child) 668 { 669 struct macio_devinfo *dinfo; 670 671 dinfo = device_get_ivars(child); 672 return (&dinfo->mdi_obdinfo); 673 } 674 675 int 676 macio_enable_wireless(device_t dev, bool enable) 677 { 678 struct macio_softc *sc = device_get_softc(dev); 679 uint32_t x; 680 681 if (enable) { 682 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); 683 x |= 0x4; 684 bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); 685 686 /* Enable card slot. */ 687 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 5); 688 DELAY(1000); 689 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 4); 690 DELAY(1000); 691 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); 692 x &= ~0x80000000; 693 694 bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); 695 /* out8(gpio + 0x10, 4); */ 696 697 bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0b, 0); 698 bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0a, 0x28); 699 bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0d, 0x28); 700 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0d, 0x28); 701 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0e, 0x28); 702 bus_write_4(sc->sc_memr, 0x1c000, 0); 703 704 /* Initialize the card. */ 705 bus_write_4(sc->sc_memr, 0x1a3e0, 0x41); 706 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); 707 x |= 0x80000000; 708 bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); 709 } else { 710 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); 711 x &= ~0x4; 712 bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); 713 /* out8(gpio + 0x10, 0); */ 714 } 715 716 return (0); 717 } 718 719 #if !defined(__powerpc64__) && defined(SMP) 720 static void 721 macio_freeze_timebase(device_t dev, bool freeze) 722 { 723 struct macio_softc *sc = device_get_softc(dev); 724 725 if (freeze) { 726 bus_write_1(sc->sc_memr, sc->sc_timebase, 4); 727 } else { 728 bus_write_1(sc->sc_memr, sc->sc_timebase, 0); 729 } 730 bus_read_1(sc->sc_memr, sc->sc_timebase); 731 } 732 #endif 733