1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2001 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * NetBSD: ki2c.c,v 1.11 2007/12/06 17:00:33 ad Exp 28 * Id: ki2c.c,v 1.7 2002/10/05 09:56:05 tsubai Exp 29 */ 30 31 /* 32 * Support routines for the Keywest I2C controller. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 46 #include <dev/iicbus/iicbus.h> 47 #include <dev/iicbus/iiconf.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include "iicbus_if.h" 50 51 /* Keywest I2C Register offsets */ 52 #define MODE 0 53 #define CONTROL 1 54 #define STATUS 2 55 #define ISR 3 56 #define IER 4 57 #define ADDR 5 58 #define SUBADDR 6 59 #define DATA 7 60 #define REV 8 61 62 /* MODE */ 63 #define I2C_SPEED 0x03 /* Speed mask */ 64 #define I2C_100kHz 0x00 65 #define I2C_50kHz 0x01 66 #define I2C_25kHz 0x02 67 #define I2C_MODE 0x0c /* Mode mask */ 68 #define I2C_DUMBMODE 0x00 /* Dumb mode */ 69 #define I2C_STDMODE 0x04 /* Standard mode */ 70 #define I2C_STDSUBMODE 0x08 /* Standard mode + sub address */ 71 #define I2C_COMBMODE 0x0c /* Combined mode */ 72 #define I2C_PORT 0xf0 /* Port mask */ 73 74 /* CONTROL */ 75 #define I2C_CT_AAK 0x01 /* Send AAK */ 76 #define I2C_CT_ADDR 0x02 /* Send address(es) */ 77 #define I2C_CT_STOP 0x04 /* Send STOP */ 78 #define I2C_CT_START 0x08 /* Send START */ 79 80 /* STATUS */ 81 #define I2C_ST_BUSY 0x01 /* Busy */ 82 #define I2C_ST_LASTAAK 0x02 /* Last AAK */ 83 #define I2C_ST_LASTRW 0x04 /* Last R/W */ 84 #define I2C_ST_SDA 0x08 /* SDA */ 85 #define I2C_ST_SCL 0x10 /* SCL */ 86 87 /* ISR/IER */ 88 #define I2C_INT_DATA 0x01 /* Data byte sent/received */ 89 #define I2C_INT_ADDR 0x02 /* Address sent */ 90 #define I2C_INT_STOP 0x04 /* STOP condition sent */ 91 #define I2C_INT_START 0x08 /* START condition sent */ 92 93 /* I2C flags */ 94 #define I2C_BUSY 0x01 95 #define I2C_READING 0x02 96 #define I2C_ERROR 0x04 97 #define I2C_SELECTED 0x08 98 99 struct kiic_softc { 100 device_t sc_dev; 101 phandle_t sc_node; 102 struct mtx sc_mutex; 103 struct resource *sc_reg; 104 int sc_irqrid; 105 struct resource *sc_irq; 106 void *sc_ih; 107 u_int sc_regstep; 108 u_int sc_flags; 109 u_char *sc_data; 110 int sc_resid; 111 uint16_t sc_i2c_base; 112 device_t sc_iicbus; 113 }; 114 115 static int kiic_probe(device_t dev); 116 static int kiic_attach(device_t dev); 117 static void kiic_writereg(struct kiic_softc *sc, u_int, u_int); 118 static u_int kiic_readreg(struct kiic_softc *, u_int); 119 static void kiic_setport(struct kiic_softc *, u_int); 120 static void kiic_setmode(struct kiic_softc *, u_int); 121 static void kiic_setspeed(struct kiic_softc *, u_int); 122 static void kiic_intr(void *xsc); 123 static int kiic_transfer(device_t dev, struct iic_msg *msgs, 124 uint32_t nmsgs); 125 static phandle_t kiic_get_node(device_t bus, device_t dev); 126 127 static device_method_t kiic_methods[] = { 128 /* device interface */ 129 DEVMETHOD(device_probe, kiic_probe), 130 DEVMETHOD(device_attach, kiic_attach), 131 132 /* iicbus interface */ 133 DEVMETHOD(iicbus_callback, iicbus_null_callback), 134 DEVMETHOD(iicbus_transfer, kiic_transfer), 135 136 /* ofw_bus interface */ 137 DEVMETHOD(ofw_bus_get_node, kiic_get_node), 138 { 0, 0 } 139 }; 140 141 static driver_t kiic_driver = { 142 "iichb", 143 kiic_methods, 144 sizeof(struct kiic_softc) 145 }; 146 147 DRIVER_MODULE(kiic, macio, kiic_driver, 0, 0); 148 DRIVER_MODULE(kiic, unin, kiic_driver, 0, 0); 149 150 static int 151 kiic_probe(device_t self) 152 { 153 const char *name; 154 155 name = ofw_bus_get_name(self); 156 if (name && strcmp(name, "i2c") == 0) { 157 device_set_desc(self, "Keywest I2C controller"); 158 return (0); 159 } 160 161 return (ENXIO); 162 } 163 164 static int 165 kiic_attach(device_t self) 166 { 167 struct kiic_softc *sc = device_get_softc(self); 168 int rid, rate; 169 phandle_t node; 170 char name[64]; 171 172 bzero(sc, sizeof(*sc)); 173 sc->sc_dev = self; 174 175 node = ofw_bus_get_node(self); 176 if (node == 0 || node == -1) { 177 return (EINVAL); 178 } 179 180 rid = 0; 181 sc->sc_reg = bus_alloc_resource_any(self, SYS_RES_MEMORY, 182 &rid, RF_ACTIVE); 183 if (sc->sc_reg == NULL) { 184 return (ENOMEM); 185 } 186 187 if (OF_getencprop(node, "AAPL,i2c-rate", &rate, 4) != 4) { 188 device_printf(self, "cannot get i2c-rate\n"); 189 return (ENXIO); 190 } 191 if (OF_getencprop(node, "AAPL,address-step", &sc->sc_regstep, 4) != 4) { 192 device_printf(self, "unable to find i2c address step\n"); 193 return (ENXIO); 194 } 195 196 /* 197 * Some Keywest I2C devices have their children attached directly 198 * underneath them. Some have a single 'iicbus' child with the 199 * devices underneath that. Sort this out, and make sure that the 200 * OFW I2C layer has the correct node. 201 * 202 * Note: the I2C children of the Uninorth bridges have two ports. 203 * In general, the port is designated in the 9th bit of the I2C 204 * address. However, for kiic devices with children attached below 205 * an i2c-bus node, the port is indicated in the 'reg' property 206 * of the i2c-bus node. 207 */ 208 209 sc->sc_node = node; 210 211 node = OF_child(node); 212 if (OF_getprop(node, "name", name, sizeof(name)) > 0) { 213 if (strcmp(name,"i2c-bus") == 0) { 214 phandle_t reg; 215 if (OF_getprop(node, "reg", ®, sizeof(reg)) > 0) 216 sc->sc_i2c_base = reg << 8; 217 218 sc->sc_node = node; 219 } 220 } 221 222 mtx_init(&sc->sc_mutex, "kiic", NULL, MTX_DEF); 223 224 sc->sc_irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &sc->sc_irqrid, 225 RF_ACTIVE); 226 bus_setup_intr(self, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE, NULL, 227 kiic_intr, sc, &sc->sc_ih); 228 229 kiic_writereg(sc, ISR, kiic_readreg(sc, ISR)); 230 kiic_writereg(sc, STATUS, 0); 231 kiic_writereg(sc, IER, 0); 232 233 kiic_setmode(sc, I2C_STDMODE); 234 kiic_setspeed(sc, I2C_100kHz); /* XXX rate */ 235 236 kiic_writereg(sc, IER, I2C_INT_DATA | I2C_INT_ADDR | I2C_INT_STOP); 237 238 if (bootverbose) 239 device_printf(self, "Revision: %02X\n", kiic_readreg(sc, REV)); 240 241 /* Add the IIC bus layer */ 242 sc->sc_iicbus = device_add_child(self, "iicbus", DEVICE_UNIT_ANY); 243 244 return (bus_generic_attach(self)); 245 } 246 247 static void 248 kiic_writereg(struct kiic_softc *sc, u_int reg, u_int val) 249 { 250 bus_write_4(sc->sc_reg, sc->sc_regstep * reg, val); 251 DELAY(100); /* register access delay */ 252 } 253 254 static u_int 255 kiic_readreg(struct kiic_softc *sc, u_int reg) 256 { 257 return bus_read_4(sc->sc_reg, sc->sc_regstep * reg) & 0xff; 258 } 259 260 static void 261 kiic_setmode(struct kiic_softc *sc, u_int mode) 262 { 263 u_int x; 264 265 KASSERT((mode & ~I2C_MODE) == 0, ("bad mode")); 266 x = kiic_readreg(sc, MODE); 267 x &= ~I2C_MODE; 268 x |= mode; 269 kiic_writereg(sc, MODE, x); 270 } 271 272 static void 273 kiic_setport(struct kiic_softc *sc, u_int port) 274 { 275 u_int x; 276 277 KASSERT(port == 1 || port == 0, ("bad port")); 278 x = kiic_readreg(sc, MODE); 279 x &= ~I2C_PORT; 280 x |= (port << 4); 281 kiic_writereg(sc, MODE, x); 282 } 283 284 static void 285 kiic_setspeed(struct kiic_softc *sc, u_int speed) 286 { 287 u_int x; 288 289 KASSERT((speed & ~I2C_SPEED) == 0, ("bad speed")); 290 x = kiic_readreg(sc, MODE); 291 x &= ~I2C_SPEED; 292 x |= speed; 293 kiic_writereg(sc, MODE, x); 294 } 295 296 static void 297 kiic_intr(void *xsc) 298 { 299 struct kiic_softc *sc = xsc; 300 u_int isr; 301 uint32_t x; 302 303 mtx_lock(&sc->sc_mutex); 304 isr = kiic_readreg(sc, ISR); 305 306 if (isr & I2C_INT_ADDR) { 307 sc->sc_flags |= I2C_SELECTED; 308 309 if (sc->sc_flags & I2C_READING) { 310 if (sc->sc_resid > 1) { 311 x = kiic_readreg(sc, CONTROL); 312 x |= I2C_CT_AAK; 313 kiic_writereg(sc, CONTROL, x); 314 } 315 } else { 316 kiic_writereg(sc, DATA, *sc->sc_data++); 317 sc->sc_resid--; 318 } 319 } 320 321 if (isr & I2C_INT_DATA) { 322 if (sc->sc_flags & I2C_READING) { 323 if (sc->sc_resid > 0) { 324 *sc->sc_data++ = kiic_readreg(sc, DATA); 325 sc->sc_resid--; 326 } 327 if (sc->sc_resid == 0) /* done */ 328 kiic_writereg(sc, CONTROL, 0); 329 } else { 330 if (sc->sc_resid == 0) { 331 x = kiic_readreg(sc, CONTROL); 332 x |= I2C_CT_STOP; 333 kiic_writereg(sc, CONTROL, x); 334 } else { 335 kiic_writereg(sc, DATA, *sc->sc_data++); 336 sc->sc_resid--; 337 } 338 } 339 } 340 341 if (isr & I2C_INT_STOP) { 342 kiic_writereg(sc, CONTROL, 0); 343 sc->sc_flags &= ~I2C_SELECTED; 344 wakeup(sc->sc_dev); 345 } 346 347 kiic_writereg(sc, ISR, isr); 348 mtx_unlock(&sc->sc_mutex); 349 } 350 351 static int 352 kiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 353 { 354 struct kiic_softc *sc; 355 int i, x, timo, err; 356 uint16_t addr; 357 uint8_t subaddr; 358 359 sc = device_get_softc(dev); 360 timo = 100; 361 subaddr = 0; 362 363 mtx_lock(&sc->sc_mutex); 364 365 if (sc->sc_flags & I2C_BUSY) 366 mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo); 367 368 if (sc->sc_flags & I2C_BUSY) { 369 mtx_unlock(&sc->sc_mutex); 370 return (ETIMEDOUT); 371 } 372 373 sc->sc_flags = I2C_BUSY; 374 375 /* Clear pending interrupts, and reset controller */ 376 kiic_writereg(sc, ISR, kiic_readreg(sc, ISR)); 377 kiic_writereg(sc, STATUS, 0); 378 379 for (i = 0; i < nmsgs; i++) { 380 if (msgs[i].flags & IIC_M_NOSTOP) { 381 if (msgs[i+1].flags & IIC_M_RD) 382 kiic_setmode(sc, I2C_COMBMODE); 383 else 384 kiic_setmode(sc, I2C_STDSUBMODE); 385 KASSERT(msgs[i].len == 1, ("oversize I2C message")); 386 subaddr = msgs[i].buf[0]; 387 i++; 388 } else { 389 kiic_setmode(sc, I2C_STDMODE); 390 } 391 392 sc->sc_data = msgs[i].buf; 393 sc->sc_resid = msgs[i].len; 394 sc->sc_flags = I2C_BUSY; 395 addr = msgs[i].slave; 396 timo = 1000 + sc->sc_resid * 200; 397 timo += 100000; 398 399 if (msgs[i].flags & IIC_M_RD) { 400 sc->sc_flags |= I2C_READING; 401 addr |= 1; 402 } 403 404 addr |= sc->sc_i2c_base; 405 406 kiic_setport(sc, (addr & 0x100) >> 8); 407 kiic_writereg(sc, ADDR, addr & 0xff); 408 kiic_writereg(sc, SUBADDR, subaddr); 409 410 x = kiic_readreg(sc, CONTROL) | I2C_CT_ADDR; 411 kiic_writereg(sc, CONTROL, x); 412 413 err = mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo); 414 415 msgs[i].len -= sc->sc_resid; 416 417 if ((sc->sc_flags & I2C_ERROR) || err == EWOULDBLOCK) { 418 device_printf(sc->sc_dev, "I2C error\n"); 419 sc->sc_flags = 0; 420 mtx_unlock(&sc->sc_mutex); 421 return (EIO); 422 } 423 } 424 425 sc->sc_flags = 0; 426 427 mtx_unlock(&sc->sc_mutex); 428 429 return (0); 430 } 431 432 static phandle_t 433 kiic_get_node(device_t bus, device_t dev) 434 { 435 struct kiic_softc *sc; 436 437 sc = device_get_softc(bus); 438 /* We only have one child, the I2C bus, which needs our own node. */ 439 440 return sc->sc_node; 441 } 442