1 /*- 2 * Copyright (c) 2001 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * NetBSD: ki2c.c,v 1.11 2007/12/06 17:00:33 ad Exp 28 * Id: ki2c.c,v 1.7 2002/10/05 09:56:05 tsubai Exp 29 */ 30 31 /* 32 * Support routines for the Keywest I2C controller. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 46 #include <dev/iicbus/iicbus.h> 47 #include <dev/iicbus/iiconf.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include "iicbus_if.h" 50 51 /* Keywest I2C Register offsets */ 52 #define MODE 0 53 #define CONTROL 1 54 #define STATUS 2 55 #define ISR 3 56 #define IER 4 57 #define ADDR 5 58 #define SUBADDR 6 59 #define DATA 7 60 61 /* MODE */ 62 #define I2C_SPEED 0x03 /* Speed mask */ 63 #define I2C_100kHz 0x00 64 #define I2C_50kHz 0x01 65 #define I2C_25kHz 0x02 66 #define I2C_MODE 0x0c /* Mode mask */ 67 #define I2C_DUMBMODE 0x00 /* Dumb mode */ 68 #define I2C_STDMODE 0x04 /* Standard mode */ 69 #define I2C_STDSUBMODE 0x08 /* Standard mode + sub address */ 70 #define I2C_COMBMODE 0x0c /* Combined mode */ 71 #define I2C_PORT 0xf0 /* Port mask */ 72 73 /* CONTROL */ 74 #define I2C_CT_AAK 0x01 /* Send AAK */ 75 #define I2C_CT_ADDR 0x02 /* Send address(es) */ 76 #define I2C_CT_STOP 0x04 /* Send STOP */ 77 #define I2C_CT_START 0x08 /* Send START */ 78 79 /* STATUS */ 80 #define I2C_ST_BUSY 0x01 /* Busy */ 81 #define I2C_ST_LASTAAK 0x02 /* Last AAK */ 82 #define I2C_ST_LASTRW 0x04 /* Last R/W */ 83 #define I2C_ST_SDA 0x08 /* SDA */ 84 #define I2C_ST_SCL 0x10 /* SCL */ 85 86 /* ISR/IER */ 87 #define I2C_INT_DATA 0x01 /* Data byte sent/received */ 88 #define I2C_INT_ADDR 0x02 /* Address sent */ 89 #define I2C_INT_STOP 0x04 /* STOP condition sent */ 90 #define I2C_INT_START 0x08 /* START condition sent */ 91 92 /* I2C flags */ 93 #define I2C_BUSY 0x01 94 #define I2C_READING 0x02 95 #define I2C_ERROR 0x04 96 #define I2C_SELECTED 0x08 97 98 struct kiic_softc { 99 device_t sc_dev; 100 phandle_t sc_node; 101 struct mtx sc_mutex; 102 struct resource *sc_reg; 103 int sc_irqrid; 104 struct resource *sc_irq; 105 void *sc_ih; 106 u_int sc_regstep; 107 u_int sc_flags; 108 u_char *sc_data; 109 int sc_resid; 110 uint16_t sc_i2c_base; 111 device_t sc_iicbus; 112 }; 113 114 static int kiic_probe(device_t dev); 115 static int kiic_attach(device_t dev); 116 static void kiic_writereg(struct kiic_softc *sc, u_int, u_int); 117 static u_int kiic_readreg(struct kiic_softc *, u_int); 118 static void kiic_setport(struct kiic_softc *, u_int); 119 static void kiic_setmode(struct kiic_softc *, u_int); 120 static void kiic_setspeed(struct kiic_softc *, u_int); 121 static void kiic_intr(void *xsc); 122 static int kiic_transfer(device_t dev, struct iic_msg *msgs, 123 uint32_t nmsgs); 124 static phandle_t kiic_get_node(device_t bus, device_t dev); 125 126 static device_method_t kiic_methods[] = { 127 /* device interface */ 128 DEVMETHOD(device_probe, kiic_probe), 129 DEVMETHOD(device_attach, kiic_attach), 130 131 /* iicbus interface */ 132 DEVMETHOD(iicbus_callback, iicbus_null_callback), 133 DEVMETHOD(iicbus_transfer, kiic_transfer), 134 135 /* ofw_bus interface */ 136 DEVMETHOD(ofw_bus_get_node, kiic_get_node), 137 138 { 0, 0 } 139 }; 140 141 static driver_t kiic_driver = { 142 "iichb", 143 kiic_methods, 144 sizeof(struct kiic_softc) 145 }; 146 static devclass_t kiic_devclass; 147 148 DRIVER_MODULE(kiic, macio, kiic_driver, kiic_devclass, 0, 0); 149 150 static int 151 kiic_probe(device_t self) 152 { 153 const char *name; 154 155 name = ofw_bus_get_name(self); 156 if (name && strcmp(name, "i2c") == 0) { 157 device_set_desc(self, "Keywest I2C controller"); 158 return (0); 159 } 160 161 return (ENXIO); 162 } 163 164 static int 165 kiic_attach(device_t self) 166 { 167 struct kiic_softc *sc = device_get_softc(self); 168 int rid, rate; 169 phandle_t node; 170 char name[64]; 171 172 bzero(sc, sizeof(*sc)); 173 sc->sc_dev = self; 174 175 node = ofw_bus_get_node(self); 176 if (node == 0 || node == -1) { 177 return (EINVAL); 178 } 179 180 rid = 0; 181 sc->sc_reg = bus_alloc_resource_any(self, SYS_RES_MEMORY, 182 &rid, RF_ACTIVE); 183 if (sc->sc_reg == NULL) { 184 return (ENOMEM); 185 } 186 187 if (OF_getprop(node, "AAPL,i2c-rate", &rate, 4) != 4) { 188 device_printf(self, "cannot get i2c-rate\n"); 189 return (ENXIO); 190 } 191 if (OF_getprop(node, "AAPL,address-step", &sc->sc_regstep, 4) != 4) { 192 device_printf(self, "unable to find i2c address step\n"); 193 return (ENXIO); 194 } 195 196 /* 197 * Some Keywest I2C devices have their children attached directly 198 * underneath them. Some have a single 'iicbus' child with the 199 * devices underneath that. Sort this out, and make sure that the 200 * OFW I2C layer has the correct node. 201 * 202 * Note: the I2C children of the Uninorth bridges have two ports. 203 * In general, the port is designated in the 9th bit of the I2C 204 * address. However, for kiic devices with children attached below 205 * an i2c-bus node, the port is indicated in the 'reg' property 206 * of the i2c-bus node. 207 */ 208 209 sc->sc_node = node; 210 211 node = OF_child(node); 212 if (OF_getprop(node, "name", name, sizeof(name)) > 0) { 213 if (strcmp(name,"i2c-bus") == 0) { 214 phandle_t reg; 215 if (OF_getprop(node, "reg", ®, sizeof(reg)) > 0) 216 sc->sc_i2c_base = reg << 8; 217 218 sc->sc_node = node; 219 } 220 } 221 222 mtx_init(&sc->sc_mutex, "kiic", NULL, MTX_DEF); 223 224 sc->sc_irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &sc->sc_irqrid, 225 RF_ACTIVE); 226 bus_setup_intr(self, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE, NULL, 227 kiic_intr, sc, &sc->sc_ih); 228 229 kiic_writereg(sc, ISR, kiic_readreg(sc, ISR)); 230 kiic_writereg(sc, STATUS, 0); 231 kiic_writereg(sc, IER, 0); 232 233 kiic_setmode(sc, I2C_STDMODE); 234 kiic_setspeed(sc, I2C_100kHz); /* XXX rate */ 235 236 kiic_writereg(sc, IER, I2C_INT_DATA | I2C_INT_ADDR | I2C_INT_STOP); 237 238 /* Add the IIC bus layer */ 239 sc->sc_iicbus = device_add_child(self, "iicbus", -1); 240 241 return (bus_generic_attach(self)); 242 } 243 244 static void 245 kiic_writereg(struct kiic_softc *sc, u_int reg, u_int val) 246 { 247 bus_write_1(sc->sc_reg, sc->sc_regstep * reg, val); 248 DELAY(10); /* register access delay */ 249 } 250 251 static u_int 252 kiic_readreg(struct kiic_softc *sc, u_int reg) 253 { 254 return bus_read_1(sc->sc_reg, sc->sc_regstep * reg); 255 } 256 257 static void 258 kiic_setmode(struct kiic_softc *sc, u_int mode) 259 { 260 u_int x; 261 262 KASSERT((mode & ~I2C_MODE) == 0, ("bad mode")); 263 x = kiic_readreg(sc, MODE); 264 x &= ~I2C_MODE; 265 x |= mode; 266 kiic_writereg(sc, MODE, x); 267 } 268 269 static void 270 kiic_setport(struct kiic_softc *sc, u_int port) 271 { 272 u_int x; 273 274 KASSERT(port == 1 || port == 0, ("bad port")); 275 x = kiic_readreg(sc, MODE); 276 x &= ~I2C_PORT; 277 x |= (port << 4); 278 kiic_writereg(sc, MODE, x); 279 } 280 281 static void 282 kiic_setspeed(struct kiic_softc *sc, u_int speed) 283 { 284 u_int x; 285 286 KASSERT((speed & ~I2C_SPEED) == 0, ("bad speed")); 287 x = kiic_readreg(sc, MODE); 288 x &= ~I2C_SPEED; 289 x |= speed; 290 kiic_writereg(sc, MODE, x); 291 } 292 293 static void 294 kiic_intr(void *xsc) 295 { 296 struct kiic_softc *sc = xsc; 297 u_int isr; 298 uint32_t x; 299 300 mtx_lock(&sc->sc_mutex); 301 isr = kiic_readreg(sc, ISR); 302 303 if (isr & I2C_INT_ADDR) { 304 sc->sc_flags |= I2C_SELECTED; 305 306 if (sc->sc_flags & I2C_READING) { 307 if (sc->sc_resid > 1) { 308 x = kiic_readreg(sc, CONTROL); 309 x |= I2C_CT_AAK; 310 kiic_writereg(sc, CONTROL, x); 311 } 312 } else { 313 kiic_writereg(sc, DATA, *sc->sc_data++); 314 sc->sc_resid--; 315 } 316 } 317 318 if (isr & I2C_INT_DATA) { 319 if (sc->sc_flags & I2C_READING) { 320 if (sc->sc_resid > 0) { 321 *sc->sc_data++ = kiic_readreg(sc, DATA); 322 sc->sc_resid--; 323 } 324 if (sc->sc_resid == 0) /* done */ 325 kiic_writereg(sc, CONTROL, 0); 326 } else { 327 if (sc->sc_resid == 0) { 328 x = kiic_readreg(sc, CONTROL); 329 x |= I2C_CT_STOP; 330 kiic_writereg(sc, CONTROL, x); 331 } else { 332 kiic_writereg(sc, DATA, *sc->sc_data++); 333 sc->sc_resid--; 334 } 335 } 336 } 337 338 if (isr & I2C_INT_STOP) { 339 kiic_writereg(sc, CONTROL, 0); 340 sc->sc_flags &= ~I2C_SELECTED; 341 wakeup(sc->sc_dev); 342 } 343 344 kiic_writereg(sc, ISR, isr); 345 mtx_unlock(&sc->sc_mutex); 346 } 347 348 static int 349 kiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 350 { 351 struct kiic_softc *sc; 352 int i, x, timo, err; 353 uint16_t addr; 354 uint8_t subaddr; 355 356 sc = device_get_softc(dev); 357 timo = 100; 358 subaddr = 0; 359 360 mtx_lock(&sc->sc_mutex); 361 362 if (sc->sc_flags & I2C_BUSY) 363 mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo); 364 365 if (sc->sc_flags & I2C_BUSY) { 366 mtx_unlock(&sc->sc_mutex); 367 return (ETIMEDOUT); 368 } 369 370 sc->sc_flags = I2C_BUSY; 371 372 /* Clear pending interrupts, and reset controller */ 373 kiic_writereg(sc, ISR, kiic_readreg(sc, ISR)); 374 kiic_writereg(sc, STATUS, 0); 375 376 for (i = 0; i < nmsgs; i++) { 377 if (msgs[i].flags & IIC_M_NOSTOP) { 378 if (msgs[i+1].flags & IIC_M_RD) 379 kiic_setmode(sc, I2C_COMBMODE); 380 else 381 kiic_setmode(sc, I2C_STDSUBMODE); 382 KASSERT(msgs[i].len == 1, ("oversize I2C message")); 383 subaddr = msgs[i].buf[0]; 384 i++; 385 } else { 386 kiic_setmode(sc, I2C_STDMODE); 387 } 388 389 sc->sc_data = msgs[i].buf; 390 sc->sc_resid = msgs[i].len; 391 sc->sc_flags = I2C_BUSY; 392 addr = msgs[i].slave; 393 timo = 1000 + sc->sc_resid * 200; 394 timo += 100000; 395 396 if (msgs[i].flags & IIC_M_RD) { 397 sc->sc_flags |= I2C_READING; 398 addr |= 1; 399 } 400 401 addr |= sc->sc_i2c_base; 402 403 kiic_setport(sc, (addr & 0x100) >> 8); 404 kiic_writereg(sc, ADDR, addr & 0xff); 405 kiic_writereg(sc, SUBADDR, subaddr); 406 407 x = kiic_readreg(sc, CONTROL) | I2C_CT_ADDR; 408 kiic_writereg(sc, CONTROL, x); 409 410 err = mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo); 411 412 msgs[i].len -= sc->sc_resid; 413 414 if ((sc->sc_flags & I2C_ERROR) || err == EWOULDBLOCK) { 415 device_printf(sc->sc_dev, "I2C error\n"); 416 sc->sc_flags = 0; 417 mtx_unlock(&sc->sc_mutex); 418 return (-1); 419 } 420 } 421 422 sc->sc_flags = 0; 423 424 mtx_unlock(&sc->sc_mutex); 425 426 return (0); 427 } 428 429 static phandle_t 430 kiic_get_node(device_t bus, device_t dev) 431 { 432 struct kiic_softc *sc; 433 434 sc = device_get_softc(bus); 435 /* We only have one child, the I2C bus, which needs our own node. */ 436 437 return sc->sc_node; 438 } 439 440