1 /*- 2 * Copyright 2003 by Peter Grehan. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _POWERPC_POWERMAC_HROWPICVAR_H_ 31 #define _POWERPC_POWERMAC_HROWPICVAR_H_ 32 33 #define HROWPIC_IRQMAX 64 34 #define HROWPIC_IRQ_REGNUM 32 /* irqs per register */ 35 #define HROWPIC_IRQ_SHIFT 5 /* high or low irq word */ 36 #define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */ 37 38 /* 39 * Register offsets within bank. There are two identical banks, 40 * separated by 16 bytes. Interrupts 0->31 are processed in the 41 * second bank, and 32->63 in the first bank. 42 */ 43 #define HPIC_STATUS 0x00 /* active interrupt sources */ 44 #define HPIC_ENABLE 0x04 /* interrupt asserts ppc EXTINT */ 45 #define HPIC_CLEAR 0x08 /* clear int source */ 46 #define HPIC_TRIGGER 0x0c /* edge/level int trigger */ 47 48 #define HPIC_PRIMARY 1 /* primary register bank */ 49 #define HPIC_SECONDARY 0 /* secondary register bank */ 50 51 /* 52 * Convert an interrupt into a prim/sec bank number 53 */ 54 #define HPIC_INT_TO_BANK(x) \ 55 (((x) >> HROWPIC_IRQ_SHIFT) ^ 1) 56 57 /* 58 * Convert an interrupt into the bit number within a bank register 59 */ 60 #define HPIC_INT_TO_REGBIT(x) \ 61 ((x) & HROWPIC_IRQ_MASK) 62 63 #define HPIC_1ST_OFFSET 0x10 /* offset to primary reg bank */ 64 65 66 struct hrowpic_softc { 67 struct rman sc_rman; /* resource mgr for IRQs */ 68 u_int32_t sc_irq[HROWPIC_IRQMAX]; /* allocated IRQ flags */ 69 u_int32_t sc_softreg[2]; /* ENABLE reg copy */ 70 device_t sc_maciodev; /* macio device */ 71 struct resource *sc_memr; /* macio bus resource */ 72 bus_space_tag_t sc_bt; /* macio bus tag/handle */ 73 bus_space_handle_t sc_bh; 74 }; 75 76 77 #endif /* _POWERPC_POWERMAC_HROWPICVAR_H_ */ 78