1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2003 by Peter Grehan. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _POWERPC_POWERMAC_HROWPICVAR_H_ 31 #define _POWERPC_POWERMAC_HROWPICVAR_H_ 32 33 #define HROWPIC_IRQMAX 64 34 #define HROWPIC_IRQ_REGNUM 32 /* irqs per register */ 35 #define HROWPIC_IRQ_SHIFT 5 /* high or low irq word */ 36 #define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */ 37 38 /* 39 * Register offsets within bank. There are two identical banks, 40 * separated by 16 bytes. Interrupts 0->31 are processed in the 41 * second bank, and 32->63 in the first bank. 42 */ 43 #define HPIC_STATUS 0x00 /* active interrupt sources */ 44 #define HPIC_ENABLE 0x04 /* interrupt asserts ppc EXTINT */ 45 #define HPIC_CLEAR 0x08 /* clear int source */ 46 #define HPIC_TRIGGER 0x0c /* edge/level int trigger */ 47 48 #define HPIC_PRIMARY 1 /* primary register bank */ 49 #define HPIC_SECONDARY 0 /* secondary register bank */ 50 51 /* 52 * Convert an interrupt into a prim/sec bank number 53 */ 54 #define HPIC_INT_TO_BANK(x) \ 55 (((x) >> HROWPIC_IRQ_SHIFT) ^ 1) 56 57 /* 58 * Convert an interrupt into the bit number within a bank register 59 */ 60 #define HPIC_INT_TO_REGBIT(x) \ 61 ((x) & HROWPIC_IRQ_MASK) 62 63 #define HPIC_1ST_OFFSET 0x10 /* offset to primary reg bank */ 64 65 struct hrowpic_softc { 66 device_t sc_dev; /* macio device */ 67 struct resource *sc_rres; /* macio bus resource */ 68 bus_space_tag_t sc_bt; /* macio bus tag/handle */ 69 bus_space_handle_t sc_bh; 70 int sc_rrid; 71 uint32_t sc_softreg[2]; /* ENABLE reg copy */ 72 u_int sc_vector[HROWPIC_IRQMAX]; 73 }; 74 75 #endif /* _POWERPC_POWERMAC_HROWPICVAR_H_ */ 76