1 /*- 2 * Copyright 2003 by Peter Grehan. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * A driver for the PIC found in the Heathrow/Paddington MacIO chips. 32 * This was superseded by an OpenPIC in the Keylargo and beyond 33 * MacIO versions. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/rman.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/openfirm.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 #include <machine/intr_machdep.h> 50 #include <machine/md_var.h> 51 #include <machine/nexusvar.h> 52 #include <machine/pio.h> 53 #include <machine/resource.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <powerpc/powermac/hrowpicvar.h> 59 60 #include "pic_if.h" 61 62 /* 63 * MacIO interface 64 */ 65 static int hrowpic_probe(device_t); 66 static int hrowpic_attach(device_t); 67 68 static void hrowpic_dispatch(device_t, struct trapframe *); 69 static void hrowpic_enable(device_t, u_int, u_int); 70 static void hrowpic_eoi(device_t, u_int); 71 static void hrowpic_ipi(device_t, u_int); 72 static void hrowpic_mask(device_t, u_int); 73 static void hrowpic_unmask(device_t, u_int); 74 75 static device_method_t hrowpic_methods[] = { 76 /* Device interface */ 77 DEVMETHOD(device_probe, hrowpic_probe), 78 DEVMETHOD(device_attach, hrowpic_attach), 79 80 /* PIC interface */ 81 DEVMETHOD(pic_dispatch, hrowpic_dispatch), 82 DEVMETHOD(pic_enable, hrowpic_enable), 83 DEVMETHOD(pic_eoi, hrowpic_eoi), 84 DEVMETHOD(pic_ipi, hrowpic_ipi), 85 DEVMETHOD(pic_mask, hrowpic_mask), 86 DEVMETHOD(pic_unmask, hrowpic_unmask), 87 88 { 0, 0 }, 89 }; 90 91 static driver_t hrowpic_driver = { 92 "hrowpic", 93 hrowpic_methods, 94 sizeof(struct hrowpic_softc) 95 }; 96 97 static devclass_t hrowpic_devclass; 98 99 DRIVER_MODULE(hrowpic, macio, hrowpic_driver, hrowpic_devclass, 0, 0); 100 101 static uint32_t 102 hrowpic_read_reg(struct hrowpic_softc *sc, u_int reg, u_int bank) 103 { 104 if (bank == HPIC_PRIMARY) 105 reg += HPIC_1ST_OFFSET; 106 107 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); 108 } 109 110 static void 111 hrowpic_write_reg(struct hrowpic_softc *sc, u_int reg, u_int bank, 112 uint32_t val) 113 { 114 115 if (bank == HPIC_PRIMARY) 116 reg += HPIC_1ST_OFFSET; 117 118 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); 119 120 /* XXX Issue a read to force the write to complete. */ 121 bus_space_read_4(sc->sc_bt, sc->sc_bh, reg); 122 } 123 124 static int 125 hrowpic_probe(device_t dev) 126 { 127 const char *type = ofw_bus_get_type(dev); 128 129 /* 130 * OpenPIC cells have a type of "open-pic", so this 131 * is sufficient to identify a Heathrow cell 132 */ 133 if (strcmp(type, "interrupt-controller") != 0) 134 return (ENXIO); 135 136 /* 137 * The description was already printed out in the nexus 138 * probe, so don't do it again here 139 */ 140 device_set_desc(dev, "Heathrow MacIO interrupt controller"); 141 return (0); 142 } 143 144 static int 145 hrowpic_attach(device_t dev) 146 { 147 struct hrowpic_softc *sc; 148 149 sc = device_get_softc(dev); 150 sc->sc_dev = dev; 151 152 sc->sc_rrid = 0; 153 sc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rrid, 154 RF_ACTIVE); 155 156 if (sc->sc_rres == NULL) { 157 device_printf(dev, "Could not alloc mem resource!\n"); 158 return (ENXIO); 159 } 160 161 sc->sc_bt = rman_get_bustag(sc->sc_rres); 162 sc->sc_bh = rman_get_bushandle(sc->sc_rres); 163 164 /* 165 * Disable all interrupt sources and clear outstanding interrupts 166 */ 167 hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_PRIMARY, 0); 168 hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_PRIMARY, 0xffffffff); 169 hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_SECONDARY, 0); 170 hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff); 171 172 powerpc_register_pic(dev, 64); 173 return (0); 174 } 175 176 /* 177 * Local routines 178 */ 179 180 static void 181 hrowpic_toggle_irq(struct hrowpic_softc *sc, int irq, int enable) 182 { 183 u_int roffset; 184 u_int rbit; 185 186 KASSERT((irq > 0) && (irq < HROWPIC_IRQMAX), ("en irq out of range")); 187 188 /* 189 * Calculate prim/sec register bank for the IRQ, update soft copy, 190 * and enable the IRQ as an interrupt source 191 */ 192 roffset = HPIC_INT_TO_BANK(irq); 193 rbit = HPIC_INT_TO_REGBIT(irq); 194 195 if (enable) 196 sc->sc_softreg[roffset] |= (1 << rbit); 197 else 198 sc->sc_softreg[roffset] &= ~(1 << rbit); 199 200 hrowpic_write_reg(sc, HPIC_ENABLE, roffset, sc->sc_softreg[roffset]); 201 } 202 203 /* 204 * PIC I/F methods. 205 */ 206 207 static void 208 hrowpic_dispatch(device_t dev, struct trapframe *tf) 209 { 210 struct hrowpic_softc *sc; 211 uint64_t mask; 212 uint32_t reg; 213 u_int irq; 214 215 sc = device_get_softc(dev); 216 while (1) { 217 mask = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_SECONDARY); 218 reg = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_PRIMARY); 219 mask = (mask << 32) | reg; 220 if (mask == 0) 221 break; 222 223 irq = 0; 224 while (irq < HROWPIC_IRQMAX) { 225 if (mask & 1) 226 powerpc_dispatch_intr(sc->sc_vector[irq], tf); 227 mask >>= 1; 228 irq++; 229 } 230 } 231 } 232 233 static void 234 hrowpic_enable(device_t dev, u_int irq, u_int vector) 235 { 236 struct hrowpic_softc *sc; 237 238 sc = device_get_softc(dev); 239 sc->sc_vector[irq] = vector; 240 hrowpic_toggle_irq(sc, irq, 1); 241 } 242 243 static void 244 hrowpic_eoi(device_t dev __unused, u_int irq __unused) 245 { 246 struct hrowpic_softc *sc; 247 int bank; 248 249 sc = device_get_softc(dev); 250 bank = (irq >= 32) ? HPIC_SECONDARY : HPIC_PRIMARY ; 251 hrowpic_write_reg(sc, HPIC_CLEAR, bank, 1U << (irq & 0x1f)); 252 } 253 254 static void 255 hrowpic_ipi(device_t dev, u_int irq) 256 { 257 /* No SMP support. */ 258 } 259 260 static void 261 hrowpic_mask(device_t dev, u_int irq) 262 { 263 struct hrowpic_softc *sc; 264 int bank; 265 266 sc = device_get_softc(dev); 267 hrowpic_toggle_irq(sc, irq, 0); 268 bank = (irq >= 32) ? HPIC_SECONDARY : HPIC_PRIMARY ; 269 hrowpic_write_reg(sc, HPIC_CLEAR, bank, 1U << (irq & 0x1f)); 270 } 271 272 static void 273 hrowpic_unmask(device_t dev, u_int irq) 274 { 275 struct hrowpic_softc *sc; 276 277 sc = device_get_softc(dev); 278 hrowpic_toggle_irq(sc, irq, 1); 279 } 280