xref: /freebsd/sys/powerpc/powermac/dbdmavar.h (revision 9268022b74279434ed6300244e3f977e56a8ceb5)
1 /*-
2  * Copyright (c) 2008 Nathan Whitehorn
3  * All rights reserved
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  */
28 
29 #ifndef _POWERPC_POWERMAC_DBDMAVAR_H_
30 #define _POWERPC_POWERMAC_DBDMAVAR_H_
31 
32 struct dbdma_command {
33 	uint8_t cmd:4; /* DBDMA command */
34 
35 	uint8_t _resd1:1;
36 	uint8_t key:3; /* Stream number, or 6 for KEY_SYSTEM */
37 	uint8_t _resd2:2;
38 
39 	/* Interrupt, branch, and wait flags */
40 	uint8_t intr:2;
41 	uint8_t branch:2;
42 	uint8_t wait:2;
43 
44 	uint16_t reqCount; /* Bytes to transfer */
45 
46 	uint32_t address; /* 32-bit system physical address */
47 	uint32_t cmdDep; /* Branch address or quad word to load/store */
48 
49 	uint16_t xferStatus; /* Contents of channel status after completion */
50 	uint16_t resCount; /* Number of residual bytes outstanding */
51 };
52 
53 struct dbdma_channel {
54 	struct resource 	*sc_regs;
55 	u_int			sc_off;
56 
57 	struct dbdma_command	*sc_slots;
58 	int			sc_nslots;
59 	bus_addr_t		sc_slots_pa;
60 
61 	bus_dma_tag_t		sc_dmatag;
62 	bus_dmamap_t		sc_dmamap;
63 	uint32_t		sc_saved_regs[5];
64 };
65 
66 
67 /*
68    DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
69    and are laid out as follows within each block:
70 
71    Address:			Description:		Length (bytes):
72    0x000 			Channel Control 	4
73    0x004 			Channel Status		4
74    0x00C			Command Phys Addr	4
75    0x010			Interrupt Select	4
76    0x014			Branch Select		4
77    0x018			Wait Select		4
78 */
79 
80 #define CHAN_CONTROL_REG	0x00
81 #define	CHAN_STATUS_REG		0x04
82 #define CHAN_CMDPTR_HI		0x08
83 #define CHAN_CMDPTR		0x0C
84 #define	CHAN_INTR_SELECT	0x10
85 #define CHAN_BRANCH_SELECT	0x14
86 #define CHAN_WAIT_SELECT	0x18
87 
88 /* Channel control is the write channel to channel status, the upper 16 bits
89    are a mask of which bytes to change */
90 
91 #define	DBDMA_REG_MASK_SHIFT	16
92 
93 /* Status bits 0-7 are device dependent status bits */
94 
95 /*
96    The Interrupt/Branch/Wait Select triggers the corresponding condition bits
97    in the event that (select.mask & device dependent status) == select.value
98 
99    They are defined a follows:
100 	Byte 1: Reserved
101 	Byte 2: Mask
102 	Byte 3: Reserved
103 	Byte 4: Value
104 */
105 
106 #endif /* _POWERPC_POWERMAC_DBDMAVAR_H_ */
107