xref: /freebsd/sys/powerpc/powermac/cuda.c (revision 3df9e0375a80324fc2c38fd9a582c31ad286e035)
1b4dbc599SNathan Whitehorn /*-
2b4dbc599SNathan Whitehorn  * Copyright (c) 2006 Michael Lorenz
3b4dbc599SNathan Whitehorn  * Copyright 2008 by Nathan Whitehorn
4b4dbc599SNathan Whitehorn  * All rights reserved.
5b4dbc599SNathan Whitehorn  *
6b4dbc599SNathan Whitehorn  * Redistribution and use in source and binary forms, with or without
7b4dbc599SNathan Whitehorn  * modification, are permitted provided that the following conditions
8b4dbc599SNathan Whitehorn  * are met:
9b4dbc599SNathan Whitehorn  * 1. Redistributions of source code must retain the above copyright
10b4dbc599SNathan Whitehorn  *    notice, this list of conditions and the following disclaimer.
11b4dbc599SNathan Whitehorn  * 2. Redistributions in binary form must reproduce the above copyright
12b4dbc599SNathan Whitehorn  *    notice, this list of conditions and the following disclaimer in the
13b4dbc599SNathan Whitehorn  *    documentation and/or other materials provided with the distribution.
14b4dbc599SNathan Whitehorn  * 3. The name of the author may not be used to endorse or promote products
15b4dbc599SNathan Whitehorn  *    derived from this software without specific prior written permission.
16b4dbc599SNathan Whitehorn  *
17b4dbc599SNathan Whitehorn  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18b4dbc599SNathan Whitehorn  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19b4dbc599SNathan Whitehorn  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20b4dbc599SNathan Whitehorn  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21b4dbc599SNathan Whitehorn  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22b4dbc599SNathan Whitehorn  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23b4dbc599SNathan Whitehorn  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24b4dbc599SNathan Whitehorn  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25b4dbc599SNathan Whitehorn  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26b4dbc599SNathan Whitehorn  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27b4dbc599SNathan Whitehorn  * SUCH DAMAGE.
28b4dbc599SNathan Whitehorn  *
29b4dbc599SNathan Whitehorn  */
30b4dbc599SNathan Whitehorn 
31b4dbc599SNathan Whitehorn #include <sys/cdefs.h>
32b4dbc599SNathan Whitehorn __FBSDID("$FreeBSD$");
33b4dbc599SNathan Whitehorn 
34b4dbc599SNathan Whitehorn #include <sys/param.h>
35b4dbc599SNathan Whitehorn #include <sys/systm.h>
36b4dbc599SNathan Whitehorn #include <sys/module.h>
37b4dbc599SNathan Whitehorn #include <sys/bus.h>
38b4dbc599SNathan Whitehorn #include <sys/conf.h>
39b4dbc599SNathan Whitehorn #include <sys/kernel.h>
403df9e037SNathan Whitehorn #include <sys/clock.h>
41b4dbc599SNathan Whitehorn 
42b4dbc599SNathan Whitehorn #include <dev/ofw/ofw_bus.h>
43b4dbc599SNathan Whitehorn #include <dev/ofw/openfirm.h>
44b4dbc599SNathan Whitehorn 
45b4dbc599SNathan Whitehorn #include <machine/bus.h>
46b4dbc599SNathan Whitehorn #include <machine/intr.h>
47b4dbc599SNathan Whitehorn #include <machine/intr_machdep.h>
48b4dbc599SNathan Whitehorn #include <machine/md_var.h>
49b4dbc599SNathan Whitehorn #include <machine/pio.h>
50b4dbc599SNathan Whitehorn #include <machine/resource.h>
51b4dbc599SNathan Whitehorn 
52b4dbc599SNathan Whitehorn #include <vm/vm.h>
53b4dbc599SNathan Whitehorn #include <vm/pmap.h>
54b4dbc599SNathan Whitehorn 
55b4dbc599SNathan Whitehorn #include <sys/rman.h>
56b4dbc599SNathan Whitehorn 
57b4dbc599SNathan Whitehorn #include <dev/adb/adb.h>
58b4dbc599SNathan Whitehorn 
593df9e037SNathan Whitehorn #include "clock_if.h"
60b4dbc599SNathan Whitehorn #include "cudavar.h"
61b4dbc599SNathan Whitehorn #include "viareg.h"
62b4dbc599SNathan Whitehorn 
63b4dbc599SNathan Whitehorn /*
64b4dbc599SNathan Whitehorn  * MacIO interface
65b4dbc599SNathan Whitehorn  */
66b4dbc599SNathan Whitehorn static int	cuda_probe(device_t);
67b4dbc599SNathan Whitehorn static int	cuda_attach(device_t);
68b4dbc599SNathan Whitehorn static int	cuda_detach(device_t);
69b4dbc599SNathan Whitehorn 
70b4dbc599SNathan Whitehorn static u_int	cuda_adb_send(device_t dev, u_char command_byte, int len,
71b4dbc599SNathan Whitehorn     u_char *data, u_char poll);
72b4dbc599SNathan Whitehorn static u_int	cuda_adb_autopoll(device_t dev, uint16_t mask);
7365f44679SAndriy Gapon static u_int	cuda_poll(device_t dev);
74582434bdSNathan Whitehorn static void	cuda_send_inbound(struct cuda_softc *sc);
75582434bdSNathan Whitehorn static void	cuda_send_outbound(struct cuda_softc *sc);
76b4dbc599SNathan Whitehorn 
773df9e037SNathan Whitehorn /*
783df9e037SNathan Whitehorn  * Clock interface
793df9e037SNathan Whitehorn  */
803df9e037SNathan Whitehorn static int cuda_gettime(device_t dev, struct timespec *ts);
813df9e037SNathan Whitehorn static int cuda_settime(device_t dev, struct timespec *ts);
823df9e037SNathan Whitehorn 
83b4dbc599SNathan Whitehorn static device_method_t  cuda_methods[] = {
84b4dbc599SNathan Whitehorn 	/* Device interface */
85b4dbc599SNathan Whitehorn 	DEVMETHOD(device_probe,		cuda_probe),
86b4dbc599SNathan Whitehorn 	DEVMETHOD(device_attach,	cuda_attach),
87b4dbc599SNathan Whitehorn         DEVMETHOD(device_detach,        cuda_detach),
88b4dbc599SNathan Whitehorn         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
89b4dbc599SNathan Whitehorn         DEVMETHOD(device_suspend,       bus_generic_suspend),
90b4dbc599SNathan Whitehorn         DEVMETHOD(device_resume,        bus_generic_resume),
91b4dbc599SNathan Whitehorn 
92b4dbc599SNathan Whitehorn 	/* bus interface, for ADB root */
93b4dbc599SNathan Whitehorn         DEVMETHOD(bus_print_child,      bus_generic_print_child),
94b4dbc599SNathan Whitehorn         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
95b4dbc599SNathan Whitehorn 
96b4dbc599SNathan Whitehorn 	/* ADB bus interface */
97b4dbc599SNathan Whitehorn 	DEVMETHOD(adb_hb_send_raw_packet,	cuda_adb_send),
98b4dbc599SNathan Whitehorn 	DEVMETHOD(adb_hb_controller_poll,	cuda_poll),
99b4dbc599SNathan Whitehorn 	DEVMETHOD(adb_hb_set_autopoll_mask,	cuda_adb_autopoll),
100b4dbc599SNathan Whitehorn 
1013df9e037SNathan Whitehorn 	/* Clock interface */
1023df9e037SNathan Whitehorn 	DEVMETHOD(clock_gettime,	cuda_gettime),
1033df9e037SNathan Whitehorn 	DEVMETHOD(clock_settime,	cuda_settime),
1043df9e037SNathan Whitehorn 
105b4dbc599SNathan Whitehorn 	{ 0, 0 },
106b4dbc599SNathan Whitehorn };
107b4dbc599SNathan Whitehorn 
108b4dbc599SNathan Whitehorn static driver_t cuda_driver = {
109b4dbc599SNathan Whitehorn 	"cuda",
110b4dbc599SNathan Whitehorn 	cuda_methods,
111b4dbc599SNathan Whitehorn 	sizeof(struct cuda_softc),
112b4dbc599SNathan Whitehorn };
113b4dbc599SNathan Whitehorn 
114b4dbc599SNathan Whitehorn static devclass_t cuda_devclass;
115b4dbc599SNathan Whitehorn 
116b4dbc599SNathan Whitehorn DRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0);
117b4dbc599SNathan Whitehorn DRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0);
118b4dbc599SNathan Whitehorn 
119b4dbc599SNathan Whitehorn static void cuda_intr(void *arg);
120b4dbc599SNathan Whitehorn static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
121b4dbc599SNathan Whitehorn static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
122b4dbc599SNathan Whitehorn static void cuda_idle(struct cuda_softc *);
123b4dbc599SNathan Whitehorn static void cuda_tip(struct cuda_softc *);
124b4dbc599SNathan Whitehorn static void cuda_clear_tip(struct cuda_softc *);
125b4dbc599SNathan Whitehorn static void cuda_in(struct cuda_softc *);
126b4dbc599SNathan Whitehorn static void cuda_out(struct cuda_softc *);
127b4dbc599SNathan Whitehorn static void cuda_toggle_ack(struct cuda_softc *);
128b4dbc599SNathan Whitehorn static void cuda_ack_off(struct cuda_softc *);
129b4dbc599SNathan Whitehorn static int cuda_intr_state(struct cuda_softc *);
130b4dbc599SNathan Whitehorn 
131b4dbc599SNathan Whitehorn static int
132b4dbc599SNathan Whitehorn cuda_probe(device_t dev)
133b4dbc599SNathan Whitehorn {
134b4dbc599SNathan Whitehorn 	const char *type = ofw_bus_get_type(dev);
135b4dbc599SNathan Whitehorn 
136b4dbc599SNathan Whitehorn 	if (strcmp(type, "via-cuda") != 0)
137b4dbc599SNathan Whitehorn                 return (ENXIO);
138b4dbc599SNathan Whitehorn 
139b4dbc599SNathan Whitehorn 	device_set_desc(dev, CUDA_DEVSTR);
140b4dbc599SNathan Whitehorn 	return (0);
141b4dbc599SNathan Whitehorn }
142b4dbc599SNathan Whitehorn 
143b4dbc599SNathan Whitehorn static int
144b4dbc599SNathan Whitehorn cuda_attach(device_t dev)
145b4dbc599SNathan Whitehorn {
146b4dbc599SNathan Whitehorn 	struct cuda_softc *sc;
147b4dbc599SNathan Whitehorn 
148b4dbc599SNathan Whitehorn 	volatile int i;
149b4dbc599SNathan Whitehorn 	uint8_t reg;
150b4dbc599SNathan Whitehorn 	phandle_t node,child;
151b4dbc599SNathan Whitehorn 
152b4dbc599SNathan Whitehorn 	sc = device_get_softc(dev);
153b4dbc599SNathan Whitehorn 	sc->sc_dev = dev;
154b4dbc599SNathan Whitehorn 
155b4dbc599SNathan Whitehorn 	sc->sc_memrid = 0;
156b4dbc599SNathan Whitehorn 	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
157b4dbc599SNathan Whitehorn 	    &sc->sc_memrid, RF_ACTIVE);
158b4dbc599SNathan Whitehorn 
159b4dbc599SNathan Whitehorn 	if (sc->sc_memr == NULL) {
160b4dbc599SNathan Whitehorn 		device_printf(dev, "Could not alloc mem resource!\n");
161b4dbc599SNathan Whitehorn 		return (ENXIO);
162b4dbc599SNathan Whitehorn 	}
163b4dbc599SNathan Whitehorn 
164b4dbc599SNathan Whitehorn 	sc->sc_irqrid = 0;
165b4dbc599SNathan Whitehorn 	sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
166b4dbc599SNathan Whitehorn             	RF_ACTIVE);
167b4dbc599SNathan Whitehorn         if (sc->sc_irq == NULL) {
168b4dbc599SNathan Whitehorn                 device_printf(dev, "could not allocate interrupt\n");
169b4dbc599SNathan Whitehorn                 return (ENXIO);
170b4dbc599SNathan Whitehorn         }
171b4dbc599SNathan Whitehorn 
172b4dbc599SNathan Whitehorn 	if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
173b4dbc599SNathan Whitehorn 	    | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
174b4dbc599SNathan Whitehorn                 device_printf(dev, "could not setup interrupt\n");
175b4dbc599SNathan Whitehorn                 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
176b4dbc599SNathan Whitehorn                     sc->sc_irq);
177b4dbc599SNathan Whitehorn                 return (ENXIO);
178b4dbc599SNathan Whitehorn         }
179b4dbc599SNathan Whitehorn 
180b4dbc599SNathan Whitehorn 	mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
181b4dbc599SNathan Whitehorn 
182b4dbc599SNathan Whitehorn 	sc->sc_sent = 0;
183b4dbc599SNathan Whitehorn 	sc->sc_received = 0;
184b4dbc599SNathan Whitehorn 	sc->sc_waiting = 0;
185b4dbc599SNathan Whitehorn 	sc->sc_polling = 0;
186b4dbc599SNathan Whitehorn 	sc->sc_state = CUDA_NOTREADY;
187b4dbc599SNathan Whitehorn 	sc->sc_autopoll = 0;
1883df9e037SNathan Whitehorn 	sc->sc_rtc = -1;
189b4dbc599SNathan Whitehorn 
190582434bdSNathan Whitehorn 	STAILQ_INIT(&sc->sc_inq);
191582434bdSNathan Whitehorn 	STAILQ_INIT(&sc->sc_outq);
192011ad8e7SNathan Whitehorn 	STAILQ_INIT(&sc->sc_freeq);
193011ad8e7SNathan Whitehorn 
194011ad8e7SNathan Whitehorn 	for (i = 0; i < CUDA_MAXPACKETS; i++)
195011ad8e7SNathan Whitehorn 		STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
196582434bdSNathan Whitehorn 
197b4dbc599SNathan Whitehorn 	/* Init CUDA */
198b4dbc599SNathan Whitehorn 
199b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vDirB);
200b4dbc599SNathan Whitehorn 	reg |= 0x30;	/* register B bits 4 and 5: outputs */
201b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vDirB, reg);
202b4dbc599SNathan Whitehorn 
203b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vDirB);
204b4dbc599SNathan Whitehorn 	reg &= 0xf7;	/* register B bit 3: input */
205b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vDirB, reg);
206b4dbc599SNathan Whitehorn 
207b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vACR);
208b4dbc599SNathan Whitehorn 	reg &= ~vSR_OUT;	/* make sure SR is set to IN */
209b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vACR, reg);
210b4dbc599SNathan Whitehorn 
211b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
212b4dbc599SNathan Whitehorn 
213b4dbc599SNathan Whitehorn 	sc->sc_state = CUDA_IDLE;	/* used by all types of hardware */
214b4dbc599SNathan Whitehorn 
215b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
216b4dbc599SNathan Whitehorn 
217b4dbc599SNathan Whitehorn 	cuda_idle(sc);	/* reset ADB */
218b4dbc599SNathan Whitehorn 
219b4dbc599SNathan Whitehorn 	/* Reset CUDA */
220b4dbc599SNathan Whitehorn 
221b4dbc599SNathan Whitehorn 	i = cuda_read_reg(sc, vSR);	/* clear interrupt */
222b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
223b4dbc599SNathan Whitehorn 	cuda_idle(sc);	/* reset state to idle */
224b4dbc599SNathan Whitehorn 	DELAY(150);
225b4dbc599SNathan Whitehorn 	cuda_tip(sc);	/* signal start of frame */
226b4dbc599SNathan Whitehorn 	DELAY(150);
227b4dbc599SNathan Whitehorn 	cuda_toggle_ack(sc);
228b4dbc599SNathan Whitehorn 	DELAY(150);
229b4dbc599SNathan Whitehorn 	cuda_clear_tip(sc);
230b4dbc599SNathan Whitehorn 	DELAY(150);
231b4dbc599SNathan Whitehorn 	cuda_idle(sc);	/* back to idle state */
232b4dbc599SNathan Whitehorn 	i = cuda_read_reg(sc, vSR);	/* clear interrupt */
233b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vIER, 0x84);	/* ints ok now */
234b4dbc599SNathan Whitehorn 
235b4dbc599SNathan Whitehorn 	/* Initialize child buses (ADB) */
236b4dbc599SNathan Whitehorn 	node = ofw_bus_get_node(dev);
237b4dbc599SNathan Whitehorn 
238b4dbc599SNathan Whitehorn 	for (child = OF_child(node); child != 0; child = OF_peer(child)) {
239b4dbc599SNathan Whitehorn 		char name[32];
240b4dbc599SNathan Whitehorn 
241b4dbc599SNathan Whitehorn 		memset(name, 0, sizeof(name));
242b4dbc599SNathan Whitehorn 		OF_getprop(child, "name", name, sizeof(name));
243b4dbc599SNathan Whitehorn 
244b4dbc599SNathan Whitehorn 		if (bootverbose)
245b4dbc599SNathan Whitehorn 			device_printf(dev, "CUDA child <%s>\n",name);
246b4dbc599SNathan Whitehorn 
247b4dbc599SNathan Whitehorn 		if (strncmp(name, "adb", 4) == 0) {
248b4dbc599SNathan Whitehorn 			sc->adb_bus = device_add_child(dev,"adb",-1);
249b4dbc599SNathan Whitehorn 		}
250b4dbc599SNathan Whitehorn 	}
251b4dbc599SNathan Whitehorn 
2523df9e037SNathan Whitehorn 	clock_register(dev, 1000);
2533df9e037SNathan Whitehorn 
254b4dbc599SNathan Whitehorn 	return (bus_generic_attach(dev));
255b4dbc599SNathan Whitehorn }
256b4dbc599SNathan Whitehorn 
257b4dbc599SNathan Whitehorn static int cuda_detach(device_t dev) {
258b4dbc599SNathan Whitehorn 	struct cuda_softc *sc;
259b4dbc599SNathan Whitehorn 
260b4dbc599SNathan Whitehorn 	sc = device_get_softc(dev);
261b4dbc599SNathan Whitehorn 
262b4dbc599SNathan Whitehorn 	bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
263b4dbc599SNathan Whitehorn 	bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
264b4dbc599SNathan Whitehorn 	bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
265b4dbc599SNathan Whitehorn 	mtx_destroy(&sc->sc_mutex);
266b4dbc599SNathan Whitehorn 
267b4dbc599SNathan Whitehorn 	return (bus_generic_detach(dev));
268b4dbc599SNathan Whitehorn }
269b4dbc599SNathan Whitehorn 
270b4dbc599SNathan Whitehorn static uint8_t
271b4dbc599SNathan Whitehorn cuda_read_reg(struct cuda_softc *sc, u_int offset) {
272b4dbc599SNathan Whitehorn 	return (bus_read_1(sc->sc_memr, offset));
273b4dbc599SNathan Whitehorn }
274b4dbc599SNathan Whitehorn 
275b4dbc599SNathan Whitehorn static void
276b4dbc599SNathan Whitehorn cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
277b4dbc599SNathan Whitehorn 	bus_write_1(sc->sc_memr, offset, value);
278b4dbc599SNathan Whitehorn }
279b4dbc599SNathan Whitehorn 
280b4dbc599SNathan Whitehorn static void
281b4dbc599SNathan Whitehorn cuda_idle(struct cuda_softc *sc)
282b4dbc599SNathan Whitehorn {
283b4dbc599SNathan Whitehorn 	uint8_t reg;
284b4dbc599SNathan Whitehorn 
285b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vBufB);
286b4dbc599SNathan Whitehorn 	reg |= (vPB4 | vPB5);
287b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vBufB, reg);
288b4dbc599SNathan Whitehorn }
289b4dbc599SNathan Whitehorn 
290b4dbc599SNathan Whitehorn static void
291b4dbc599SNathan Whitehorn cuda_tip(struct cuda_softc *sc)
292b4dbc599SNathan Whitehorn {
293b4dbc599SNathan Whitehorn 	uint8_t reg;
294b4dbc599SNathan Whitehorn 
295b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vBufB);
296b4dbc599SNathan Whitehorn 	reg &= ~vPB5;
297b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vBufB, reg);
298b4dbc599SNathan Whitehorn }
299b4dbc599SNathan Whitehorn 
300b4dbc599SNathan Whitehorn static void
301b4dbc599SNathan Whitehorn cuda_clear_tip(struct cuda_softc *sc)
302b4dbc599SNathan Whitehorn {
303b4dbc599SNathan Whitehorn 	uint8_t reg;
304b4dbc599SNathan Whitehorn 
305b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vBufB);
306b4dbc599SNathan Whitehorn 	reg |= vPB5;
307b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vBufB, reg);
308b4dbc599SNathan Whitehorn }
309b4dbc599SNathan Whitehorn 
310b4dbc599SNathan Whitehorn static void
311b4dbc599SNathan Whitehorn cuda_in(struct cuda_softc *sc)
312b4dbc599SNathan Whitehorn {
313b4dbc599SNathan Whitehorn 	uint8_t reg;
314b4dbc599SNathan Whitehorn 
315b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vACR);
316b4dbc599SNathan Whitehorn 	reg &= ~vSR_OUT;
317b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vACR, reg);
318b4dbc599SNathan Whitehorn }
319b4dbc599SNathan Whitehorn 
320b4dbc599SNathan Whitehorn static void
321b4dbc599SNathan Whitehorn cuda_out(struct cuda_softc *sc)
322b4dbc599SNathan Whitehorn {
323b4dbc599SNathan Whitehorn 	uint8_t reg;
324b4dbc599SNathan Whitehorn 
325b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vACR);
326b4dbc599SNathan Whitehorn 	reg |= vSR_OUT;
327b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vACR, reg);
328b4dbc599SNathan Whitehorn }
329b4dbc599SNathan Whitehorn 
330b4dbc599SNathan Whitehorn static void
331b4dbc599SNathan Whitehorn cuda_toggle_ack(struct cuda_softc *sc)
332b4dbc599SNathan Whitehorn {
333b4dbc599SNathan Whitehorn 	uint8_t reg;
334b4dbc599SNathan Whitehorn 
335b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vBufB);
336b4dbc599SNathan Whitehorn 	reg ^= vPB4;
337b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vBufB, reg);
338b4dbc599SNathan Whitehorn }
339b4dbc599SNathan Whitehorn 
340b4dbc599SNathan Whitehorn static void
341b4dbc599SNathan Whitehorn cuda_ack_off(struct cuda_softc *sc)
342b4dbc599SNathan Whitehorn {
343b4dbc599SNathan Whitehorn 	uint8_t reg;
344b4dbc599SNathan Whitehorn 
345b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vBufB);
346b4dbc599SNathan Whitehorn 	reg |= vPB4;
347b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vBufB, reg);
348b4dbc599SNathan Whitehorn }
349b4dbc599SNathan Whitehorn 
350b4dbc599SNathan Whitehorn static int
351b4dbc599SNathan Whitehorn cuda_intr_state(struct cuda_softc *sc)
352b4dbc599SNathan Whitehorn {
353b4dbc599SNathan Whitehorn 	return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
354b4dbc599SNathan Whitehorn }
355b4dbc599SNathan Whitehorn 
356b4dbc599SNathan Whitehorn static int
357b4dbc599SNathan Whitehorn cuda_send(void *cookie, int poll, int length, uint8_t *msg)
358b4dbc599SNathan Whitehorn {
359b4dbc599SNathan Whitehorn 	struct cuda_softc *sc = cookie;
360b4dbc599SNathan Whitehorn 	device_t dev = sc->sc_dev;
361582434bdSNathan Whitehorn 	struct cuda_packet *pkt;
362b4dbc599SNathan Whitehorn 
363b4dbc599SNathan Whitehorn 	if (sc->sc_state == CUDA_NOTREADY)
364582434bdSNathan Whitehorn 		return (-1);
365b4dbc599SNathan Whitehorn 
366b4dbc599SNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
367b4dbc599SNathan Whitehorn 
368011ad8e7SNathan Whitehorn 	pkt = STAILQ_FIRST(&sc->sc_freeq);
369011ad8e7SNathan Whitehorn 	if (pkt == NULL) {
370011ad8e7SNathan Whitehorn 		mtx_unlock(&sc->sc_mutex);
371011ad8e7SNathan Whitehorn 		return (-1);
372011ad8e7SNathan Whitehorn 	}
373011ad8e7SNathan Whitehorn 
374582434bdSNathan Whitehorn 	pkt->len = length - 1;
375582434bdSNathan Whitehorn 	pkt->type = msg[0];
376582434bdSNathan Whitehorn 	memcpy(pkt->data, &msg[1], pkt->len);
377582434bdSNathan Whitehorn 
378011ad8e7SNathan Whitehorn 	STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
379582434bdSNathan Whitehorn 	STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
380582434bdSNathan Whitehorn 
381582434bdSNathan Whitehorn 	/*
382582434bdSNathan Whitehorn 	 * If we already are sending a packet, we should bail now that this
383582434bdSNathan Whitehorn 	 * one has been added to the queue.
384582434bdSNathan Whitehorn 	 */
385582434bdSNathan Whitehorn 
386582434bdSNathan Whitehorn 	if (sc->sc_waiting) {
387b4dbc599SNathan Whitehorn 		mtx_unlock(&sc->sc_mutex);
388582434bdSNathan Whitehorn 		return (0);
389b4dbc599SNathan Whitehorn 	}
390b4dbc599SNathan Whitehorn 
391582434bdSNathan Whitehorn 	cuda_send_outbound(sc);
392582434bdSNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
393582434bdSNathan Whitehorn 
394582434bdSNathan Whitehorn 	if (sc->sc_polling || poll || cold)
395582434bdSNathan Whitehorn 		cuda_poll(dev);
396582434bdSNathan Whitehorn 
397582434bdSNathan Whitehorn 	return (0);
398582434bdSNathan Whitehorn }
399582434bdSNathan Whitehorn 
400582434bdSNathan Whitehorn static void
401582434bdSNathan Whitehorn cuda_send_outbound(struct cuda_softc *sc)
402582434bdSNathan Whitehorn {
403582434bdSNathan Whitehorn 	struct cuda_packet *pkt;
404582434bdSNathan Whitehorn 
405582434bdSNathan Whitehorn 	mtx_assert(&sc->sc_mutex, MA_OWNED);
406582434bdSNathan Whitehorn 
407582434bdSNathan Whitehorn 	pkt = STAILQ_FIRST(&sc->sc_outq);
408582434bdSNathan Whitehorn 	if (pkt == NULL)
409582434bdSNathan Whitehorn 		return;
410582434bdSNathan Whitehorn 
411582434bdSNathan Whitehorn 	sc->sc_out_length = pkt->len + 1;
412582434bdSNathan Whitehorn 	memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
413b4dbc599SNathan Whitehorn 	sc->sc_sent = 0;
414b4dbc599SNathan Whitehorn 
415582434bdSNathan Whitehorn 	STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
416011ad8e7SNathan Whitehorn 	STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
417582434bdSNathan Whitehorn 
418582434bdSNathan Whitehorn 	sc->sc_waiting = 1;
419582434bdSNathan Whitehorn 
420582434bdSNathan Whitehorn 	cuda_poll(sc->sc_dev);
421582434bdSNathan Whitehorn 
422b4dbc599SNathan Whitehorn 	DELAY(150);
423582434bdSNathan Whitehorn 
424582434bdSNathan Whitehorn 	if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
425b4dbc599SNathan Whitehorn 		sc->sc_state = CUDA_OUT;
426b4dbc599SNathan Whitehorn 		cuda_out(sc);
427b4dbc599SNathan Whitehorn 		cuda_write_reg(sc, vSR, sc->sc_out[0]);
428b4dbc599SNathan Whitehorn 		cuda_ack_off(sc);
429b4dbc599SNathan Whitehorn 		cuda_tip(sc);
430b4dbc599SNathan Whitehorn 	}
431b4dbc599SNathan Whitehorn }
432b4dbc599SNathan Whitehorn 
433582434bdSNathan Whitehorn static void
434582434bdSNathan Whitehorn cuda_send_inbound(struct cuda_softc *sc)
435582434bdSNathan Whitehorn {
436582434bdSNathan Whitehorn 	device_t dev;
437582434bdSNathan Whitehorn 	struct cuda_packet *pkt;
438582434bdSNathan Whitehorn 
439582434bdSNathan Whitehorn 	dev = sc->sc_dev;
440582434bdSNathan Whitehorn 
441582434bdSNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
442582434bdSNathan Whitehorn 
443582434bdSNathan Whitehorn 	while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
444582434bdSNathan Whitehorn 		STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
445582434bdSNathan Whitehorn 
446582434bdSNathan Whitehorn 		mtx_unlock(&sc->sc_mutex);
447582434bdSNathan Whitehorn 
448582434bdSNathan Whitehorn 		/* check if we have a handler for this message */
449582434bdSNathan Whitehorn 		switch (pkt->type) {
450582434bdSNathan Whitehorn 		   case CUDA_ADB:
451582434bdSNathan Whitehorn 			if (pkt->len > 2) {
452582434bdSNathan Whitehorn 				adb_receive_raw_packet(sc->adb_bus,
453582434bdSNathan Whitehorn 				    pkt->data[0],pkt->data[1],
454582434bdSNathan Whitehorn 				    pkt->len - 2,&pkt->data[2]);
455582434bdSNathan Whitehorn 			} else {
456582434bdSNathan Whitehorn 				adb_receive_raw_packet(sc->adb_bus,
457582434bdSNathan Whitehorn 				    pkt->data[0],pkt->data[1],0,NULL);
458582434bdSNathan Whitehorn 			}
459582434bdSNathan Whitehorn 			break;
460582434bdSNathan Whitehorn 		   case CUDA_PSEUDO:
461582434bdSNathan Whitehorn 			mtx_lock(&sc->sc_mutex);
4623df9e037SNathan Whitehorn 			switch (pkt->data[1]) {
4633df9e037SNathan Whitehorn 			case CMD_AUTOPOLL:
464582434bdSNathan Whitehorn 				sc->sc_autopoll = 1;
4653df9e037SNathan Whitehorn 				break;
4663df9e037SNathan Whitehorn 			case CMD_READ_RTC:
4673df9e037SNathan Whitehorn 				memcpy(&sc->sc_rtc, &pkt->data[2],
4683df9e037SNathan Whitehorn 				    sizeof(sc->sc_rtc));
4693df9e037SNathan Whitehorn 				wakeup(&sc->sc_rtc);
4703df9e037SNathan Whitehorn 				break;
4713df9e037SNathan Whitehorn 			case CMD_WRITE_RTC:
4723df9e037SNathan Whitehorn 				break;
4733df9e037SNathan Whitehorn 			}
474582434bdSNathan Whitehorn 			mtx_unlock(&sc->sc_mutex);
475582434bdSNathan Whitehorn 			break;
476582434bdSNathan Whitehorn 		   case CUDA_ERROR:
477582434bdSNathan Whitehorn 			/*
478582434bdSNathan Whitehorn 			 * CUDA will throw errors if we miss a race between
479582434bdSNathan Whitehorn 			 * sending and receiving packets. This is already
480582434bdSNathan Whitehorn 			 * handled when we abort packet output to handle
481582434bdSNathan Whitehorn 			 * this packet in cuda_intr(). Thus, we ignore
482582434bdSNathan Whitehorn 			 * these messages.
483582434bdSNathan Whitehorn 			 */
484582434bdSNathan Whitehorn 			break;
485582434bdSNathan Whitehorn 		   default:
486582434bdSNathan Whitehorn 			device_printf(dev,"unknown CUDA command %d\n",
487582434bdSNathan Whitehorn 			    pkt->type);
488582434bdSNathan Whitehorn 			break;
489582434bdSNathan Whitehorn 		}
490582434bdSNathan Whitehorn 
491582434bdSNathan Whitehorn 		mtx_lock(&sc->sc_mutex);
492011ad8e7SNathan Whitehorn 
493011ad8e7SNathan Whitehorn 		STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
494582434bdSNathan Whitehorn 	}
495582434bdSNathan Whitehorn 
496582434bdSNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
497b4dbc599SNathan Whitehorn }
498b4dbc599SNathan Whitehorn 
49965f44679SAndriy Gapon static u_int
500b4dbc599SNathan Whitehorn cuda_poll(device_t dev)
501b4dbc599SNathan Whitehorn {
502b4dbc599SNathan Whitehorn 	struct cuda_softc *sc = device_get_softc(dev);
503b4dbc599SNathan Whitehorn 
50401418697SNathan Whitehorn 	if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
50501418697SNathan Whitehorn 	    !sc->sc_waiting)
50665f44679SAndriy Gapon 		return (0);
50701418697SNathan Whitehorn 
508b4dbc599SNathan Whitehorn 	cuda_intr(dev);
50965f44679SAndriy Gapon 	return (0);
510b4dbc599SNathan Whitehorn }
511b4dbc599SNathan Whitehorn 
512b4dbc599SNathan Whitehorn static void
513b4dbc599SNathan Whitehorn cuda_intr(void *arg)
514b4dbc599SNathan Whitehorn {
515b4dbc599SNathan Whitehorn 	device_t        dev;
516b4dbc599SNathan Whitehorn 	struct cuda_softc *sc;
517b4dbc599SNathan Whitehorn 
518582434bdSNathan Whitehorn 	int i, ending, restart_send, process_inbound;
519b4dbc599SNathan Whitehorn 	uint8_t reg;
520b4dbc599SNathan Whitehorn 
521b4dbc599SNathan Whitehorn         dev = (device_t)arg;
522b4dbc599SNathan Whitehorn 	sc = device_get_softc(dev);
523b4dbc599SNathan Whitehorn 
524b4dbc599SNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
525b4dbc599SNathan Whitehorn 
526b4dbc599SNathan Whitehorn 	restart_send = 0;
527582434bdSNathan Whitehorn 	process_inbound = 0;
528b4dbc599SNathan Whitehorn 	reg = cuda_read_reg(sc, vIFR);
529582434bdSNathan Whitehorn 	if ((reg & vSR_INT) != vSR_INT) {
530582434bdSNathan Whitehorn 		mtx_unlock(&sc->sc_mutex);
531582434bdSNathan Whitehorn 		return;
532582434bdSNathan Whitehorn 	}
533582434bdSNathan Whitehorn 
534b4dbc599SNathan Whitehorn 	cuda_write_reg(sc, vIFR, 0x7f);	/* Clear interrupt */
535b4dbc599SNathan Whitehorn 
536b4dbc599SNathan Whitehorn switch_start:
537b4dbc599SNathan Whitehorn 	switch (sc->sc_state) {
538b4dbc599SNathan Whitehorn 	case CUDA_IDLE:
539b4dbc599SNathan Whitehorn 		/*
540b4dbc599SNathan Whitehorn 		 * This is an unexpected packet, so grab the first (dummy)
541b4dbc599SNathan Whitehorn 		 * byte, set up the proper vars, and tell the chip we are
542b4dbc599SNathan Whitehorn 		 * starting to receive the packet by setting the TIP bit.
543b4dbc599SNathan Whitehorn 		 */
544b4dbc599SNathan Whitehorn 		sc->sc_in[1] = cuda_read_reg(sc, vSR);
545b4dbc599SNathan Whitehorn 
546b4dbc599SNathan Whitehorn 		if (cuda_intr_state(sc) == 0) {
547b4dbc599SNathan Whitehorn 			/* must have been a fake start */
548b4dbc599SNathan Whitehorn 
549b4dbc599SNathan Whitehorn 			if (sc->sc_waiting) {
550b4dbc599SNathan Whitehorn 				/* start over */
551b4dbc599SNathan Whitehorn 				DELAY(150);
552b4dbc599SNathan Whitehorn 				sc->sc_state = CUDA_OUT;
553b4dbc599SNathan Whitehorn 				sc->sc_sent = 0;
554b4dbc599SNathan Whitehorn 				cuda_out(sc);
555b4dbc599SNathan Whitehorn 				cuda_write_reg(sc, vSR, sc->sc_out[1]);
556b4dbc599SNathan Whitehorn 				cuda_ack_off(sc);
557b4dbc599SNathan Whitehorn 				cuda_tip(sc);
558b4dbc599SNathan Whitehorn 			}
559b4dbc599SNathan Whitehorn 			break;
560b4dbc599SNathan Whitehorn 		}
561b4dbc599SNathan Whitehorn 
562b4dbc599SNathan Whitehorn 		cuda_in(sc);
563b4dbc599SNathan Whitehorn 		cuda_tip(sc);
564b4dbc599SNathan Whitehorn 
565b4dbc599SNathan Whitehorn 		sc->sc_received = 1;
566b4dbc599SNathan Whitehorn 		sc->sc_state = CUDA_IN;
567b4dbc599SNathan Whitehorn 		break;
568b4dbc599SNathan Whitehorn 
569b4dbc599SNathan Whitehorn 	case CUDA_IN:
570b4dbc599SNathan Whitehorn 		sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
571b4dbc599SNathan Whitehorn 		ending = 0;
572b4dbc599SNathan Whitehorn 
573b4dbc599SNathan Whitehorn 		if (sc->sc_received > 255) {
574b4dbc599SNathan Whitehorn 			/* bitch only once */
575b4dbc599SNathan Whitehorn 			if (sc->sc_received == 256) {
576b4dbc599SNathan Whitehorn 				device_printf(dev,"input overflow\n");
577b4dbc599SNathan Whitehorn 				ending = 1;
578b4dbc599SNathan Whitehorn 			}
579b4dbc599SNathan Whitehorn 		} else
580b4dbc599SNathan Whitehorn 			sc->sc_received++;
581b4dbc599SNathan Whitehorn 
582b4dbc599SNathan Whitehorn 		/* intr off means this is the last byte (end of frame) */
583b4dbc599SNathan Whitehorn 		if (cuda_intr_state(sc) == 0) {
584b4dbc599SNathan Whitehorn 			ending = 1;
585b4dbc599SNathan Whitehorn 		} else {
586b4dbc599SNathan Whitehorn 			cuda_toggle_ack(sc);
587b4dbc599SNathan Whitehorn 		}
588b4dbc599SNathan Whitehorn 
589b4dbc599SNathan Whitehorn 		if (ending == 1) {	/* end of message? */
590582434bdSNathan Whitehorn 			struct cuda_packet *pkt;
591b4dbc599SNathan Whitehorn 
592b4dbc599SNathan Whitehorn 			/* reset vars and signal the end of this frame */
593b4dbc599SNathan Whitehorn 			cuda_idle(sc);
594b4dbc599SNathan Whitehorn 
595582434bdSNathan Whitehorn 			/* Queue up the packet */
596011ad8e7SNathan Whitehorn 			pkt = STAILQ_FIRST(&sc->sc_freeq);
597011ad8e7SNathan Whitehorn 			if (pkt != NULL) {
598011ad8e7SNathan Whitehorn 				/* If we have a free packet, process it */
599b4dbc599SNathan Whitehorn 
600582434bdSNathan Whitehorn 				pkt->len = sc->sc_received - 2;
601582434bdSNathan Whitehorn 				pkt->type = sc->sc_in[1];
602582434bdSNathan Whitehorn 				memcpy(pkt->data, &sc->sc_in[2], pkt->len);
603582434bdSNathan Whitehorn 
604011ad8e7SNathan Whitehorn 				STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
605582434bdSNathan Whitehorn 				STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
606b4dbc599SNathan Whitehorn 
607011ad8e7SNathan Whitehorn 				process_inbound = 1;
608011ad8e7SNathan Whitehorn 			}
609011ad8e7SNathan Whitehorn 
610b4dbc599SNathan Whitehorn 			sc->sc_state = CUDA_IDLE;
611b4dbc599SNathan Whitehorn 			sc->sc_received = 0;
612b4dbc599SNathan Whitehorn 
613b4dbc599SNathan Whitehorn 			/*
614b4dbc599SNathan Whitehorn 			 * If there is something waiting to be sent out,
615b4dbc599SNathan Whitehorn 			 * set everything up and send the first byte.
616b4dbc599SNathan Whitehorn 			 */
617b4dbc599SNathan Whitehorn 			if (sc->sc_waiting == 1) {
618b4dbc599SNathan Whitehorn 				DELAY(1500);	/* required */
619b4dbc599SNathan Whitehorn 				sc->sc_sent = 0;
620b4dbc599SNathan Whitehorn 				sc->sc_state = CUDA_OUT;
621b4dbc599SNathan Whitehorn 
622b4dbc599SNathan Whitehorn 				/*
623b4dbc599SNathan Whitehorn 				 * If the interrupt is on, we were too slow
624b4dbc599SNathan Whitehorn 				 * and the chip has already started to send
625b4dbc599SNathan Whitehorn 				 * something to us, so back out of the write
626b4dbc599SNathan Whitehorn 				 * and start a read cycle.
627b4dbc599SNathan Whitehorn 				 */
628b4dbc599SNathan Whitehorn 				if (cuda_intr_state(sc)) {
629b4dbc599SNathan Whitehorn 					cuda_in(sc);
630b4dbc599SNathan Whitehorn 					cuda_idle(sc);
631b4dbc599SNathan Whitehorn 					sc->sc_sent = 0;
632b4dbc599SNathan Whitehorn 					sc->sc_state = CUDA_IDLE;
633b4dbc599SNathan Whitehorn 					sc->sc_received = 0;
634b4dbc599SNathan Whitehorn 					DELAY(150);
635b4dbc599SNathan Whitehorn 					goto switch_start;
636b4dbc599SNathan Whitehorn 				}
637582434bdSNathan Whitehorn 
638b4dbc599SNathan Whitehorn 				/*
639b4dbc599SNathan Whitehorn 				 * If we got here, it's ok to start sending
640b4dbc599SNathan Whitehorn 				 * so load the first byte and tell the chip
641b4dbc599SNathan Whitehorn 				 * we want to send.
642b4dbc599SNathan Whitehorn 				 */
643b4dbc599SNathan Whitehorn 				cuda_out(sc);
644b4dbc599SNathan Whitehorn 				cuda_write_reg(sc, vSR,
645b4dbc599SNathan Whitehorn 				    sc->sc_out[sc->sc_sent]);
646b4dbc599SNathan Whitehorn 				cuda_ack_off(sc);
647b4dbc599SNathan Whitehorn 				cuda_tip(sc);
648b4dbc599SNathan Whitehorn 			}
649b4dbc599SNathan Whitehorn 		}
650b4dbc599SNathan Whitehorn 		break;
651b4dbc599SNathan Whitehorn 
652b4dbc599SNathan Whitehorn 	case CUDA_OUT:
653b4dbc599SNathan Whitehorn 		i = cuda_read_reg(sc, vSR);	/* reset SR-intr in IFR */
654b4dbc599SNathan Whitehorn 
655b4dbc599SNathan Whitehorn 		sc->sc_sent++;
656b4dbc599SNathan Whitehorn 		if (cuda_intr_state(sc)) {	/* ADB intr low during write */
657b4dbc599SNathan Whitehorn 			cuda_in(sc);	/* make sure SR is set to IN */
658b4dbc599SNathan Whitehorn 			cuda_idle(sc);
659b4dbc599SNathan Whitehorn 			sc->sc_sent = 0;	/* must start all over */
660b4dbc599SNathan Whitehorn 			sc->sc_state = CUDA_IDLE;	/* new state */
661b4dbc599SNathan Whitehorn 			sc->sc_received = 0;
662b4dbc599SNathan Whitehorn 			sc->sc_waiting = 1;	/* must retry when done with
663b4dbc599SNathan Whitehorn 						 * read */
664b4dbc599SNathan Whitehorn 			DELAY(150);
665b4dbc599SNathan Whitehorn 			goto switch_start;	/* process next state right
666b4dbc599SNathan Whitehorn 						 * now */
667b4dbc599SNathan Whitehorn 			break;
668b4dbc599SNathan Whitehorn 		}
669b4dbc599SNathan Whitehorn 		if (sc->sc_out_length == sc->sc_sent) {	/* check for done */
670b4dbc599SNathan Whitehorn 			sc->sc_waiting = 0;	/* done writing */
671b4dbc599SNathan Whitehorn 			sc->sc_state = CUDA_IDLE;	/* signal bus is idle */
672b4dbc599SNathan Whitehorn 			cuda_in(sc);
673b4dbc599SNathan Whitehorn 			cuda_idle(sc);
674b4dbc599SNathan Whitehorn 		} else {
675b4dbc599SNathan Whitehorn 			/* send next byte */
676b4dbc599SNathan Whitehorn 			cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
677b4dbc599SNathan Whitehorn 			cuda_toggle_ack(sc);	/* signal byte ready to
678b4dbc599SNathan Whitehorn 							 * shift */
679b4dbc599SNathan Whitehorn 		}
680b4dbc599SNathan Whitehorn 		break;
681b4dbc599SNathan Whitehorn 
682b4dbc599SNathan Whitehorn 	case CUDA_NOTREADY:
683b4dbc599SNathan Whitehorn 		break;
684b4dbc599SNathan Whitehorn 
685b4dbc599SNathan Whitehorn 	default:
686b4dbc599SNathan Whitehorn 		break;
687b4dbc599SNathan Whitehorn 	}
688b4dbc599SNathan Whitehorn 
689b4dbc599SNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
690582434bdSNathan Whitehorn 
691582434bdSNathan Whitehorn 	if (process_inbound)
692582434bdSNathan Whitehorn 		cuda_send_inbound(sc);
693582434bdSNathan Whitehorn 
694582434bdSNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
695582434bdSNathan Whitehorn 	/* If we have another packet waiting, set it up */
696582434bdSNathan Whitehorn 	if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
697582434bdSNathan Whitehorn 		cuda_send_outbound(sc);
698582434bdSNathan Whitehorn 
699582434bdSNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
700582434bdSNathan Whitehorn 
701b4dbc599SNathan Whitehorn }
702b4dbc599SNathan Whitehorn 
703b4dbc599SNathan Whitehorn static u_int
704582434bdSNathan Whitehorn cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
705582434bdSNathan Whitehorn     u_char poll)
706b4dbc599SNathan Whitehorn {
707b4dbc599SNathan Whitehorn 	struct cuda_softc *sc = device_get_softc(dev);
708b4dbc599SNathan Whitehorn 	uint8_t packet[16];
709582434bdSNathan Whitehorn 	int i;
710b4dbc599SNathan Whitehorn 
711b4dbc599SNathan Whitehorn 	/* construct an ADB command packet and send it */
712b4dbc599SNathan Whitehorn 	packet[0] = CUDA_ADB;
713b4dbc599SNathan Whitehorn 	packet[1] = command_byte;
714b4dbc599SNathan Whitehorn 	for (i = 0; i < len; i++)
715b4dbc599SNathan Whitehorn 		packet[i + 2] = data[i];
716b4dbc599SNathan Whitehorn 
717b4dbc599SNathan Whitehorn 	cuda_send(sc, poll, len + 2, packet);
718b4dbc599SNathan Whitehorn 
719582434bdSNathan Whitehorn 	return (0);
720b4dbc599SNathan Whitehorn }
721b4dbc599SNathan Whitehorn 
722b4dbc599SNathan Whitehorn static u_int
723b4dbc599SNathan Whitehorn cuda_adb_autopoll(device_t dev, uint16_t mask) {
724b4dbc599SNathan Whitehorn 	struct cuda_softc *sc = device_get_softc(dev);
725b4dbc599SNathan Whitehorn 
726b4dbc599SNathan Whitehorn 	uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
727b4dbc599SNathan Whitehorn 
728b4dbc599SNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
72901418697SNathan Whitehorn 
730b4dbc599SNathan Whitehorn 	if (cmd[2] == sc->sc_autopoll) {
731b4dbc599SNathan Whitehorn 		mtx_unlock(&sc->sc_mutex);
732582434bdSNathan Whitehorn 		return (0);
733b4dbc599SNathan Whitehorn 	}
734b4dbc599SNathan Whitehorn 
735b4dbc599SNathan Whitehorn 	sc->sc_autopoll = -1;
736582434bdSNathan Whitehorn 	cuda_send(sc, 1, 3, cmd);
737b4dbc599SNathan Whitehorn 
738b4dbc599SNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
739b4dbc599SNathan Whitehorn 
740582434bdSNathan Whitehorn 	return (0);
741b4dbc599SNathan Whitehorn }
742b4dbc599SNathan Whitehorn 
7433df9e037SNathan Whitehorn #define DIFF19041970	2082844800
7443df9e037SNathan Whitehorn 
7453df9e037SNathan Whitehorn static int
7463df9e037SNathan Whitehorn cuda_gettime(device_t dev, struct timespec *ts)
7473df9e037SNathan Whitehorn {
7483df9e037SNathan Whitehorn 	struct cuda_softc *sc = device_get_softc(dev);
7493df9e037SNathan Whitehorn 	uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
7503df9e037SNathan Whitehorn 
7513df9e037SNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
7523df9e037SNathan Whitehorn 	sc->sc_rtc = -1;
7533df9e037SNathan Whitehorn 	cuda_send(sc, 1, 2, cmd);
7543df9e037SNathan Whitehorn 	if (sc->sc_rtc == -1)
7553df9e037SNathan Whitehorn 		mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
7563df9e037SNathan Whitehorn 
7573df9e037SNathan Whitehorn 	ts->tv_sec = sc->sc_rtc - DIFF19041970;
7583df9e037SNathan Whitehorn 	ts->tv_nsec = 0;
7593df9e037SNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
7603df9e037SNathan Whitehorn 
7613df9e037SNathan Whitehorn 	return (0);
7623df9e037SNathan Whitehorn }
7633df9e037SNathan Whitehorn 
7643df9e037SNathan Whitehorn static int
7653df9e037SNathan Whitehorn cuda_settime(device_t dev, struct timespec *ts)
7663df9e037SNathan Whitehorn {
7673df9e037SNathan Whitehorn 	struct cuda_softc *sc = device_get_softc(dev);
7683df9e037SNathan Whitehorn 	uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
7693df9e037SNathan Whitehorn 	uint32_t sec;
7703df9e037SNathan Whitehorn 
7713df9e037SNathan Whitehorn 	sec = ts->tv_sec + DIFF19041970;
7723df9e037SNathan Whitehorn 	memcpy(&cmd[2], &sec, sizeof(sec));
7733df9e037SNathan Whitehorn 
7743df9e037SNathan Whitehorn 	mtx_lock(&sc->sc_mutex);
7753df9e037SNathan Whitehorn 	cuda_send(sc, 0, 6, cmd);
7763df9e037SNathan Whitehorn 	mtx_unlock(&sc->sc_mutex);
7773df9e037SNathan Whitehorn 
7783df9e037SNathan Whitehorn 	return (0);
7793df9e037SNathan Whitehorn }
7803df9e037SNathan Whitehorn 
781