xref: /freebsd/sys/powerpc/powermac/cpcht.c (revision 830940567b49bb0c08dfaed40418999e76616909)
1 /*-
2  * Copyright (C) 2008 Nathan Whitehorn
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/module.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 
35 #include <dev/ofw/openfirm.h>
36 #include <dev/ofw/ofw_pci.h>
37 
38 #include <dev/pci/pcivar.h>
39 #include <dev/pci/pcireg.h>
40 
41 #include <machine/bus.h>
42 #include <machine/md_var.h>
43 #include <machine/pio.h>
44 #include <machine/resource.h>
45 
46 #include <sys/rman.h>
47 
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 #include <powerpc/powermac/cpchtvar.h>
51 
52 #include <vm/vm.h>
53 #include <vm/pmap.h>
54 
55 #include "pcib_if.h"
56 
57 #include "opt_isa.h"
58 
59 #ifdef DEV_ISA
60 #include <isa/isavar.h>
61 #endif
62 
63 static MALLOC_DEFINE(M_CPCHT, "cpcht", "CPC HT device information");
64 
65 /*
66  * HT Driver methods.
67  */
68 static int		cpcht_probe(device_t);
69 static int		cpcht_attach(device_t);
70 static ofw_bus_get_devinfo_t cpcht_get_devinfo;
71 
72 
73 static device_method_t	cpcht_methods[] = {
74 	/* Device interface */
75 	DEVMETHOD(device_probe,		cpcht_probe),
76 	DEVMETHOD(device_attach,	cpcht_attach),
77 
78 	/* Bus interface */
79 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
80 	DEVMETHOD(bus_read_ivar,	bus_generic_read_ivar),
81 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
82 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
83 	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
84 	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
85 	DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
86 
87 	/* ofw_bus interface */
88 	DEVMETHOD(ofw_bus_get_devinfo,  cpcht_get_devinfo),
89 	DEVMETHOD(ofw_bus_get_compat,   ofw_bus_gen_get_compat),
90 	DEVMETHOD(ofw_bus_get_model,    ofw_bus_gen_get_model),
91 	DEVMETHOD(ofw_bus_get_name,     ofw_bus_gen_get_name),
92 	DEVMETHOD(ofw_bus_get_node,     ofw_bus_gen_get_node),
93 	DEVMETHOD(ofw_bus_get_type,     ofw_bus_gen_get_type),
94 
95 	{ 0, 0 }
96 };
97 
98 static driver_t	cpcht_driver = {
99 	"cpcht",
100 	cpcht_methods,
101 	0
102 };
103 
104 static devclass_t	cpcht_devclass;
105 
106 DRIVER_MODULE(cpcht, nexus, cpcht_driver, cpcht_devclass, 0, 0);
107 
108 static int
109 cpcht_probe(device_t dev)
110 {
111 	const char	*type, *compatible;
112 
113 	type = ofw_bus_get_type(dev);
114 	compatible = ofw_bus_get_compat(dev);
115 
116 	if (type == NULL || compatible == NULL)
117 		return (ENXIO);
118 
119 	if (strcmp(type, "ht") != 0)
120 		return (ENXIO);
121 
122 	if (strcmp(compatible, "u3-ht") == 0) {
123 		device_set_desc(dev, "IBM CPC925 HyperTransport Tunnel");
124 		return (0);
125 	} else if (strcmp(compatible,"u4-ht") == 0) {
126 		device_set_desc(dev, "IBM CPC945 HyperTransport Tunnel");
127 		return (0);
128 	}
129 
130 	return (ENXIO);
131 }
132 
133 static int
134 cpcht_attach(device_t dev)
135 {
136 	phandle_t root, child;
137 	device_t cdev;
138 	struct ofw_bus_devinfo *dinfo;
139 	u_int32_t reg[6];
140 
141 	root = ofw_bus_get_node(dev);
142 
143 	if (OF_getprop(root, "reg", reg, sizeof(reg)) < 8)
144 		return (ENXIO);
145 
146 	for (child = OF_child(root); child != 0; child = OF_peer(child)) {
147 		dinfo = malloc(sizeof(*dinfo), M_CPCHT, M_WAITOK | M_ZERO);
148 
149                 if (ofw_bus_gen_setup_devinfo(dinfo, child) != 0) {
150                         free(dinfo, M_CPCHT);
151                         continue;
152                 }
153                 cdev = device_add_child(dev, NULL, -1);
154                 if (cdev == NULL) {
155                         device_printf(dev, "<%s>: device_add_child failed\n",
156                             dinfo->obd_name);
157                         ofw_bus_gen_destroy_devinfo(dinfo);
158                         free(dinfo, M_CPCHT);
159                         continue;
160                 }
161 		device_set_ivars(cdev, dinfo);
162 	}
163 
164 	return (bus_generic_attach(dev));
165 }
166 
167 static const struct ofw_bus_devinfo *
168 cpcht_get_devinfo(device_t dev, device_t child)
169 {
170 	return (device_get_ivars(child));
171 }
172 
173 #ifdef DEV_ISA
174 
175 /*
176  * CPC ISA Device interface.
177  */
178 static int		cpcisa_probe(device_t);
179 
180 /*
181  * Driver methods.
182  */
183 static device_method_t	cpcisa_methods[] = {
184 	/* Device interface */
185 	DEVMETHOD(device_probe,		cpcisa_probe),
186 	DEVMETHOD(device_attach,	isab_attach),
187 
188 	/* Bus interface */
189 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
190 	DEVMETHOD(bus_read_ivar,	bus_generic_read_ivar),
191 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
192 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
193 	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
194 	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
195 	DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
196 
197 	{0,0}
198 };
199 
200 static driver_t	cpcisa_driver = {
201 	"isab",
202 	cpcisa_methods,
203 	0
204 };
205 
206 DRIVER_MODULE(cpcisa, cpcht, cpcisa_driver, isab_devclass, 0, 0);
207 
208 static int
209 cpcisa_probe(device_t dev)
210 {
211 	const char	*type;
212 
213 	type = ofw_bus_get_type(dev);
214 
215 	if (type == NULL)
216 		return (ENXIO);
217 
218 	if (strcmp(type, "isa") != 0)
219 		return (ENXIO);
220 
221 	device_set_desc(dev, "HyperTransport-ISA bridge");
222 
223 	return (0);
224 }
225 
226 #endif /* DEV_ISA */
227 
228 /*
229  * CPC PCI Device interface.
230  */
231 static int		cpcpci_probe(device_t);
232 static int		cpcpci_attach(device_t);
233 
234 /*
235  * Bus interface.
236  */
237 static int		cpcpci_read_ivar(device_t, device_t, int,
238 			    uintptr_t *);
239 static struct		resource * cpcpci_alloc_resource(device_t bus,
240 			    device_t child, int type, int *rid, u_long start,
241 			    u_long end, u_long count, u_int flags);
242 static int		cpcpci_activate_resource(device_t bus, device_t child,
243 			    int type, int rid, struct resource *res);
244 
245 /*
246  * pcib interface.
247  */
248 static int		cpcpci_maxslots(device_t);
249 static u_int32_t	cpcpci_read_config(device_t, u_int, u_int, u_int,
250 			    u_int, int);
251 static void		cpcpci_write_config(device_t, u_int, u_int, u_int,
252 			    u_int, u_int32_t, int);
253 static int		cpcpci_route_interrupt(device_t, device_t, int);
254 
255 /*
256  * ofw_bus interface
257  */
258 
259 static phandle_t	cpcpci_get_node(device_t bus, device_t child);
260 
261 /*
262  * Driver methods.
263  */
264 static device_method_t	cpcpci_methods[] = {
265 	/* Device interface */
266 	DEVMETHOD(device_probe,		cpcpci_probe),
267 	DEVMETHOD(device_attach,	cpcpci_attach),
268 
269 	/* Bus interface */
270 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
271 	DEVMETHOD(bus_read_ivar,	cpcpci_read_ivar),
272 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
273 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
274 	DEVMETHOD(bus_alloc_resource,	cpcpci_alloc_resource),
275 	DEVMETHOD(bus_activate_resource,	cpcpci_activate_resource),
276 
277 	/* pcib interface */
278 	DEVMETHOD(pcib_maxslots,	cpcpci_maxslots),
279 	DEVMETHOD(pcib_read_config,	cpcpci_read_config),
280 	DEVMETHOD(pcib_write_config,	cpcpci_write_config),
281 	DEVMETHOD(pcib_route_interrupt,	cpcpci_route_interrupt),
282 
283 	/* ofw_bus interface */
284 	DEVMETHOD(ofw_bus_get_node,     cpcpci_get_node),
285 	{ 0, 0 }
286 };
287 
288 static driver_t	cpcpci_driver = {
289 	"pcib",
290 	cpcpci_methods,
291 	sizeof(struct cpcpci_softc)
292 };
293 
294 static devclass_t	cpcpci_devclass;
295 
296 DRIVER_MODULE(cpcpci, cpcht, cpcpci_driver, cpcpci_devclass, 0, 0);
297 
298 static int
299 cpcpci_probe(device_t dev)
300 {
301 	const char	*type;
302 
303 	type = ofw_bus_get_type(dev);
304 
305 	if (type == NULL)
306 		return (ENXIO);
307 
308 	if (strcmp(type, "pci") != 0)
309 		return (ENXIO);
310 
311 	device_set_desc(dev, "HyperTransport-PCI bridge");
312 
313 	return (0);
314 }
315 
316 static int
317 cpcpci_attach(device_t dev)
318 {
319 	struct		cpcpci_softc *sc;
320 	phandle_t	node;
321 	u_int32_t	reg[2], busrange[2], config_base;
322 	struct		cpcpci_range *rp, *io, *mem[2];
323 	struct		cpcpci_range fakeio;
324 	int		nmem, i;
325 
326 	node = ofw_bus_get_node(dev);
327 	sc = device_get_softc(dev);
328 
329 	if (OF_getprop(OF_parent(node), "reg", reg, sizeof(reg)) < 8)
330 		return (ENXIO);
331 
332 	if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
333 		return (ENXIO);
334 
335 	sc->sc_dev = dev;
336 	sc->sc_node = node;
337 	sc->sc_bus = busrange[0];
338 	config_base = reg[1];
339 	if (sc->sc_bus)
340 		config_base += 0x01000000UL + (sc->sc_bus << 16);
341 	sc->sc_data = (vm_offset_t)pmap_mapdev(config_base, PAGE_SIZE << 4);
342 
343 	bzero(sc->sc_range, sizeof(sc->sc_range));
344 	sc->sc_nrange = OF_getprop(node, "ranges", sc->sc_range,
345 	    sizeof(sc->sc_range));
346 
347 	if (sc->sc_nrange == -1) {
348 		device_printf(dev, "could not get ranges\n");
349 		return (ENXIO);
350 	}
351 
352 	sc->sc_range[6].pci_hi = 0;
353 	io = NULL;
354 	nmem = 0;
355 
356 	for (rp = sc->sc_range; rp->pci_hi != 0; rp++) {
357 		switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
358 		case OFW_PCI_PHYS_HI_SPACE_CONFIG:
359 			break;
360 		case OFW_PCI_PHYS_HI_SPACE_IO:
361 			io = rp;
362 			break;
363 		case OFW_PCI_PHYS_HI_SPACE_MEM32:
364 			mem[nmem] = rp;
365 			nmem++;
366 			break;
367 		case OFW_PCI_PHYS_HI_SPACE_MEM64:
368 			break;
369 		}
370 	}
371 
372 	if (io == NULL) {
373 		/*
374 		 * On at least some machines, the I/O port range is
375 		 * not exported in the OF device tree. So hardcode it.
376 		 */
377 
378 		fakeio.host_lo = 0;
379 		fakeio.pci_lo = reg[1];
380 		fakeio.size_lo = 0x00400000;
381 		if (sc->sc_bus)
382 			fakeio.pci_lo += 0x02000000UL + (sc->sc_bus << 14);
383 		io = &fakeio;
384 	}
385 	sc->sc_io_rman.rm_type = RMAN_ARRAY;
386 	sc->sc_io_rman.rm_descr = "CPC 9xx PCI I/O Ports";
387 	sc->sc_iostart = io->host_lo;
388 	if (rman_init(&sc->sc_io_rman) != 0 ||
389 	    rman_manage_region(&sc->sc_io_rman, io->pci_lo,
390 	    io->pci_lo + io->size_lo - 1) != 0) {
391 		device_printf(dev, "failed to set up io range management\n");
392 		return (ENXIO);
393 	}
394 
395 	if (nmem == 0) {
396 		device_printf(dev, "can't find mem ranges\n");
397 		return (ENXIO);
398 	}
399 	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
400 	sc->sc_mem_rman.rm_descr = "CPC 9xx PCI Memory";
401 	if (rman_init(&sc->sc_mem_rman) != 0) {
402 		device_printf(dev,
403 		    "failed to init mem range resources\n");
404 		return (ENXIO);
405 	}
406 	for (i = 0; i < nmem; i++) {
407 		if (rman_manage_region(&sc->sc_mem_rman, mem[i]->pci_lo,
408 		    mem[i]->pci_lo + mem[i]->size_lo - 1) != 0) {
409 			device_printf(dev,
410 			    "failed to set up memory range management\n");
411 			return (ENXIO);
412 		}
413 	}
414 
415 	ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(cell_t));
416 
417 	device_add_child(dev, "pci", device_get_unit(dev));
418 
419 	return (bus_generic_attach(dev));
420 }
421 
422 static int
423 cpcpci_maxslots(device_t dev)
424 {
425 
426 	return (PCI_SLOTMAX);
427 }
428 
429 static u_int32_t
430 cpcpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
431     int width)
432 {
433 	struct		cpcpci_softc *sc;
434 	vm_offset_t	caoff;
435 
436 	sc = device_get_softc(dev);
437 	caoff = sc->sc_data +
438 		(((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);
439 
440 	switch (width) {
441 	case 1:
442 		return (in8rb(caoff));
443 		break;
444 	case 2:
445 		return (in16rb(caoff));
446 		break;
447 	case 4:
448 		return (in32rb(caoff));
449 		break;
450 	}
451 
452 	return (0xffffffff);
453 }
454 
455 static void
456 cpcpci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
457     u_int reg, u_int32_t val, int width)
458 {
459 	struct		cpcpci_softc *sc;
460 	vm_offset_t	caoff;
461 
462 	sc = device_get_softc(dev);
463 	caoff = sc->sc_data +
464 		(((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);
465 
466 	switch (width) {
467 	case 1:
468 		out8rb(caoff, val);
469 		break;
470 	case 2:
471 		out16rb(caoff, val);
472 		break;
473 	case 4:
474 		out32rb(caoff, val);
475 		break;
476 	}
477 }
478 
479 static int
480 cpcpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
481 {
482 	struct	cpcpci_softc *sc;
483 
484 	sc = device_get_softc(dev);
485 
486 	switch (which) {
487 	case PCIB_IVAR_DOMAIN:
488 		*result = device_get_unit(dev);
489 		return (0);
490 	case PCIB_IVAR_BUS:
491 		*result = sc->sc_bus;
492 		return (0);
493 	}
494 
495 	return (ENOENT);
496 }
497 
498 static struct resource *
499 cpcpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
500     u_long start, u_long end, u_long count, u_int flags)
501 {
502 	struct			cpcpci_softc *sc;
503 	struct			resource *rv;
504 	struct			rman *rm;
505 	int			needactivate;
506 
507 	needactivate = flags & RF_ACTIVE;
508 	flags &= ~RF_ACTIVE;
509 
510 	sc = device_get_softc(bus);
511 
512 	switch (type) {
513 	case SYS_RES_MEMORY:
514 		rm = &sc->sc_mem_rman;
515 		break;
516 
517 	case SYS_RES_IOPORT:
518 		rm = &sc->sc_io_rman;
519 		if (rm == NULL)
520 			return (NULL);
521 		break;
522 
523 	case SYS_RES_IRQ:
524 		return (bus_alloc_resource(bus, type, rid, start, end, count,
525 		    flags));
526 
527 	default:
528 		device_printf(bus, "unknown resource request from %s\n",
529 		    device_get_nameunit(child));
530 		return (NULL);
531 	}
532 
533 	rv = rman_reserve_resource(rm, start, end, count, flags, child);
534 	if (rv == NULL) {
535 		device_printf(bus, "failed to reserve resource for %s\n",
536 		    device_get_nameunit(child));
537 		return (NULL);
538 	}
539 
540 	rman_set_rid(rv, *rid);
541 
542 	if (needactivate) {
543 		if (bus_activate_resource(child, type, *rid, rv) != 0) {
544 			device_printf(bus,
545 			    "failed to activate resource for %s\n",
546 			    device_get_nameunit(child));
547 			rman_release_resource(rv);
548 			return (NULL);
549 		}
550 	}
551 
552 	return (rv);
553 }
554 
555 static int
556 cpcpci_activate_resource(device_t bus, device_t child, int type, int rid,
557     struct resource *res)
558 {
559 	void	*p;
560 	struct	cpcpci_softc *sc;
561 
562 	sc = device_get_softc(bus);
563 
564 	if (type == SYS_RES_IRQ)
565 		return (bus_activate_resource(bus, type, rid, res));
566 
567 	if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
568 		vm_offset_t start;
569 
570 		start = (vm_offset_t)rman_get_start(res);
571 		/*
572 		 * For i/o-ports, convert the start address to the
573 		 * CPC PCI i/o window
574 		 */
575 		if (type == SYS_RES_IOPORT)
576 			start += sc->sc_iostart;
577 
578 		if (bootverbose)
579 			printf("cpcpci mapdev: start %x, len %ld\n", start,
580 			    rman_get_size(res));
581 
582 		p = pmap_mapdev(start, (vm_size_t)rman_get_size(res));
583 		if (p == NULL)
584 			return (ENOMEM);
585 		rman_set_virtual(res, p);
586 		rman_set_bustag(res, &bs_le_tag);
587 		rman_set_bushandle(res, (u_long)p);
588 	}
589 
590 	return (rman_activate_resource(res));
591 }
592 
593 static phandle_t
594 cpcpci_get_node(device_t bus, device_t dev)
595 {
596 	struct cpcpci_softc *sc;
597 
598 	sc = device_get_softc(bus);
599 	/* We only have one child, the PCI bus, which needs our own node. */
600 	return (sc->sc_node);
601 }
602 
603 static int
604 cpcpci_route_interrupt(device_t bus, device_t dev, int pin)
605 {
606 	struct cpcpci_softc *sc;
607 	struct ofw_pci_register reg;
608 	uint32_t pintr, mintr;
609 	uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
610 
611 	sc = device_get_softc(bus);
612 	pintr = pin;
613 	if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
614 	    sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
615 		return (mintr);
616 
617 	/* Maybe it's a real interrupt, not an intpin */
618 	if (pin > 4)
619 		return (pin);
620 
621 	device_printf(bus, "could not route pin %d for device %d.%d\n",
622 	    pin, pci_get_slot(dev), pci_get_function(dev));
623 	return (PCI_INVALID_IRQ);
624 }
625 
626