1 /*- 2 * Copyright (C) 2008-2010 Nathan Whitehorn 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/module.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/pciio.h> 36 #include <sys/rman.h> 37 38 #include <dev/ofw/openfirm.h> 39 #include <dev/ofw/ofw_pci.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr_machdep.h> 46 #include <machine/md_var.h> 47 #include <machine/openpicvar.h> 48 #include <machine/pio.h> 49 #include <machine/resource.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include "pcib_if.h" 58 #include "pic_if.h" 59 60 /* 61 * IBM CPC9X5 Hypertransport Device interface. 62 */ 63 static int cpcht_probe(device_t); 64 static int cpcht_attach(device_t); 65 66 static void cpcht_configure_htbridge(device_t, phandle_t); 67 68 /* 69 * Bus interface. 70 */ 71 static int cpcht_read_ivar(device_t, device_t, int, 72 uintptr_t *); 73 static struct resource *cpcht_alloc_resource(device_t bus, device_t child, 74 int type, int *rid, u_long start, u_long end, 75 u_long count, u_int flags); 76 static int cpcht_activate_resource(device_t bus, device_t child, 77 int type, int rid, struct resource *res); 78 static int cpcht_release_resource(device_t bus, device_t child, 79 int type, int rid, struct resource *res); 80 static int cpcht_deactivate_resource(device_t bus, device_t child, 81 int type, int rid, struct resource *res); 82 83 /* 84 * pcib interface. 85 */ 86 static int cpcht_maxslots(device_t); 87 static u_int32_t cpcht_read_config(device_t, u_int, u_int, u_int, 88 u_int, int); 89 static void cpcht_write_config(device_t, u_int, u_int, u_int, 90 u_int, u_int32_t, int); 91 static int cpcht_route_interrupt(device_t bus, device_t dev, 92 int pin); 93 static int cpcht_alloc_msi(device_t dev, device_t child, 94 int count, int maxcount, int *irqs); 95 static int cpcht_release_msi(device_t dev, device_t child, 96 int count, int *irqs); 97 static int cpcht_alloc_msix(device_t dev, device_t child, 98 int *irq); 99 static int cpcht_release_msix(device_t dev, device_t child, 100 int irq); 101 static int cpcht_map_msi(device_t dev, device_t child, 102 int irq, uint64_t *addr, uint32_t *data); 103 104 /* 105 * ofw_bus interface 106 */ 107 108 static phandle_t cpcht_get_node(device_t bus, device_t child); 109 110 /* 111 * Driver methods. 112 */ 113 static device_method_t cpcht_methods[] = { 114 /* Device interface */ 115 DEVMETHOD(device_probe, cpcht_probe), 116 DEVMETHOD(device_attach, cpcht_attach), 117 118 /* Bus interface */ 119 DEVMETHOD(bus_read_ivar, cpcht_read_ivar), 120 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 121 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 122 DEVMETHOD(bus_alloc_resource, cpcht_alloc_resource), 123 DEVMETHOD(bus_release_resource, cpcht_release_resource), 124 DEVMETHOD(bus_activate_resource, cpcht_activate_resource), 125 DEVMETHOD(bus_deactivate_resource, cpcht_deactivate_resource), 126 127 /* pcib interface */ 128 DEVMETHOD(pcib_maxslots, cpcht_maxslots), 129 DEVMETHOD(pcib_read_config, cpcht_read_config), 130 DEVMETHOD(pcib_write_config, cpcht_write_config), 131 DEVMETHOD(pcib_route_interrupt, cpcht_route_interrupt), 132 DEVMETHOD(pcib_alloc_msi, cpcht_alloc_msi), 133 DEVMETHOD(pcib_release_msi, cpcht_release_msi), 134 DEVMETHOD(pcib_alloc_msix, cpcht_alloc_msix), 135 DEVMETHOD(pcib_release_msix, cpcht_release_msix), 136 DEVMETHOD(pcib_map_msi, cpcht_map_msi), 137 138 /* ofw_bus interface */ 139 DEVMETHOD(ofw_bus_get_node, cpcht_get_node), 140 141 DEVMETHOD_END 142 }; 143 144 struct cpcht_irq { 145 enum { 146 IRQ_NONE, IRQ_HT, IRQ_MSI, IRQ_INTERNAL 147 } irq_type; 148 149 int ht_source; 150 151 vm_offset_t ht_base; 152 vm_offset_t apple_eoi; 153 uint32_t eoi_data; 154 int edge; 155 }; 156 157 static struct cpcht_irq *cpcht_irqmap = NULL; 158 uint32_t cpcht_msipic = 0; 159 160 struct cpcht_softc { 161 device_t sc_dev; 162 phandle_t sc_node; 163 vm_offset_t sc_data; 164 uint64_t sc_populated_slots; 165 struct rman sc_mem_rman; 166 struct rman sc_io_rman; 167 168 struct cpcht_irq htirq_map[128]; 169 struct mtx htirq_mtx; 170 }; 171 172 static driver_t cpcht_driver = { 173 "pcib", 174 cpcht_methods, 175 sizeof(struct cpcht_softc) 176 }; 177 178 static devclass_t cpcht_devclass; 179 180 DRIVER_MODULE(cpcht, nexus, cpcht_driver, cpcht_devclass, 0, 0); 181 182 #define CPCHT_IOPORT_BASE 0xf4000000UL /* Hardwired */ 183 #define CPCHT_IOPORT_SIZE 0x00400000UL 184 185 #define HTAPIC_REQUEST_EOI 0x20 186 #define HTAPIC_TRIGGER_LEVEL 0x02 187 #define HTAPIC_MASK 0x01 188 189 struct cpcht_range { 190 u_int32_t pci_hi; 191 u_int32_t pci_mid; 192 u_int32_t pci_lo; 193 u_int32_t junk; 194 u_int32_t host_hi; 195 u_int32_t host_lo; 196 u_int32_t size_hi; 197 u_int32_t size_lo; 198 }; 199 200 static int 201 cpcht_probe(device_t dev) 202 { 203 const char *type, *compatible; 204 205 type = ofw_bus_get_type(dev); 206 compatible = ofw_bus_get_compat(dev); 207 208 if (type == NULL || compatible == NULL) 209 return (ENXIO); 210 211 if (strcmp(type, "ht") != 0) 212 return (ENXIO); 213 214 if (strcmp(compatible, "u3-ht") != 0) 215 return (ENXIO); 216 217 218 device_set_desc(dev, "IBM CPC9X5 HyperTransport Tunnel"); 219 return (0); 220 } 221 222 static int 223 cpcht_attach(device_t dev) 224 { 225 struct cpcht_softc *sc; 226 phandle_t node, child; 227 u_int32_t reg[3]; 228 int i, error; 229 230 node = ofw_bus_get_node(dev); 231 sc = device_get_softc(dev); 232 233 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 12) 234 return (ENXIO); 235 236 sc->sc_dev = dev; 237 sc->sc_node = node; 238 sc->sc_populated_slots = 0; 239 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]); 240 241 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 242 sc->sc_mem_rman.rm_descr = "CPCHT Device Memory"; 243 error = rman_init(&sc->sc_mem_rman); 244 if (error) { 245 device_printf(dev, "rman_init() failed. error = %d\n", error); 246 return (error); 247 } 248 249 sc->sc_io_rman.rm_type = RMAN_ARRAY; 250 sc->sc_io_rman.rm_descr = "CPCHT I/O Memory"; 251 error = rman_init(&sc->sc_io_rman); 252 if (error) { 253 device_printf(dev, "rman_init() failed. error = %d\n", error); 254 return (error); 255 } 256 257 /* 258 * Set up the resource manager and the HT->MPIC mapping. For cpcht, 259 * the ranges are properties of the child bridges, and this is also 260 * where we get the HT interrupts properties. 261 */ 262 263 /* I/O port mappings are usually not in the device tree */ 264 rman_manage_region(&sc->sc_io_rman, 0, CPCHT_IOPORT_SIZE - 1); 265 266 bzero(sc->htirq_map, sizeof(sc->htirq_map)); 267 mtx_init(&sc->htirq_mtx, "cpcht irq", NULL, MTX_DEF); 268 for (i = 0; i < 8; i++) 269 sc->htirq_map[i].irq_type = IRQ_INTERNAL; 270 for (child = OF_child(node); child != 0; child = OF_peer(child)) 271 cpcht_configure_htbridge(dev, child); 272 273 /* Now make the mapping table available to the MPIC */ 274 cpcht_irqmap = sc->htirq_map; 275 276 device_add_child(dev, "pci", device_get_unit(dev)); 277 278 return (bus_generic_attach(dev)); 279 } 280 281 static void 282 cpcht_configure_htbridge(device_t dev, phandle_t child) 283 { 284 struct cpcht_softc *sc; 285 struct ofw_pci_register pcir; 286 struct cpcht_range ranges[7], *rp; 287 int nranges, ptr, nextptr; 288 uint32_t vend, val; 289 int i, nirq, irq; 290 u_int f, s; 291 292 sc = device_get_softc(dev); 293 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1) 294 return; 295 296 s = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 297 f = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 298 299 /* 300 * Mark this slot is populated. The remote south bridge does 301 * not like us talking to unpopulated slots on the root bus. 302 */ 303 sc->sc_populated_slots |= (1 << s); 304 305 /* 306 * Next grab this child bus's bus ranges. 307 */ 308 bzero(ranges, sizeof(ranges)); 309 nranges = OF_getprop(child, "ranges", ranges, sizeof(ranges)); 310 nranges /= sizeof(ranges[0]); 311 312 ranges[6].pci_hi = 0; 313 for (rp = ranges; rp < ranges + nranges && rp->pci_hi != 0; rp++) { 314 switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) { 315 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 316 break; 317 case OFW_PCI_PHYS_HI_SPACE_IO: 318 rman_manage_region(&sc->sc_io_rman, rp->pci_lo, 319 rp->pci_lo + rp->size_lo - 1); 320 break; 321 case OFW_PCI_PHYS_HI_SPACE_MEM32: 322 rman_manage_region(&sc->sc_mem_rman, rp->pci_lo, 323 rp->pci_lo + rp->size_lo - 1); 324 break; 325 case OFW_PCI_PHYS_HI_SPACE_MEM64: 326 panic("64-bit CPCHT reserved memory!"); 327 break; 328 } 329 } 330 331 /* 332 * Next build up any HT->MPIC mappings for this sub-bus. One would 333 * naively hope that enabling, disabling, and EOIing interrupts would 334 * cause the appropriate HT bus transactions to that effect. This is 335 * not the case. 336 * 337 * Instead, we have to muck about on the HT peer's root PCI bridges, 338 * figure out what interrupts they send, enable them, and cache 339 * the location of their WaitForEOI registers so that we can 340 * send EOIs later. 341 */ 342 343 /* All the devices we are interested in have caps */ 344 if (!(PCIB_READ_CONFIG(dev, 0, s, f, PCIR_STATUS, 2) 345 & PCIM_STATUS_CAPPRESENT)) 346 return; 347 348 nextptr = PCIB_READ_CONFIG(dev, 0, s, f, PCIR_CAP_PTR, 1); 349 while (nextptr != 0) { 350 ptr = nextptr; 351 nextptr = PCIB_READ_CONFIG(dev, 0, s, f, 352 ptr + PCICAP_NEXTPTR, 1); 353 354 /* Find the HT IRQ capabilities */ 355 if (PCIB_READ_CONFIG(dev, 0, s, f, 356 ptr + PCICAP_ID, 1) != PCIY_HT) 357 continue; 358 359 val = PCIB_READ_CONFIG(dev, 0, s, f, ptr + PCIR_HT_COMMAND, 2); 360 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_INTERRUPT) 361 continue; 362 363 /* Ask for the IRQ count */ 364 PCIB_WRITE_CONFIG(dev, 0, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1); 365 nirq = PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4); 366 nirq = ((nirq >> 16) & 0xff) + 1; 367 368 device_printf(dev, "%d HT IRQs on device %d.%d\n", nirq, s, f); 369 370 for (i = 0; i < nirq; i++) { 371 PCIB_WRITE_CONFIG(dev, 0, s, f, 372 ptr + PCIR_HT_COMMAND, 0x10 + (i << 1), 1); 373 irq = PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4); 374 375 /* 376 * Mask this interrupt for now. 377 */ 378 PCIB_WRITE_CONFIG(dev, 0, s, f, ptr + 4, 379 irq | HTAPIC_MASK, 4); 380 irq = (irq >> 16) & 0xff; 381 382 sc->htirq_map[irq].irq_type = IRQ_HT; 383 sc->htirq_map[irq].ht_source = i; 384 sc->htirq_map[irq].ht_base = sc->sc_data + 385 (((((s & 0x1f) << 3) | (f & 0x07)) << 8) | (ptr)); 386 387 PCIB_WRITE_CONFIG(dev, 0, s, f, 388 ptr + PCIR_HT_COMMAND, 0x11 + (i << 1), 1); 389 sc->htirq_map[irq].eoi_data = 390 PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4) | 391 0x80000000; 392 393 /* 394 * Apple uses a non-compliant IO/APIC that differs 395 * in how we signal EOIs. Check if this device was 396 * made by Apple, and act accordingly. 397 */ 398 vend = PCIB_READ_CONFIG(dev, 0, s, f, 399 PCIR_DEVVENDOR, 4); 400 if ((vend & 0xffff) == 0x106b) 401 sc->htirq_map[irq].apple_eoi = 402 (sc->htirq_map[irq].ht_base - ptr) + 0x60; 403 } 404 } 405 } 406 407 static int 408 cpcht_maxslots(device_t dev) 409 { 410 411 return (PCI_SLOTMAX); 412 } 413 414 static u_int32_t 415 cpcht_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 416 int width) 417 { 418 struct cpcht_softc *sc; 419 vm_offset_t caoff; 420 421 sc = device_get_softc(dev); 422 caoff = sc->sc_data + 423 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg); 424 425 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0)) 426 return (0xffffffff); 427 428 if (bus > 0) 429 caoff += 0x01000000UL + (bus << 16); 430 431 switch (width) { 432 case 1: 433 return (in8rb(caoff)); 434 break; 435 case 2: 436 return (in16rb(caoff)); 437 break; 438 case 4: 439 return (in32rb(caoff)); 440 break; 441 } 442 443 return (0xffffffff); 444 } 445 446 static void 447 cpcht_write_config(device_t dev, u_int bus, u_int slot, u_int func, 448 u_int reg, u_int32_t val, int width) 449 { 450 struct cpcht_softc *sc; 451 vm_offset_t caoff; 452 453 sc = device_get_softc(dev); 454 caoff = sc->sc_data + 455 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg); 456 457 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0)) 458 return; 459 460 if (bus > 0) 461 caoff += 0x01000000UL + (bus << 16); 462 463 switch (width) { 464 case 1: 465 out8rb(caoff, val); 466 break; 467 case 2: 468 out16rb(caoff, val); 469 break; 470 case 4: 471 out32rb(caoff, val); 472 break; 473 } 474 } 475 476 static int 477 cpcht_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 478 { 479 switch (which) { 480 case PCIB_IVAR_DOMAIN: 481 *result = device_get_unit(dev); 482 return (0); 483 case PCIB_IVAR_BUS: 484 *result = 0; /* Root bus */ 485 return (0); 486 } 487 488 return (ENOENT); 489 } 490 491 static phandle_t 492 cpcht_get_node(device_t bus, device_t dev) 493 { 494 struct cpcht_softc *sc; 495 496 sc = device_get_softc(bus); 497 /* We only have one child, the PCI bus, which needs our own node. */ 498 return (sc->sc_node); 499 } 500 501 static int 502 cpcht_route_interrupt(device_t bus, device_t dev, int pin) 503 { 504 return (pin); 505 } 506 507 static struct resource * 508 cpcht_alloc_resource(device_t bus, device_t child, int type, int *rid, 509 u_long start, u_long end, u_long count, u_int flags) 510 { 511 struct cpcht_softc *sc; 512 struct resource *rv; 513 struct rman *rm; 514 int needactivate; 515 516 needactivate = flags & RF_ACTIVE; 517 flags &= ~RF_ACTIVE; 518 519 sc = device_get_softc(bus); 520 521 switch (type) { 522 case SYS_RES_IOPORT: 523 end = min(end, start + count); 524 rm = &sc->sc_io_rman; 525 break; 526 527 case SYS_RES_MEMORY: 528 rm = &sc->sc_mem_rman; 529 break; 530 531 case SYS_RES_IRQ: 532 return (bus_alloc_resource(bus, type, rid, start, end, count, 533 flags)); 534 535 default: 536 device_printf(bus, "unknown resource request from %s\n", 537 device_get_nameunit(child)); 538 return (NULL); 539 } 540 541 rv = rman_reserve_resource(rm, start, end, count, flags, child); 542 if (rv == NULL) { 543 device_printf(bus, "failed to reserve resource for %s\n", 544 device_get_nameunit(child)); 545 return (NULL); 546 } 547 548 rman_set_rid(rv, *rid); 549 550 if (needactivate) { 551 if (bus_activate_resource(child, type, *rid, rv) != 0) { 552 device_printf(bus, 553 "failed to activate resource for %s\n", 554 device_get_nameunit(child)); 555 rman_release_resource(rv); 556 return (NULL); 557 } 558 } 559 560 return (rv); 561 } 562 563 static int 564 cpcht_activate_resource(device_t bus, device_t child, int type, int rid, 565 struct resource *res) 566 { 567 void *p; 568 569 if (type == SYS_RES_IRQ) 570 return (bus_activate_resource(bus, type, rid, res)); 571 572 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 573 vm_offset_t start; 574 575 start = (vm_offset_t)rman_get_start(res); 576 577 if (type == SYS_RES_IOPORT) 578 start += CPCHT_IOPORT_BASE; 579 580 if (bootverbose) 581 printf("cpcht mapdev: start %zx, len %ld\n", start, 582 rman_get_size(res)); 583 584 p = pmap_mapdev(start, (vm_size_t)rman_get_size(res)); 585 if (p == NULL) 586 return (ENOMEM); 587 rman_set_virtual(res, p); 588 rman_set_bustag(res, &bs_le_tag); 589 rman_set_bushandle(res, (u_long)p); 590 } 591 592 return (rman_activate_resource(res)); 593 } 594 595 static int 596 cpcht_release_resource(device_t bus, device_t child, int type, int rid, 597 struct resource *res) 598 { 599 600 if (rman_get_flags(res) & RF_ACTIVE) { 601 int error = bus_deactivate_resource(child, type, rid, res); 602 if (error) 603 return error; 604 } 605 606 return (rman_release_resource(res)); 607 } 608 609 static int 610 cpcht_deactivate_resource(device_t bus, device_t child, int type, int rid, 611 struct resource *res) 612 { 613 614 /* 615 * If this is a memory resource, unmap it. 616 */ 617 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { 618 u_int32_t psize; 619 620 psize = rman_get_size(res); 621 pmap_unmapdev((vm_offset_t)rman_get_virtual(res), psize); 622 } 623 624 return (rman_deactivate_resource(res)); 625 } 626 627 static int 628 cpcht_alloc_msi(device_t dev, device_t child, int count, int maxcount, 629 int *irqs) 630 { 631 struct cpcht_softc *sc; 632 int i, j; 633 634 sc = device_get_softc(dev); 635 j = 0; 636 637 /* Bail if no MSI PIC yet */ 638 if (cpcht_msipic == 0) 639 return (ENXIO); 640 641 mtx_lock(&sc->htirq_mtx); 642 for (i = 8; i < 124 - count; i++) { 643 for (j = 0; j < count; j++) { 644 if (sc->htirq_map[i+j].irq_type != IRQ_NONE) 645 break; 646 } 647 if (j == count) 648 break; 649 650 i += j; /* We know there isn't a large enough run */ 651 } 652 653 if (j != count) { 654 mtx_unlock(&sc->htirq_mtx); 655 return (ENXIO); 656 } 657 658 for (j = 0; j < count; j++) { 659 irqs[j] = MAP_IRQ(cpcht_msipic, i+j); 660 sc->htirq_map[i+j].irq_type = IRQ_MSI; 661 } 662 mtx_unlock(&sc->htirq_mtx); 663 664 return (0); 665 } 666 667 static int 668 cpcht_release_msi(device_t dev, device_t child, int count, int *irqs) 669 { 670 struct cpcht_softc *sc; 671 int i; 672 673 sc = device_get_softc(dev); 674 675 mtx_lock(&sc->htirq_mtx); 676 for (i = 0; i < count; i++) 677 sc->htirq_map[irqs[i] & 0xff].irq_type = IRQ_NONE; 678 mtx_unlock(&sc->htirq_mtx); 679 680 return (0); 681 } 682 683 static int 684 cpcht_alloc_msix(device_t dev, device_t child, int *irq) 685 { 686 struct cpcht_softc *sc; 687 int i; 688 689 sc = device_get_softc(dev); 690 691 /* Bail if no MSI PIC yet */ 692 if (cpcht_msipic == 0) 693 return (ENXIO); 694 695 mtx_lock(&sc->htirq_mtx); 696 for (i = 8; i < 124; i++) { 697 if (sc->htirq_map[i].irq_type == IRQ_NONE) { 698 sc->htirq_map[i].irq_type = IRQ_MSI; 699 *irq = MAP_IRQ(cpcht_msipic, i); 700 701 mtx_unlock(&sc->htirq_mtx); 702 return (0); 703 } 704 } 705 mtx_unlock(&sc->htirq_mtx); 706 707 return (ENXIO); 708 } 709 710 static int 711 cpcht_release_msix(device_t dev, device_t child, int irq) 712 { 713 struct cpcht_softc *sc; 714 715 sc = device_get_softc(dev); 716 717 mtx_lock(&sc->htirq_mtx); 718 sc->htirq_map[irq & 0xff].irq_type = IRQ_NONE; 719 mtx_unlock(&sc->htirq_mtx); 720 721 return (0); 722 } 723 724 static int 725 cpcht_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 726 uint32_t *data) 727 { 728 device_t pcib; 729 struct pci_devinfo *dinfo; 730 struct pcicfg_ht *ht = NULL; 731 732 for (pcib = child; pcib != dev; pcib = 733 device_get_parent(device_get_parent(pcib))) { 734 dinfo = device_get_ivars(pcib); 735 ht = &dinfo->cfg.ht; 736 737 if (ht == NULL) 738 continue; 739 } 740 741 if (ht == NULL) 742 return (ENXIO); 743 744 *addr = ht->ht_msiaddr; 745 *data = irq & 0xff; 746 747 return (0); 748 } 749 750 /* 751 * Driver for the integrated MPIC on U3/U4 (CPC925/CPC945) 752 */ 753 754 static int openpic_cpcht_probe(device_t); 755 static int openpic_cpcht_attach(device_t); 756 static void openpic_cpcht_config(device_t, u_int irq, 757 enum intr_trigger trig, enum intr_polarity pol); 758 static void openpic_cpcht_enable(device_t, u_int irq, u_int vector); 759 static void openpic_cpcht_unmask(device_t, u_int irq); 760 static void openpic_cpcht_eoi(device_t, u_int irq); 761 762 static device_method_t openpic_cpcht_methods[] = { 763 /* Device interface */ 764 DEVMETHOD(device_probe, openpic_cpcht_probe), 765 DEVMETHOD(device_attach, openpic_cpcht_attach), 766 767 /* PIC interface */ 768 DEVMETHOD(pic_bind, openpic_bind), 769 DEVMETHOD(pic_config, openpic_cpcht_config), 770 DEVMETHOD(pic_dispatch, openpic_dispatch), 771 DEVMETHOD(pic_enable, openpic_cpcht_enable), 772 DEVMETHOD(pic_eoi, openpic_cpcht_eoi), 773 DEVMETHOD(pic_ipi, openpic_ipi), 774 DEVMETHOD(pic_mask, openpic_mask), 775 DEVMETHOD(pic_unmask, openpic_cpcht_unmask), 776 777 { 0, 0 }, 778 }; 779 780 struct openpic_cpcht_softc { 781 struct openpic_softc sc_openpic; 782 783 struct mtx sc_ht_mtx; 784 }; 785 786 static driver_t openpic_cpcht_driver = { 787 "htpic", 788 openpic_cpcht_methods, 789 sizeof(struct openpic_cpcht_softc), 790 }; 791 792 DRIVER_MODULE(openpic, unin, openpic_cpcht_driver, openpic_devclass, 0, 0); 793 794 static int 795 openpic_cpcht_probe(device_t dev) 796 { 797 const char *type = ofw_bus_get_type(dev); 798 799 if (strcmp(type, "open-pic") != 0) 800 return (ENXIO); 801 802 device_set_desc(dev, OPENPIC_DEVSTR); 803 return (0); 804 } 805 806 static int 807 openpic_cpcht_attach(device_t dev) 808 { 809 struct openpic_cpcht_softc *sc; 810 phandle_t node; 811 int err, irq; 812 813 node = ofw_bus_get_node(dev); 814 err = openpic_common_attach(dev, node); 815 if (err != 0) 816 return (err); 817 818 /* 819 * The HT APIC stuff is not thread-safe, so we need a mutex to 820 * protect it. 821 */ 822 sc = device_get_softc(dev); 823 mtx_init(&sc->sc_ht_mtx, "htpic", NULL, MTX_SPIN); 824 825 /* 826 * Interrupts 0-3 are internally sourced and are level triggered 827 * active low. Interrupts 4-123 are connected to a pulse generator 828 * and should be programmed as edge triggered low-to-high. 829 * 830 * IBM CPC945 Manual, Section 9.3. 831 */ 832 833 for (irq = 0; irq < 4; irq++) 834 openpic_config(dev, irq, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); 835 for (irq = 4; irq < 124; irq++) 836 openpic_config(dev, irq, INTR_TRIGGER_EDGE, INTR_POLARITY_LOW); 837 838 /* 839 * Use this PIC for MSI only if it is the root PIC. This may not 840 * be necessary, but Linux does it, and I cannot find any U3 machines 841 * with MSI devices to test. 842 */ 843 if (dev == root_pic) 844 cpcht_msipic = node; 845 846 return (0); 847 } 848 849 static void 850 openpic_cpcht_config(device_t dev, u_int irq, enum intr_trigger trig, 851 enum intr_polarity pol) 852 { 853 struct openpic_cpcht_softc *sc; 854 uint32_t ht_irq; 855 856 /* 857 * The interrupt settings for the MPIC are completely determined 858 * by the internal wiring in the northbridge. Real changes to these 859 * settings need to be negotiated with the remote IO-APIC on the HT 860 * link. 861 */ 862 863 sc = device_get_softc(dev); 864 865 if (cpcht_irqmap != NULL && irq < 128 && 866 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) { 867 mtx_lock_spin(&sc->sc_ht_mtx); 868 869 /* Program the data port */ 870 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 871 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 872 873 /* Grab the IRQ config register */ 874 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 875 876 /* Mask the IRQ while we fiddle settings */ 877 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq | HTAPIC_MASK); 878 879 /* Program the interrupt sense */ 880 ht_irq &= ~(HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI); 881 if (trig == INTR_TRIGGER_EDGE) { 882 cpcht_irqmap[irq].edge = 1; 883 } else { 884 cpcht_irqmap[irq].edge = 0; 885 ht_irq |= HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI; 886 } 887 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 888 889 mtx_unlock_spin(&sc->sc_ht_mtx); 890 } 891 } 892 893 static void 894 openpic_cpcht_enable(device_t dev, u_int irq, u_int vec) 895 { 896 struct openpic_cpcht_softc *sc; 897 uint32_t ht_irq; 898 899 openpic_enable(dev, irq, vec); 900 901 sc = device_get_softc(dev); 902 903 if (cpcht_irqmap != NULL && irq < 128 && 904 cpcht_irqmap[irq].ht_base > 0) { 905 mtx_lock_spin(&sc->sc_ht_mtx); 906 907 /* Program the data port */ 908 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 909 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 910 911 /* Unmask the interrupt */ 912 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 913 ht_irq &= ~HTAPIC_MASK; 914 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 915 916 mtx_unlock_spin(&sc->sc_ht_mtx); 917 } 918 919 openpic_cpcht_eoi(dev, irq); 920 } 921 922 static void 923 openpic_cpcht_unmask(device_t dev, u_int irq) 924 { 925 struct openpic_cpcht_softc *sc; 926 uint32_t ht_irq; 927 928 openpic_unmask(dev, irq); 929 930 sc = device_get_softc(dev); 931 932 if (cpcht_irqmap != NULL && irq < 128 && 933 cpcht_irqmap[irq].ht_base > 0) { 934 mtx_lock_spin(&sc->sc_ht_mtx); 935 936 /* Program the data port */ 937 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 938 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 939 940 /* Unmask the interrupt */ 941 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 942 ht_irq &= ~HTAPIC_MASK; 943 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 944 945 mtx_unlock_spin(&sc->sc_ht_mtx); 946 } 947 948 openpic_cpcht_eoi(dev, irq); 949 } 950 951 static void 952 openpic_cpcht_eoi(device_t dev, u_int irq) 953 { 954 struct openpic_cpcht_softc *sc; 955 uint32_t off, mask; 956 957 if (irq == 255) 958 return; 959 960 sc = device_get_softc(dev); 961 962 if (cpcht_irqmap != NULL && irq < 128 && 963 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) { 964 /* If this is an HT IRQ, acknowledge it at the remote APIC */ 965 966 if (cpcht_irqmap[irq].apple_eoi) { 967 off = (cpcht_irqmap[irq].ht_source >> 3) & ~3; 968 mask = 1 << (cpcht_irqmap[irq].ht_source & 0x1f); 969 out32rb(cpcht_irqmap[irq].apple_eoi + off, mask); 970 } else { 971 mtx_lock_spin(&sc->sc_ht_mtx); 972 973 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 974 0x11 + (cpcht_irqmap[irq].ht_source << 1)); 975 out32rb(cpcht_irqmap[irq].ht_base + 4, 976 cpcht_irqmap[irq].eoi_data); 977 978 mtx_unlock_spin(&sc->sc_ht_mtx); 979 } 980 } 981 982 openpic_eoi(dev, irq); 983 } 984