1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2008-2010 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/pciio.h> 38 #include <sys/rman.h> 39 40 #include <dev/ofw/openfirm.h> 41 #include <dev/ofw/ofw_pci.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcireg.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr_machdep.h> 48 #include <machine/md_var.h> 49 #include <machine/openpicreg.h> 50 #include <machine/openpicvar.h> 51 #include <machine/pio.h> 52 #include <machine/resource.h> 53 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofwpci.h> 57 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 61 #include "pcib_if.h" 62 #include <dev/pci/pcib_private.h> 63 #include "pic_if.h" 64 65 /* 66 * IBM CPC9X5 Hypertransport Device interface. 67 */ 68 static int cpcht_probe(device_t); 69 static int cpcht_attach(device_t); 70 71 static void cpcht_configure_htbridge(device_t, phandle_t); 72 73 /* 74 * pcib interface. 75 */ 76 static u_int32_t cpcht_read_config(device_t, u_int, u_int, u_int, 77 u_int, int); 78 static void cpcht_write_config(device_t, u_int, u_int, u_int, 79 u_int, u_int32_t, int); 80 static int cpcht_route_interrupt(device_t, device_t, int); 81 static int cpcht_alloc_msi(device_t dev, device_t child, 82 int count, int maxcount, int *irqs); 83 static int cpcht_release_msi(device_t dev, device_t child, 84 int count, int *irqs); 85 static int cpcht_alloc_msix(device_t dev, device_t child, 86 int *irq); 87 static int cpcht_release_msix(device_t dev, device_t child, 88 int irq); 89 static int cpcht_map_msi(device_t dev, device_t child, 90 int irq, uint64_t *addr, uint32_t *data); 91 92 /* 93 * Driver methods. 94 */ 95 static device_method_t cpcht_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, cpcht_probe), 98 DEVMETHOD(device_attach, cpcht_attach), 99 100 /* pcib interface */ 101 DEVMETHOD(pcib_read_config, cpcht_read_config), 102 DEVMETHOD(pcib_write_config, cpcht_write_config), 103 DEVMETHOD(pcib_route_interrupt, cpcht_route_interrupt), 104 DEVMETHOD(pcib_alloc_msi, cpcht_alloc_msi), 105 DEVMETHOD(pcib_release_msi, cpcht_release_msi), 106 DEVMETHOD(pcib_alloc_msix, cpcht_alloc_msix), 107 DEVMETHOD(pcib_release_msix, cpcht_release_msix), 108 DEVMETHOD(pcib_map_msi, cpcht_map_msi), 109 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 110 111 DEVMETHOD_END 112 }; 113 114 struct cpcht_irq { 115 enum { 116 IRQ_NONE, IRQ_HT, IRQ_MSI, IRQ_INTERNAL 117 } irq_type; 118 119 int ht_source; 120 121 vm_offset_t ht_base; 122 vm_offset_t apple_eoi; 123 uint32_t eoi_data; 124 int edge; 125 }; 126 127 static struct cpcht_irq *cpcht_irqmap = NULL; 128 uint32_t cpcht_msipic = 0; 129 130 struct cpcht_softc { 131 struct ofw_pci_softc pci_sc; 132 vm_offset_t sc_data; 133 uint64_t sc_populated_slots; 134 135 struct cpcht_irq htirq_map[128]; 136 struct mtx htirq_mtx; 137 }; 138 139 static devclass_t cpcht_devclass; 140 DEFINE_CLASS_1(pcib, cpcht_driver, cpcht_methods, sizeof(struct cpcht_softc), 141 ofw_pci_driver); 142 DRIVER_MODULE(cpcht, ofwbus, cpcht_driver, cpcht_devclass, 0, 0); 143 144 #define CPCHT_IOPORT_BASE 0xf4000000UL /* Hardwired */ 145 #define CPCHT_IOPORT_SIZE 0x00400000UL 146 147 #define HTAPIC_REQUEST_EOI 0x20 148 #define HTAPIC_TRIGGER_LEVEL 0x02 149 #define HTAPIC_MASK 0x01 150 151 static int 152 cpcht_probe(device_t dev) 153 { 154 const char *type, *compatible; 155 156 type = ofw_bus_get_type(dev); 157 compatible = ofw_bus_get_compat(dev); 158 159 if (type == NULL || compatible == NULL) 160 return (ENXIO); 161 162 if (strcmp(type, "ht") != 0) 163 return (ENXIO); 164 165 if (strcmp(compatible, "u3-ht") != 0) 166 return (ENXIO); 167 168 device_set_desc(dev, "IBM CPC9X5 HyperTransport Tunnel"); 169 return (0); 170 } 171 172 static int 173 cpcht_attach(device_t dev) 174 { 175 struct cpcht_softc *sc; 176 phandle_t node, child; 177 u_int32_t reg[3]; 178 int i; 179 180 node = ofw_bus_get_node(dev); 181 sc = device_get_softc(dev); 182 183 if (OF_getencprop(node, "reg", reg, sizeof(reg)) < 12) 184 return (ENXIO); 185 186 if (OF_getproplen(node, "ranges") <= 0) 187 sc->pci_sc.sc_quirks = OFW_PCI_QUIRK_RANGES_ON_CHILDREN; 188 sc->sc_populated_slots = 0; 189 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]); 190 191 /* 192 * Set up the resource manager and the HT->MPIC mapping. For cpcht, 193 * the ranges are properties of the child bridges, and this is also 194 * where we get the HT interrupts properties. 195 */ 196 197 #if 0 198 /* I/O port mappings are usually not in the device tree */ 199 rman_manage_region(&sc->pci_sc.sc_io_rman, 0, CPCHT_IOPORT_SIZE - 1); 200 #endif 201 202 bzero(sc->htirq_map, sizeof(sc->htirq_map)); 203 mtx_init(&sc->htirq_mtx, "cpcht irq", NULL, MTX_DEF); 204 for (i = 0; i < 8; i++) 205 sc->htirq_map[i].irq_type = IRQ_INTERNAL; 206 for (child = OF_child(node); child != 0; child = OF_peer(child)) 207 cpcht_configure_htbridge(dev, child); 208 209 /* Now make the mapping table available to the MPIC */ 210 cpcht_irqmap = sc->htirq_map; 211 212 return (ofw_pci_attach(dev)); 213 } 214 215 static void 216 cpcht_configure_htbridge(device_t dev, phandle_t child) 217 { 218 struct cpcht_softc *sc; 219 struct ofw_pci_register pcir; 220 int ptr, nextptr; 221 uint32_t vend, val; 222 int i, nirq, irq; 223 u_int b, f, s; 224 225 sc = device_get_softc(dev); 226 if (OF_getencprop(child, "reg", (pcell_t *)&pcir, sizeof(pcir)) == -1) 227 return; 228 229 b = OFW_PCI_PHYS_HI_BUS(pcir.phys_hi); 230 s = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 231 f = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 232 233 /* 234 * Mark this slot is populated. The remote south bridge does 235 * not like us talking to unpopulated slots on the root bus. 236 */ 237 sc->sc_populated_slots |= (1 << s); 238 239 /* 240 * Next build up any HT->MPIC mappings for this sub-bus. One would 241 * naively hope that enabling, disabling, and EOIing interrupts would 242 * cause the appropriate HT bus transactions to that effect. This is 243 * not the case. 244 * 245 * Instead, we have to muck about on the HT peer's root PCI bridges, 246 * figure out what interrupts they send, enable them, and cache 247 * the location of their WaitForEOI registers so that we can 248 * send EOIs later. 249 */ 250 251 /* All the devices we are interested in have caps */ 252 if (!(PCIB_READ_CONFIG(dev, b, s, f, PCIR_STATUS, 2) 253 & PCIM_STATUS_CAPPRESENT)) 254 return; 255 256 nextptr = PCIB_READ_CONFIG(dev, b, s, f, PCIR_CAP_PTR, 1); 257 while (nextptr != 0) { 258 ptr = nextptr; 259 nextptr = PCIB_READ_CONFIG(dev, b, s, f, 260 ptr + PCICAP_NEXTPTR, 1); 261 262 /* Find the HT IRQ capabilities */ 263 if (PCIB_READ_CONFIG(dev, b, s, f, 264 ptr + PCICAP_ID, 1) != PCIY_HT) 265 continue; 266 267 val = PCIB_READ_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 2); 268 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_INTERRUPT) 269 continue; 270 271 /* Ask for the IRQ count */ 272 PCIB_WRITE_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1); 273 nirq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4); 274 nirq = ((nirq >> 16) & 0xff) + 1; 275 276 device_printf(dev, "%d HT IRQs on device %d.%d\n", nirq, s, f); 277 278 for (i = 0; i < nirq; i++) { 279 PCIB_WRITE_CONFIG(dev, b, s, f, 280 ptr + PCIR_HT_COMMAND, 0x10 + (i << 1), 1); 281 irq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4); 282 283 /* 284 * Mask this interrupt for now. 285 */ 286 PCIB_WRITE_CONFIG(dev, b, s, f, ptr + 4, 287 irq | HTAPIC_MASK, 4); 288 irq = (irq >> 16) & 0xff; 289 290 sc->htirq_map[irq].irq_type = IRQ_HT; 291 sc->htirq_map[irq].ht_source = i; 292 sc->htirq_map[irq].ht_base = sc->sc_data + 293 (((((s & 0x1f) << 3) | (f & 0x07)) << 8) | (ptr)); 294 295 PCIB_WRITE_CONFIG(dev, b, s, f, 296 ptr + PCIR_HT_COMMAND, 0x11 + (i << 1), 1); 297 sc->htirq_map[irq].eoi_data = 298 PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4) | 299 0x80000000; 300 301 /* 302 * Apple uses a non-compliant IO/APIC that differs 303 * in how we signal EOIs. Check if this device was 304 * made by Apple, and act accordingly. 305 */ 306 vend = PCIB_READ_CONFIG(dev, b, s, f, 307 PCIR_DEVVENDOR, 4); 308 if ((vend & 0xffff) == 0x106b) 309 sc->htirq_map[irq].apple_eoi = 310 (sc->htirq_map[irq].ht_base - ptr) + 0x60; 311 } 312 } 313 } 314 315 static u_int32_t 316 cpcht_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 317 int width) 318 { 319 struct cpcht_softc *sc; 320 vm_offset_t caoff; 321 322 sc = device_get_softc(dev); 323 caoff = sc->sc_data + 324 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg); 325 326 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0)) 327 return (0xffffffff); 328 329 if (bus > 0) 330 caoff += 0x01000000UL + (bus << 16); 331 332 switch (width) { 333 case 1: 334 return (in8rb(caoff)); 335 break; 336 case 2: 337 return (in16rb(caoff)); 338 break; 339 case 4: 340 return (in32rb(caoff)); 341 break; 342 } 343 344 return (0xffffffff); 345 } 346 347 static void 348 cpcht_write_config(device_t dev, u_int bus, u_int slot, u_int func, 349 u_int reg, u_int32_t val, int width) 350 { 351 struct cpcht_softc *sc; 352 vm_offset_t caoff; 353 354 sc = device_get_softc(dev); 355 caoff = sc->sc_data + 356 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg); 357 358 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0)) 359 return; 360 361 if (bus > 0) 362 caoff += 0x01000000UL + (bus << 16); 363 364 switch (width) { 365 case 1: 366 out8rb(caoff, val); 367 break; 368 case 2: 369 out16rb(caoff, val); 370 break; 371 case 4: 372 out32rb(caoff, val); 373 break; 374 } 375 } 376 377 static int 378 cpcht_route_interrupt(device_t bus, device_t dev, int pin) 379 { 380 return (pin); 381 } 382 383 static int 384 cpcht_alloc_msi(device_t dev, device_t child, int count, int maxcount, 385 int *irqs) 386 { 387 struct cpcht_softc *sc; 388 int i, j; 389 390 sc = device_get_softc(dev); 391 j = 0; 392 393 /* Bail if no MSI PIC yet */ 394 if (cpcht_msipic == 0) 395 return (ENXIO); 396 397 mtx_lock(&sc->htirq_mtx); 398 for (i = 8; i < 124 - count; i++) { 399 for (j = 0; j < count; j++) { 400 if (sc->htirq_map[i+j].irq_type != IRQ_NONE) 401 break; 402 } 403 if (j == count) 404 break; 405 406 i += j; /* We know there isn't a large enough run */ 407 } 408 409 if (j != count) { 410 mtx_unlock(&sc->htirq_mtx); 411 return (ENXIO); 412 } 413 414 for (j = 0; j < count; j++) { 415 irqs[j] = MAP_IRQ(cpcht_msipic, i+j); 416 sc->htirq_map[i+j].irq_type = IRQ_MSI; 417 } 418 mtx_unlock(&sc->htirq_mtx); 419 420 return (0); 421 } 422 423 static int 424 cpcht_release_msi(device_t dev, device_t child, int count, int *irqs) 425 { 426 struct cpcht_softc *sc; 427 int i; 428 429 sc = device_get_softc(dev); 430 431 mtx_lock(&sc->htirq_mtx); 432 for (i = 0; i < count; i++) 433 sc->htirq_map[irqs[i] & 0xff].irq_type = IRQ_NONE; 434 mtx_unlock(&sc->htirq_mtx); 435 436 return (0); 437 } 438 439 static int 440 cpcht_alloc_msix(device_t dev, device_t child, int *irq) 441 { 442 struct cpcht_softc *sc; 443 int i; 444 445 sc = device_get_softc(dev); 446 447 /* Bail if no MSI PIC yet */ 448 if (cpcht_msipic == 0) 449 return (ENXIO); 450 451 mtx_lock(&sc->htirq_mtx); 452 for (i = 8; i < 124; i++) { 453 if (sc->htirq_map[i].irq_type == IRQ_NONE) { 454 sc->htirq_map[i].irq_type = IRQ_MSI; 455 *irq = MAP_IRQ(cpcht_msipic, i); 456 457 mtx_unlock(&sc->htirq_mtx); 458 return (0); 459 } 460 } 461 mtx_unlock(&sc->htirq_mtx); 462 463 return (ENXIO); 464 } 465 466 static int 467 cpcht_release_msix(device_t dev, device_t child, int irq) 468 { 469 struct cpcht_softc *sc; 470 471 sc = device_get_softc(dev); 472 473 mtx_lock(&sc->htirq_mtx); 474 sc->htirq_map[irq & 0xff].irq_type = IRQ_NONE; 475 mtx_unlock(&sc->htirq_mtx); 476 477 return (0); 478 } 479 480 static int 481 cpcht_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 482 uint32_t *data) 483 { 484 device_t pcib; 485 struct pci_devinfo *dinfo; 486 struct pcicfg_ht *ht = NULL; 487 488 for (pcib = child; pcib != dev; pcib = 489 device_get_parent(device_get_parent(pcib))) { 490 dinfo = device_get_ivars(pcib); 491 ht = &dinfo->cfg.ht; 492 493 if (ht == NULL) 494 continue; 495 } 496 497 if (ht == NULL) 498 return (ENXIO); 499 500 *addr = ht->ht_msiaddr; 501 *data = irq & 0xff; 502 503 return (0); 504 } 505 506 /* 507 * Driver for the integrated MPIC on U3/U4 (CPC925/CPC945) 508 */ 509 510 static int openpic_cpcht_probe(device_t); 511 static int openpic_cpcht_attach(device_t); 512 static void openpic_cpcht_config(device_t, u_int irq, 513 enum intr_trigger trig, enum intr_polarity pol); 514 static void openpic_cpcht_enable(device_t, u_int irq, u_int vector); 515 static void openpic_cpcht_unmask(device_t, u_int irq); 516 static void openpic_cpcht_eoi(device_t, u_int irq); 517 518 static device_method_t openpic_cpcht_methods[] = { 519 /* Device interface */ 520 DEVMETHOD(device_probe, openpic_cpcht_probe), 521 DEVMETHOD(device_attach, openpic_cpcht_attach), 522 523 /* PIC interface */ 524 DEVMETHOD(pic_bind, openpic_bind), 525 DEVMETHOD(pic_config, openpic_cpcht_config), 526 DEVMETHOD(pic_dispatch, openpic_dispatch), 527 DEVMETHOD(pic_enable, openpic_cpcht_enable), 528 DEVMETHOD(pic_eoi, openpic_cpcht_eoi), 529 DEVMETHOD(pic_ipi, openpic_ipi), 530 DEVMETHOD(pic_mask, openpic_mask), 531 DEVMETHOD(pic_unmask, openpic_cpcht_unmask), 532 533 { 0, 0 }, 534 }; 535 536 struct openpic_cpcht_softc { 537 struct openpic_softc sc_openpic; 538 539 struct mtx sc_ht_mtx; 540 }; 541 542 static driver_t openpic_cpcht_driver = { 543 "htpic", 544 openpic_cpcht_methods, 545 sizeof(struct openpic_cpcht_softc), 546 }; 547 548 DRIVER_MODULE(openpic, unin, openpic_cpcht_driver, openpic_devclass, 0, 0); 549 550 static int 551 openpic_cpcht_probe(device_t dev) 552 { 553 const char *type = ofw_bus_get_type(dev); 554 555 if (strcmp(type, "open-pic") != 0) 556 return (ENXIO); 557 558 device_set_desc(dev, OPENPIC_DEVSTR); 559 return (0); 560 } 561 562 static int 563 openpic_cpcht_attach(device_t dev) 564 { 565 struct openpic_cpcht_softc *sc; 566 phandle_t node; 567 int err, irq; 568 569 node = ofw_bus_get_node(dev); 570 err = openpic_common_attach(dev, node); 571 if (err != 0) 572 return (err); 573 574 /* 575 * The HT APIC stuff is not thread-safe, so we need a mutex to 576 * protect it. 577 */ 578 sc = device_get_softc(dev); 579 mtx_init(&sc->sc_ht_mtx, "htpic", NULL, MTX_SPIN); 580 581 /* 582 * Interrupts 0-3 are internally sourced and are level triggered 583 * active low. Interrupts 4-123 are connected to a pulse generator 584 * and should be programmed as edge triggered low-to-high. 585 * 586 * IBM CPC945 Manual, Section 9.3. 587 */ 588 589 for (irq = 0; irq < 4; irq++) 590 openpic_config(dev, irq, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); 591 for (irq = 4; irq < 124; irq++) 592 openpic_config(dev, irq, INTR_TRIGGER_EDGE, INTR_POLARITY_LOW); 593 594 /* 595 * Use this PIC for MSI only if it is the root PIC. This may not 596 * be necessary, but Linux does it, and I cannot find any U3 machines 597 * with MSI devices to test. 598 */ 599 if (dev == root_pic) 600 cpcht_msipic = node; 601 602 return (0); 603 } 604 605 static void 606 openpic_cpcht_config(device_t dev, u_int irq, enum intr_trigger trig, 607 enum intr_polarity pol) 608 { 609 struct openpic_cpcht_softc *sc; 610 uint32_t ht_irq; 611 612 /* 613 * The interrupt settings for the MPIC are completely determined 614 * by the internal wiring in the northbridge. Real changes to these 615 * settings need to be negotiated with the remote IO-APIC on the HT 616 * link. 617 */ 618 619 sc = device_get_softc(dev); 620 621 if (cpcht_irqmap != NULL && irq < 128 && 622 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) { 623 mtx_lock_spin(&sc->sc_ht_mtx); 624 625 /* Program the data port */ 626 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 627 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 628 629 /* Grab the IRQ config register */ 630 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 631 632 /* Mask the IRQ while we fiddle settings */ 633 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq | HTAPIC_MASK); 634 635 /* Program the interrupt sense */ 636 ht_irq &= ~(HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI); 637 if (trig == INTR_TRIGGER_EDGE) { 638 cpcht_irqmap[irq].edge = 1; 639 } else { 640 cpcht_irqmap[irq].edge = 0; 641 ht_irq |= HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI; 642 } 643 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 644 645 mtx_unlock_spin(&sc->sc_ht_mtx); 646 } 647 } 648 649 static void 650 openpic_cpcht_enable(device_t dev, u_int irq, u_int vec) 651 { 652 struct openpic_cpcht_softc *sc; 653 uint32_t ht_irq; 654 655 openpic_enable(dev, irq, vec); 656 657 sc = device_get_softc(dev); 658 659 if (cpcht_irqmap != NULL && irq < 128 && 660 cpcht_irqmap[irq].ht_base > 0) { 661 mtx_lock_spin(&sc->sc_ht_mtx); 662 663 /* Program the data port */ 664 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 665 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 666 667 /* Unmask the interrupt */ 668 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 669 ht_irq &= ~HTAPIC_MASK; 670 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 671 672 mtx_unlock_spin(&sc->sc_ht_mtx); 673 } 674 675 openpic_cpcht_eoi(dev, irq); 676 } 677 678 static void 679 openpic_cpcht_unmask(device_t dev, u_int irq) 680 { 681 struct openpic_cpcht_softc *sc; 682 uint32_t ht_irq; 683 684 openpic_unmask(dev, irq); 685 686 sc = device_get_softc(dev); 687 688 if (cpcht_irqmap != NULL && irq < 128 && 689 cpcht_irqmap[irq].ht_base > 0) { 690 mtx_lock_spin(&sc->sc_ht_mtx); 691 692 /* Program the data port */ 693 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 694 0x10 + (cpcht_irqmap[irq].ht_source << 1)); 695 696 /* Unmask the interrupt */ 697 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4); 698 ht_irq &= ~HTAPIC_MASK; 699 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq); 700 701 mtx_unlock_spin(&sc->sc_ht_mtx); 702 } 703 704 openpic_cpcht_eoi(dev, irq); 705 } 706 707 static void 708 openpic_cpcht_eoi(device_t dev, u_int irq) 709 { 710 struct openpic_cpcht_softc *sc; 711 uint32_t off, mask; 712 713 if (irq == 255) 714 return; 715 716 sc = device_get_softc(dev); 717 718 if (cpcht_irqmap != NULL && irq < 128 && 719 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) { 720 /* If this is an HT IRQ, acknowledge it at the remote APIC */ 721 722 if (cpcht_irqmap[irq].apple_eoi) { 723 off = (cpcht_irqmap[irq].ht_source >> 3) & ~3; 724 mask = 1 << (cpcht_irqmap[irq].ht_source & 0x1f); 725 out32rb(cpcht_irqmap[irq].apple_eoi + off, mask); 726 } else { 727 mtx_lock_spin(&sc->sc_ht_mtx); 728 729 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND, 730 0x11 + (cpcht_irqmap[irq].ht_source << 1)); 731 out32rb(cpcht_irqmap[irq].ht_base + 4, 732 cpcht_irqmap[irq].eoi_data); 733 734 mtx_unlock_spin(&sc->sc_ht_mtx); 735 } 736 } 737 738 openpic_eoi(dev, irq); 739 } 740