1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Justin Hibbits 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/systm.h> 33 #include <sys/module.h> 34 #include <sys/kernel.h> 35 #include <sys/rman.h> 36 #include <sys/sysctl.h> 37 38 #include <machine/bus.h> 39 40 #include <dev/ofw/openfirm.h> 41 #include <dev/pci/pcivar.h> 42 43 #ifndef PCI_VENDOR_ID_ATI 44 #define PCI_VENDOR_ID_ATI 0x1002 45 #endif 46 47 /* From the xf86-video-ati driver's radeon_reg.h */ 48 #define RADEON_LVDS_GEN_CNTL 0x02d0 49 #define RADEON_LVDS_ON (1 << 0) 50 #define RADEON_LVDS_DISPLAY_DIS (1 << 1) 51 #define RADEON_LVDS_PANEL_TYPE (1 << 2) 52 #define RADEON_LVDS_PANEL_FORMAT (1 << 3) 53 #define RADEON_LVDS_RST_FM (1 << 6) 54 #define RADEON_LVDS_EN (1 << 7) 55 #define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 56 #define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) 57 #define RADEON_LVDS_BL_MOD_EN (1 << 16) 58 #define RADEON_LVDS_DIGON (1 << 18) 59 #define RADEON_LVDS_BLON (1 << 19) 60 #define RADEON_LVDS_PLL_CNTL 0x02d4 61 #define RADEON_LVDS_PLL_EN (1 << 16) 62 #define RADEON_LVDS_PLL_RESET (1 << 17) 63 #define RADEON_PIXCLKS_CNTL 0x002d 64 #define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 65 #define RADEON_DISP_PWR_MAN 0x0d08 66 #define RADEON_AUTO_PWRUP_EN (1 << 26) 67 #define RADEON_CLOCK_CNTL_DATA 0x000c 68 #define RADEON_CLOCK_CNTL_INDEX 0x0008 69 #define RADEON_PLL_WR_EN (1 << 7) 70 #define RADEON_CRTC_GEN_CNTL 0x0050 71 72 struct atibl_softc { 73 struct resource *sc_memr; 74 int sc_level; 75 }; 76 77 static void atibl_identify(driver_t *driver, device_t parent); 78 static int atibl_probe(device_t dev); 79 static int atibl_attach(device_t dev); 80 static int atibl_setlevel(struct atibl_softc *sc, int newlevel); 81 static int atibl_getlevel(struct atibl_softc *sc); 82 static int atibl_resume(device_t dev); 83 static int atibl_suspend(device_t dev); 84 static int atibl_sysctl(SYSCTL_HANDLER_ARGS); 85 86 static device_method_t atibl_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_identify, atibl_identify), 89 DEVMETHOD(device_probe, atibl_probe), 90 DEVMETHOD(device_attach, atibl_attach), 91 DEVMETHOD(device_suspend, atibl_suspend), 92 DEVMETHOD(device_resume, atibl_resume), 93 {0, 0}, 94 }; 95 96 static driver_t atibl_driver = { 97 "backlight", 98 atibl_methods, 99 sizeof(struct atibl_softc) 100 }; 101 102 DRIVER_MODULE(atibl, vgapci, atibl_driver, 0, 0); 103 104 static void 105 atibl_identify(driver_t *driver, device_t parent) 106 { 107 if (OF_finddevice("mac-io/backlight") == -1) 108 return; 109 if (device_find_child(parent, "backlight", -1) == NULL) 110 device_add_child(parent, "backlight", -1); 111 } 112 113 static int 114 atibl_probe(device_t dev) 115 { 116 char control[8]; 117 phandle_t handle; 118 119 handle = OF_finddevice("mac-io/backlight"); 120 121 if (handle == -1) 122 return (ENXIO); 123 124 if (OF_getprop(handle, "backlight-control", &control, sizeof(control)) < 0) 125 return (ENXIO); 126 127 if (strcmp(control, "ati") != 0 && 128 (strcmp(control, "mnca") != 0 || 129 pci_get_vendor(device_get_parent(dev)) != 0x1002)) 130 return (ENXIO); 131 132 device_set_desc(dev, "PowerBook backlight for ATI graphics"); 133 134 return (0); 135 } 136 137 static int 138 atibl_attach(device_t dev) 139 { 140 struct atibl_softc *sc; 141 struct sysctl_ctx_list *ctx; 142 struct sysctl_oid *tree; 143 int rid; 144 145 sc = device_get_softc(dev); 146 147 rid = 0x18; /* BAR[2], for the MMIO register */ 148 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 149 RF_ACTIVE | RF_SHAREABLE); 150 if (sc->sc_memr == NULL) { 151 device_printf(dev, "Could not alloc mem resource!\n"); 152 return (ENXIO); 153 } 154 155 ctx = device_get_sysctl_ctx(dev); 156 tree = device_get_sysctl_tree(dev); 157 158 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 159 "level", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 160 atibl_sysctl, "I", "Backlight level (0-100)"); 161 162 return (0); 163 } 164 165 static uint32_t __inline 166 atibl_pll_rreg(struct atibl_softc *sc, uint32_t reg) 167 { 168 uint32_t data, save, tmp; 169 170 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f)); 171 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 172 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); 173 174 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 175 176 /* Only necessary on R300, but won't hurt others. */ 177 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); 178 tmp = save & (~0x3f | RADEON_PLL_WR_EN); 179 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp); 180 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 181 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save); 182 183 return data; 184 } 185 186 static void __inline 187 atibl_pll_wreg(struct atibl_softc *sc, uint32_t reg, uint32_t val) 188 { 189 uint32_t save, tmp; 190 191 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, 192 ((reg & 0x3f) | RADEON_PLL_WR_EN)); 193 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 194 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); 195 196 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val); 197 DELAY(5000); 198 199 /* Only necessary on R300, but won't hurt others. */ 200 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); 201 tmp = save & (~0x3f | RADEON_PLL_WR_EN); 202 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp); 203 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 204 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save); 205 } 206 207 static int 208 atibl_setlevel(struct atibl_softc *sc, int newlevel) 209 { 210 uint32_t lvds_gen_cntl; 211 uint32_t lvds_pll_cntl; 212 uint32_t pixclks_cntl; 213 uint32_t disp_pwr_reg; 214 215 if (newlevel > 100) 216 newlevel = 100; 217 218 if (newlevel < 0) 219 newlevel = 0; 220 221 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); 222 223 if (newlevel > 0) { 224 newlevel = (newlevel * 5) / 2 + 5; 225 disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN); 226 disp_pwr_reg |= RADEON_AUTO_PWRUP_EN; 227 bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg); 228 lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL); 229 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 230 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 231 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 232 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 233 DELAY(1000); 234 235 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 236 RADEON_LVDS_BL_MOD_LEVEL_MASK); 237 lvds_gen_cntl |= RADEON_LVDS_ON | RADEON_LVDS_EN | 238 RADEON_LVDS_DIGON | RADEON_LVDS_BLON; 239 lvds_gen_cntl |= (newlevel << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 240 RADEON_LVDS_BL_MOD_LEVEL_MASK; 241 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 242 DELAY(200000); 243 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 244 } else { 245 pixclks_cntl = atibl_pll_rreg(sc, RADEON_PIXCLKS_CNTL); 246 atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL, 247 pixclks_cntl & ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 248 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 249 lvds_gen_cntl &= ~(RADEON_LVDS_BL_MOD_EN | RADEON_LVDS_BL_MOD_LEVEL_MASK); 250 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 251 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 252 DELAY(200000); 253 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 254 255 atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL, pixclks_cntl); 256 DELAY(200000); 257 } 258 259 return (0); 260 } 261 262 static int 263 atibl_getlevel(struct atibl_softc *sc) 264 { 265 uint32_t lvds_gen_cntl; 266 int level; 267 268 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); 269 270 level = ((lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> 271 RADEON_LVDS_BL_MOD_LEVEL_SHIFT); 272 if (level != 0) 273 level = ((level - 5) * 2) / 5; 274 275 return (level); 276 } 277 278 static int 279 atibl_suspend(device_t dev) 280 { 281 struct atibl_softc *sc; 282 283 sc = device_get_softc(dev); 284 285 sc->sc_level = atibl_getlevel(sc); 286 atibl_setlevel(sc, 0); 287 288 return (0); 289 } 290 291 static int 292 atibl_resume(device_t dev) 293 { 294 struct atibl_softc *sc; 295 296 sc = device_get_softc(dev); 297 298 atibl_setlevel(sc, sc->sc_level); 299 300 return (0); 301 } 302 303 static int 304 atibl_sysctl(SYSCTL_HANDLER_ARGS) 305 { 306 struct atibl_softc *sc; 307 int newlevel, error; 308 309 sc = arg1; 310 311 newlevel = atibl_getlevel(sc); 312 313 error = sysctl_handle_int(oidp, &newlevel, 0, req); 314 315 if (error || !req->newptr) 316 return (error); 317 318 return (atibl_setlevel(sc, newlevel)); 319 } 320