xref: /freebsd/sys/powerpc/powermac/ata_macio.c (revision 7aa383846770374466b1dcb2cefd71bde9acf463)
1 /*-
2  * Copyright 2002 by Peter Grehan. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  *    derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  */
29 
30 /*
31  * Mac-io ATA controller
32  */
33 #include "opt_ata.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/malloc.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <sys/ata.h>
48 #include <dev/ata/ata-all.h>
49 #include <ata_if.h>
50 
51 #include <dev/ofw/ofw_bus.h>
52 
53 #include "ata_dbdma.h"
54 
55 /*
56  * Offset to control registers from base
57  */
58 #define ATA_MACIO_ALTOFFSET	0x160
59 
60 /*
61  * Define the gap between registers
62  */
63 #define ATA_MACIO_REGGAP	16
64 
65 /*
66  * Whether or not to bind to the DBDMA IRQ
67  */
68 #define USE_DBDMA_IRQ		0
69 
70 /*
71  * Timing register
72  */
73 #define ATA_MACIO_TIMINGREG	0x200
74 
75 #define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30)
76 #define PIO_REC_OFFSET 4
77 #define PIO_REC_MIN 1
78 #define PIO_ACT_MIN 1
79 #define DMA_REC_OFFSET 1
80 #define DMA_REC_MIN 1
81 #define DMA_ACT_MIN 1
82 
83 struct ide_timings {
84 	int cycle;      /* minimum cycle time [ns] */
85 	int active;     /* minimum command active time [ns] */
86 };
87 
88 struct ide_timings pio_timings[5] = {
89 	{ 600, 180 },	/* PIO 0 */
90 	{ 390, 150 },	/* PIO 1 */
91 	{ 240, 105 },	/* PIO 2 */
92 	{ 180,  90 },	/* PIO 3 */
93 	{ 120,  75 }	/* PIO 4 */
94 };
95 
96 static const struct ide_timings dma_timings[3] = {
97 	{ 480, 240 },	/* WDMA 0 */
98 	{ 165,  90 },	/* WDMA 1 */
99 	{ 120,  75 }	/* WDMA 2 */
100 };
101 
102 static const struct ide_timings udma_timings[5] = {
103         { 120, 180 },	/* UDMA 0 */
104         {  90, 150 },	/* UDMA 1 */
105         {  60, 120 },	/* UDMA 2 */
106         {  45,  90 },	/* UDMA 3 */
107         {  30,  90 }	/* UDMA 4 */
108 };
109 
110 /*
111  * Define the macio ata bus attachment.
112  */
113 static  int  ata_macio_probe(device_t dev);
114 static  int  ata_macio_setmode(device_t dev, int target, int mode);
115 static  int  ata_macio_attach(device_t dev);
116 static  int  ata_macio_begin_transaction(struct ata_request *request);
117 
118 static device_method_t ata_macio_methods[] = {
119         /* Device interface */
120 	DEVMETHOD(device_probe,		ata_macio_probe),
121 	DEVMETHOD(device_attach,        ata_macio_attach),
122 
123 	/* ATA interface */
124 	DEVMETHOD(ata_setmode,		ata_macio_setmode),
125 	{ 0, 0 }
126 };
127 
128 struct ata_macio_softc {
129 	struct ata_dbdma_channel sc_ch;
130 
131 	int rev;
132 	int max_mode;
133 	struct resource *sc_mem;
134 
135 	uint32_t udmaconf[2];
136 	uint32_t wdmaconf[2];
137 	uint32_t pioconf[2];
138 };
139 
140 static driver_t ata_macio_driver = {
141 	"ata",
142 	ata_macio_methods,
143 	sizeof(struct ata_macio_softc),
144 };
145 
146 DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, 0, 0);
147 MODULE_DEPEND(ata, ata, 1, 1, 1);
148 
149 static int
150 ata_macio_probe(device_t dev)
151 {
152 	const char *type = ofw_bus_get_type(dev);
153 	const char *name = ofw_bus_get_name(dev);
154 	struct ata_macio_softc *sc;
155 	struct ata_channel *ch;
156 	int rid, i;
157 
158 	if (strcmp(type, "ata") != 0 &&
159 	    strcmp(type, "ide") != 0)
160 		return (ENXIO);
161 
162 	sc = device_get_softc(dev);
163 	bzero(sc, sizeof(struct ata_macio_softc));
164 	ch = &sc->sc_ch.sc_ch;
165 
166 	if (strcmp(name,"ata-4") == 0) {
167 		device_set_desc(dev,"Apple MacIO Ultra ATA Controller");
168 		sc->rev = 4;
169 		sc->max_mode = ATA_UDMA4;
170 	} else {
171 		device_set_desc(dev,"Apple MacIO ATA Controller");
172 		sc->rev = 3;
173 		sc->max_mode = ATA_WDMA2;
174 	}
175 
176 	rid = 0;
177 	sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
178 	    RF_ACTIVE);
179 	if (sc->sc_mem == NULL) {
180 		device_printf(dev, "could not allocate memory\n");
181 		return (ENXIO);
182 	}
183 
184 	/*
185 	 * Set up the resource vectors
186 	 */
187 	for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
188 		ch->r_io[i].res = sc->sc_mem;
189 		ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
190 	}
191 	ch->r_io[ATA_CONTROL].res = sc->sc_mem;
192 	ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
193 	ata_default_registers(dev);
194 
195 	ch->unit = 0;
196 	ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA;
197 	ata_generic_hw(dev);
198 
199 	return (ata_probe(dev));
200 }
201 
202 static int
203 ata_macio_attach(device_t dev)
204 {
205 	struct ata_macio_softc *sc = device_get_softc(dev);
206 	uint32_t timingreg;
207 
208 #if USE_DBDMA_IRQ
209 	int dbdma_irq_rid = 1;
210 	struct resource *dbdma_irq;
211 	void *cookie;
212 #endif
213 
214 	/* Init DMA engine */
215 
216 	sc->sc_ch.dbdma_rid = 1;
217 	sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
218 	    &sc->sc_ch.dbdma_rid, RF_ACTIVE);
219 
220 	ata_dbdma_dmainit(dev);
221 
222 	/* Configure initial timings */
223 	timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG);
224 	if (sc->rev == 4) {
225 		sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000;
226 		sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00;
227 		sc->pioconf[0]  = sc->pioconf[1]  = timingreg & 0x000003ff;
228 	} else {
229 		sc->udmaconf[0] = sc->udmaconf[1] = 0;
230 		sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800;
231 		sc->pioconf[0]  = sc->pioconf[1]  = timingreg & 0x000007ff;
232 	}
233 
234 #if USE_DBDMA_IRQ
235 	/* Bind to DBDMA interrupt as well */
236 
237 	if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
238 	    &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
239 		bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
240 			(driver_intr_t *)ata_interrupt, sc,&cookie);
241 	}
242 #endif
243 
244 	/* Set begin_transaction */
245 	sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
246 
247 	return ata_attach(dev);
248 }
249 
250 static int
251 ata_macio_setmode(device_t dev, int target, int mode)
252 {
253 	struct ata_macio_softc *sc = device_get_softc(dev);
254 
255 	int min_cycle = 0, min_active = 0;
256         int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
257 
258 	mode = min(mode, sc->max_mode);
259 
260 	if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
261 		min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
262 		min_active = udma_timings[mode & ATA_MODE_MASK].active;
263 
264 		cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
265 		act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
266 
267 		/* mask: 0x1ff00000 */
268 		sc->udmaconf[target] =
269 		    (cycle_tick << 21) | (act_tick << 25) | 0x100000;
270 	} else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
271 		min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
272 		min_active = dma_timings[mode & ATA_MODE_MASK].active;
273 
274 		cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
275 		act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
276 
277 		if (sc->rev == 4) {
278 			inact_tick = cycle_tick - act_tick;
279 			/* mask: 0x001ffc00 */
280 			sc->wdmaconf[target] =
281 			    (act_tick << 10) | (inact_tick << 15);
282 		} else {
283 			inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
284 			if (inact_tick < DMA_REC_MIN)
285 				inact_tick = DMA_REC_MIN;
286 			half_tick = 0;  /* XXX */
287 
288 			/* mask: 0xfffff800 */
289 			sc->wdmaconf[target] = (half_tick << 21)
290 			    | (inact_tick << 16) | (act_tick << 11);
291 		}
292 	} else {
293 		min_cycle =
294 		    pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
295 		min_active =
296 		    pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
297 
298 		cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
299 		act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
300 
301 		if (sc->rev == 4) {
302 			inact_tick = cycle_tick - act_tick;
303 
304 			/* mask: 0x000003ff */
305 			sc->pioconf[target] =
306 			    (inact_tick << 5) | act_tick;
307 		} else {
308 			if (act_tick < PIO_ACT_MIN)
309 				act_tick = PIO_ACT_MIN;
310 
311 			inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
312 			if (inact_tick < PIO_REC_MIN)
313 				inact_tick = PIO_REC_MIN;
314 
315 			/* mask: 0x000007ff */
316 			sc->pioconf[target] =
317 			    (inact_tick << 5) | act_tick;
318 		}
319 	}
320 
321 	return (mode);
322 }
323 
324 static int
325 ata_macio_begin_transaction(struct ata_request *request)
326 {
327 	struct ata_macio_softc *sc = device_get_softc(request->parent);
328 
329 	bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,
330 	    sc->udmaconf[request->unit] | sc->wdmaconf[request->unit]
331 	    | sc->pioconf[request->unit]);
332 
333 	return ata_begin_transaction(request);
334 }
335 
336