1 /*- 2 * Copyright 2002 by Peter Grehan. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Mac-io ATA controller 33 */ 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/malloc.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <sys/ata.h> 48 #include <dev/ata/ata-all.h> 49 #include <ata_if.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 53 #include "ata_dbdma.h" 54 55 /* 56 * Offset to control registers from base 57 */ 58 #define ATA_MACIO_ALTOFFSET 0x160 59 60 /* 61 * Define the gap between registers 62 */ 63 #define ATA_MACIO_REGGAP 16 64 65 /* 66 * Whether or not to bind to the DBDMA IRQ 67 */ 68 #define USE_DBDMA_IRQ 0 69 70 /* 71 * Timing register 72 */ 73 #define ATA_MACIO_TIMINGREG 0x200 74 75 #define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30) 76 #define PIO_REC_OFFSET 4 77 #define PIO_REC_MIN 1 78 #define PIO_ACT_MIN 1 79 #define DMA_REC_OFFSET 1 80 #define DMA_REC_MIN 1 81 #define DMA_ACT_MIN 1 82 83 struct ide_timings { 84 int cycle; /* minimum cycle time [ns] */ 85 int active; /* minimum command active time [ns] */ 86 }; 87 88 static const struct ide_timings pio_timings[5] = { 89 { 600, 180 }, /* PIO 0 */ 90 { 390, 150 }, /* PIO 1 */ 91 { 240, 105 }, /* PIO 2 */ 92 { 180, 90 }, /* PIO 3 */ 93 { 120, 75 } /* PIO 4 */ 94 }; 95 96 static const struct ide_timings dma_timings[3] = { 97 { 480, 240 }, /* WDMA 0 */ 98 { 165, 90 }, /* WDMA 1 */ 99 { 120, 75 } /* WDMA 2 */ 100 }; 101 102 static const struct ide_timings udma_timings[5] = { 103 { 120, 180 }, /* UDMA 0 */ 104 { 90, 150 }, /* UDMA 1 */ 105 { 60, 120 }, /* UDMA 2 */ 106 { 45, 90 }, /* UDMA 3 */ 107 { 30, 90 } /* UDMA 4 */ 108 }; 109 110 /* 111 * Define the macio ata bus attachment. 112 */ 113 static int ata_macio_probe(device_t dev); 114 static int ata_macio_setmode(device_t dev, int target, int mode); 115 static int ata_macio_attach(device_t dev); 116 static int ata_macio_begin_transaction(struct ata_request *request); 117 static int ata_macio_suspend(device_t dev); 118 static int ata_macio_resume(device_t dev); 119 120 static device_method_t ata_macio_methods[] = { 121 /* Device interface */ 122 DEVMETHOD(device_probe, ata_macio_probe), 123 DEVMETHOD(device_attach, ata_macio_attach), 124 DEVMETHOD(device_suspend, ata_macio_suspend), 125 DEVMETHOD(device_resume, ata_macio_resume), 126 127 /* ATA interface */ 128 DEVMETHOD(ata_setmode, ata_macio_setmode), 129 DEVMETHOD_END 130 }; 131 132 struct ata_macio_softc { 133 struct ata_dbdma_channel sc_ch; 134 135 int rev; 136 int max_mode; 137 struct resource *sc_mem; 138 139 uint32_t udmaconf[2]; 140 uint32_t wdmaconf[2]; 141 uint32_t pioconf[2]; 142 }; 143 144 static driver_t ata_macio_driver = { 145 "ata", 146 ata_macio_methods, 147 sizeof(struct ata_macio_softc), 148 }; 149 150 DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, NULL, NULL); 151 MODULE_DEPEND(ata, ata, 1, 1, 1); 152 153 static int 154 ata_macio_probe(device_t dev) 155 { 156 const char *type = ofw_bus_get_type(dev); 157 const char *name = ofw_bus_get_name(dev); 158 struct ata_macio_softc *sc; 159 160 if (strcmp(type, "ata") != 0 && 161 strcmp(type, "ide") != 0) 162 return (ENXIO); 163 164 sc = device_get_softc(dev); 165 bzero(sc, sizeof(struct ata_macio_softc)); 166 167 if (strcmp(name,"ata-4") == 0) { 168 device_set_desc(dev,"Apple MacIO Ultra ATA Controller"); 169 sc->rev = 4; 170 sc->max_mode = ATA_UDMA4; 171 } else { 172 device_set_desc(dev,"Apple MacIO ATA Controller"); 173 sc->rev = 3; 174 sc->max_mode = ATA_WDMA2; 175 } 176 177 return (ata_probe(dev)); 178 } 179 180 static int 181 ata_macio_attach(device_t dev) 182 { 183 struct ata_macio_softc *sc = device_get_softc(dev); 184 uint32_t timingreg; 185 struct ata_channel *ch; 186 int rid, i; 187 188 /* 189 * Allocate resources 190 */ 191 192 rid = 0; 193 ch = &sc->sc_ch.sc_ch; 194 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 195 RF_ACTIVE); 196 if (sc->sc_mem == NULL) { 197 device_printf(dev, "could not allocate memory\n"); 198 return (ENXIO); 199 } 200 201 /* 202 * Set up the resource vectors 203 */ 204 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 205 ch->r_io[i].res = sc->sc_mem; 206 ch->r_io[i].offset = i * ATA_MACIO_REGGAP; 207 } 208 ch->r_io[ATA_CONTROL].res = sc->sc_mem; 209 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET; 210 ata_default_registers(dev); 211 212 ch->unit = 0; 213 ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA; 214 ata_generic_hw(dev); 215 216 #if USE_DBDMA_IRQ 217 int dbdma_irq_rid = 1; 218 struct resource *dbdma_irq; 219 void *cookie; 220 #endif 221 222 /* Init DMA engine */ 223 224 sc->sc_ch.dbdma_rid = 1; 225 sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 226 &sc->sc_ch.dbdma_rid, RF_ACTIVE); 227 228 ata_dbdma_dmainit(dev); 229 230 /* Configure initial timings */ 231 timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG); 232 if (sc->rev == 4) { 233 sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000; 234 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00; 235 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000003ff; 236 } else { 237 sc->udmaconf[0] = sc->udmaconf[1] = 0; 238 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800; 239 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000007ff; 240 } 241 242 #if USE_DBDMA_IRQ 243 /* Bind to DBDMA interrupt as well */ 244 245 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 246 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) { 247 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL, 248 (driver_intr_t *)ata_interrupt, sc,&cookie); 249 } 250 #endif 251 252 /* Set begin_transaction */ 253 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction; 254 255 return ata_attach(dev); 256 } 257 258 static int 259 ata_macio_setmode(device_t dev, int target, int mode) 260 { 261 struct ata_macio_softc *sc = device_get_softc(dev); 262 263 int min_cycle = 0, min_active = 0; 264 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 265 266 mode = min(mode, sc->max_mode); 267 268 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) { 269 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle; 270 min_active = udma_timings[mode & ATA_MODE_MASK].active; 271 272 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 273 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 274 275 /* mask: 0x1ff00000 */ 276 sc->udmaconf[target] = 277 (cycle_tick << 21) | (act_tick << 25) | 0x100000; 278 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) { 279 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle; 280 min_active = dma_timings[mode & ATA_MODE_MASK].active; 281 282 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 283 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 284 285 if (sc->rev == 4) { 286 inact_tick = cycle_tick - act_tick; 287 /* mask: 0x001ffc00 */ 288 sc->wdmaconf[target] = 289 (act_tick << 10) | (inact_tick << 15); 290 } else { 291 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 292 if (inact_tick < DMA_REC_MIN) 293 inact_tick = DMA_REC_MIN; 294 half_tick = 0; /* XXX */ 295 296 /* mask: 0xfffff800 */ 297 sc->wdmaconf[target] = (half_tick << 21) 298 | (inact_tick << 16) | (act_tick << 11); 299 } 300 } else { 301 min_cycle = 302 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle; 303 min_active = 304 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active; 305 306 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 307 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 308 309 if (sc->rev == 4) { 310 inact_tick = cycle_tick - act_tick; 311 312 /* mask: 0x000003ff */ 313 sc->pioconf[target] = 314 (inact_tick << 5) | act_tick; 315 } else { 316 if (act_tick < PIO_ACT_MIN) 317 act_tick = PIO_ACT_MIN; 318 319 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 320 if (inact_tick < PIO_REC_MIN) 321 inact_tick = PIO_REC_MIN; 322 323 /* mask: 0x000007ff */ 324 sc->pioconf[target] = 325 (inact_tick << 5) | act_tick; 326 } 327 } 328 329 return (mode); 330 } 331 332 static int 333 ata_macio_begin_transaction(struct ata_request *request) 334 { 335 struct ata_macio_softc *sc = device_get_softc(request->parent); 336 337 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG, 338 sc->udmaconf[request->unit] | sc->wdmaconf[request->unit] 339 | sc->pioconf[request->unit]); 340 341 return ata_begin_transaction(request); 342 } 343 344 static int 345 ata_macio_suspend(device_t dev) 346 { 347 struct ata_dbdma_channel *ch = device_get_softc(dev); 348 int error; 349 350 if (!ch->sc_ch.attached) 351 return (0); 352 353 error = ata_suspend(dev); 354 dbdma_save_state(ch->dbdma); 355 356 return (error); 357 } 358 359 static int 360 ata_macio_resume(device_t dev) 361 { 362 struct ata_dbdma_channel *ch = device_get_softc(dev); 363 int error; 364 365 if (!ch->sc_ch.attached) 366 return (0); 367 368 dbdma_restore_state(ch->dbdma); 369 error = ata_resume(dev); 370 371 return (error); 372 } 373 374