xref: /freebsd/sys/powerpc/powermac/ata_kauai.c (revision aca5021d5f7dcab1e11692923266373e35322d9a)
1 /*-
2  * Copyright 2004 by Peter Grehan. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  *    derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 /*
32  * Mac 'Kauai' PCI ATA controller
33  */
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/malloc.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <sys/ata.h>
48 #include <dev/ata/ata-all.h>
49 #include <ata_if.h>
50 
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <machine/intr_machdep.h>
54 
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcireg.h>
57 
58 #include "ata_dbdma.h"
59 
60 #define  ATA_KAUAI_REGOFFSET	0x2000
61 #define  ATA_KAUAI_DBDMAOFFSET	0x1000
62 
63 /*
64  * Offset to alt-control register from base
65  */
66 #define  ATA_KAUAI_ALTOFFSET    (ATA_KAUAI_REGOFFSET + 0x160)
67 
68 /*
69  * Define the gap between registers
70  */
71 #define ATA_KAUAI_REGGAP        16
72 
73 /*
74  * PIO and DMA access registers
75  */
76 #define PIO_CONFIG_REG	(ATA_KAUAI_REGOFFSET + 0x200)
77 #define UDMA_CONFIG_REG	(ATA_KAUAI_REGOFFSET + 0x210)
78 #define DMA_IRQ_REG	(ATA_KAUAI_REGOFFSET + 0x300)
79 
80 #define USE_DBDMA_IRQ	0
81 
82 /*
83  * Define the kauai pci bus attachment.
84  */
85 static  int  ata_kauai_probe(device_t dev);
86 static  int  ata_kauai_attach(device_t dev);
87 static  int  ata_kauai_setmode(device_t dev, int target, int mode);
88 static  int  ata_kauai_begin_transaction(struct ata_request *request);
89 
90 static device_method_t ata_kauai_methods[] = {
91         /* Device interface */
92 	DEVMETHOD(device_probe,		ata_kauai_probe),
93 	DEVMETHOD(device_attach,	ata_kauai_attach),
94 	DEVMETHOD(device_detach,	bus_generic_detach),
95 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
96 	DEVMETHOD(device_suspend,	bus_generic_suspend),
97 	DEVMETHOD(device_resume,	bus_generic_resume),
98 
99 	/* ATA interface */
100 	DEVMETHOD(ata_setmode,		ata_kauai_setmode),
101 	DEVMETHOD_END
102 };
103 
104 struct ata_kauai_softc {
105 	struct ata_dbdma_channel sc_ch;
106 
107 	struct resource *sc_memr;
108 
109 	int shasta;
110 
111 	uint32_t udmaconf[2];
112 	uint32_t wdmaconf[2];
113 	uint32_t pioconf[2];
114 };
115 
116 static driver_t ata_kauai_driver = {
117 	"ata",
118 	ata_kauai_methods,
119 	sizeof(struct ata_kauai_softc),
120 };
121 
122 DRIVER_MODULE(ata, pci, ata_kauai_driver, ata_devclass, NULL, NULL);
123 MODULE_DEPEND(ata, ata, 1, 1, 1);
124 
125 /*
126  * PCI ID search table
127  */
128 static const struct kauai_pci_dev {
129         u_int32_t	kpd_devid;
130         const char	*kpd_desc;
131 } kauai_pci_devlist[] = {
132         { 0x0033106b, "Uninorth2 Kauai ATA Controller" },
133         { 0x003b106b, "Intrepid Kauai ATA Controller" },
134         { 0x0043106b, "K2 Kauai ATA Controller" },
135         { 0x0050106b, "Shasta Kauai ATA Controller" },
136         { 0x0069106b, "Intrepid-2 Kauai ATA Controller" },
137         { 0, NULL }
138 };
139 
140 /*
141  * IDE transfer timings
142  */
143 #define KAUAI_PIO_MASK	0xff000fff
144 #define KAUAI_DMA_MASK	0x00fff000
145 #define KAUAI_UDMA_MASK	0x0000ffff
146 
147 static const u_int pio_timing_kauai[] = {
148 	0x08000a92,	/* PIO0 */
149 	0x0800060f,	/* PIO1 */
150 	0x0800038b,	/* PIO2 */
151 	0x05000249,	/* PIO3 */
152 	0x04000148	/* PIO4 */
153 };
154 
155 static const u_int pio_timing_shasta[] = {
156 	0x0a000c97,	/* PIO0 */
157 	0x07000712,	/* PIO1 */
158 	0x040003cd,	/* PIO2 */
159 	0x0400028b,	/* PIO3 */
160 	0x0400010a	/* PIO4 */
161 };
162 
163 static const u_int dma_timing_kauai[] = {
164         0x00618000,	/* WDMA0 */
165         0x00209000,	/* WDMA1 */
166         0x00148000	/* WDMA2 */
167 };
168 
169 static const u_int dma_timing_shasta[] = {
170         0x00820800,	/* WDMA0 */
171         0x0028b000,	/* WDMA1 */
172         0x001ca000	/* WDMA2 */
173 };
174 
175 static const u_int udma_timing_kauai[] = {
176         0x000070c1,	/* UDMA0 */
177         0x00005d81,	/* UDMA1 */
178         0x00004a61,	/* UDMA2 */
179         0x00003a51,	/* UDMA3 */
180         0x00002a31,	/* UDMA4 */
181         0x00002921	/* UDMA5 */
182 };
183 
184 static const u_int udma_timing_shasta[] = {
185         0x00035901,	/* UDMA0 */
186         0x000348b1,	/* UDMA1 */
187         0x00033881,	/* UDMA2 */
188         0x00033861,	/* UDMA3 */
189         0x00033841,	/* UDMA4 */
190         0x00033031,	/* UDMA5 */
191         0x00033021	/* UDMA6 */
192 };
193 
194 static int
195 ata_kauai_probe(device_t dev)
196 {
197 	struct ata_channel *ch;
198 	struct ata_kauai_softc *sc;
199 	u_int32_t devid;
200 	phandle_t node;
201 	const char *compatstring = NULL;
202 	int i, found, rid;
203 
204 	found = 0;
205 	devid = pci_get_devid(dev);
206         for (i = 0; kauai_pci_devlist[i].kpd_desc != NULL; i++) {
207                 if (devid == kauai_pci_devlist[i].kpd_devid) {
208 			found = 1;
209                         device_set_desc(dev, kauai_pci_devlist[i].kpd_desc);
210 		}
211 	}
212 
213 	if (!found)
214 		return (ENXIO);
215 
216 	node = ofw_bus_get_node(dev);
217 	sc = device_get_softc(dev);
218 	bzero(sc, sizeof(struct ata_kauai_softc));
219 	ch = &sc->sc_ch.sc_ch;
220 
221 	compatstring = ofw_bus_get_compat(dev);
222 	if (compatstring != NULL && strcmp(compatstring,"shasta-ata") == 0)
223 		sc->shasta = 1;
224 
225 	/* Pre-K2 controllers apparently need this hack */
226 	if (!sc->shasta &&
227 	    (compatstring == NULL || strcmp(compatstring, "K2-UATA") != 0))
228 		bus_set_resource(dev, SYS_RES_IRQ, 0, 39, 1);
229 
230         rid = PCIR_BARS;
231 	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
232 	    RF_ACTIVE);
233         if (sc->sc_memr == NULL) {
234                 device_printf(dev, "could not allocate memory\n");
235                 return (ENXIO);
236         }
237 
238 	/*
239 	 * Set up the resource vectors
240 	 */
241         for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
242                 ch->r_io[i].res = sc->sc_memr;
243                 ch->r_io[i].offset = i*ATA_KAUAI_REGGAP + ATA_KAUAI_REGOFFSET;
244         }
245         ch->r_io[ATA_CONTROL].res = sc->sc_memr;
246         ch->r_io[ATA_CONTROL].offset = ATA_KAUAI_ALTOFFSET;
247 	ata_default_registers(dev);
248 
249 	ch->unit = 0;
250 	ch->flags |= ATA_USE_16BIT;
251 
252 	/* XXX: ATAPI DMA is unreliable. We should find out why. */
253 	ch->flags |= ATA_NO_ATAPI_DMA;
254 	ata_generic_hw(dev);
255 
256         return (ata_probe(dev));
257 }
258 
259 #if USE_DBDMA_IRQ
260 static int
261 ata_kauai_dma_interrupt(struct ata_kauai_softc *sc)
262 {
263 	/* Clear the DMA interrupt bits */
264 
265 	bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000);
266 
267 	return ata_interrupt(sc);
268 }
269 #endif
270 
271 static int
272 ata_kauai_attach(device_t dev)
273 {
274 	struct ata_kauai_softc *sc = device_get_softc(dev);
275 #if USE_DBDMA_IRQ
276 	int dbdma_irq_rid = 1;
277 	struct resource *dbdma_irq;
278 	void *cookie;
279 #endif
280 
281 	pci_enable_busmaster(dev);
282 
283 	/* Init DMA engine */
284 
285 	sc->sc_ch.dbdma_rid = 1;
286 	sc->sc_ch.dbdma_regs = sc->sc_memr;
287 	sc->sc_ch.dbdma_offset = ATA_KAUAI_DBDMAOFFSET;
288 
289 	ata_dbdma_dmainit(dev);
290 
291 #if USE_DBDMA_IRQ
292 	/* Bind to DBDMA interrupt as well */
293 	if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
294 	    &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
295 		bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
296 		    (driver_intr_t *)ata_kauai_dma_interrupt, sc,&cookie);
297 	}
298 #endif
299 
300 	/* Set up initial mode */
301 	sc->pioconf[0] = sc->pioconf[1] =
302 	    bus_read_4(sc->sc_memr, PIO_CONFIG_REG) & 0x0f000fff;
303 
304 	sc->udmaconf[0] = sc->udmaconf[1] = 0;
305 	sc->wdmaconf[0] = sc->wdmaconf[1] = 0;
306 
307 	/* Magic FCR value from Apple */
308 	bus_write_4(sc->sc_memr, 0, 0x00000007);
309 
310 	/* Set begin_transaction */
311 	sc->sc_ch.sc_ch.hw.begin_transaction = ata_kauai_begin_transaction;
312 
313 	return ata_attach(dev);
314 }
315 
316 static int
317 ata_kauai_setmode(device_t dev, int target, int mode)
318 {
319 	struct ata_kauai_softc *sc = device_get_softc(dev);
320 
321 	mode = min(mode,sc->shasta ? ATA_UDMA6 : ATA_UDMA5);
322 
323 	if (sc->shasta) {
324 		switch (mode & ATA_DMA_MASK) {
325 		    case ATA_UDMA0:
326 			sc->udmaconf[target]
327 			    = udma_timing_shasta[mode & ATA_MODE_MASK];
328 			break;
329 		    case ATA_WDMA0:
330 			sc->udmaconf[target] = 0;
331 			sc->wdmaconf[target]
332 			    = dma_timing_shasta[mode & ATA_MODE_MASK];
333 			break;
334 		    default:
335 			sc->pioconf[target]
336 			    = pio_timing_shasta[(mode & ATA_MODE_MASK) -
337 			    ATA_PIO0];
338 			break;
339 		}
340 	} else {
341 		switch (mode & ATA_DMA_MASK) {
342 		    case ATA_UDMA0:
343 			sc->udmaconf[target]
344 			    = udma_timing_kauai[mode & ATA_MODE_MASK];
345 			break;
346 		    case ATA_WDMA0:
347 			sc->udmaconf[target] = 0;
348 			sc->wdmaconf[target]
349 			    = dma_timing_kauai[mode & ATA_MODE_MASK];
350 			break;
351 		    default:
352 			sc->pioconf[target]
353 			    = pio_timing_kauai[(mode & ATA_MODE_MASK)
354 			    - ATA_PIO0];
355 			break;
356 		}
357 	}
358 
359 	return (mode);
360 }
361 
362 static int
363 ata_kauai_begin_transaction(struct ata_request *request)
364 {
365 	struct ata_kauai_softc *sc = device_get_softc(request->parent);
366 
367 	bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[request->unit]);
368 	bus_write_4(sc->sc_memr, PIO_CONFIG_REG,
369 	    sc->wdmaconf[request->unit] | sc->pioconf[request->unit]);
370 
371 	return ata_begin_transaction(request);
372 }
373