1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2004 by Peter Grehan. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Mac 'Kauai' PCI ATA controller 35 */ 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/bus.h> 41 #include <sys/malloc.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <sys/ata.h> 50 #include <dev/ata/ata-all.h> 51 #include <ata_if.h> 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <machine/intr_machdep.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 60 #include "ata_dbdma.h" 61 62 #define ATA_KAUAI_REGOFFSET 0x2000 63 #define ATA_KAUAI_DBDMAOFFSET 0x1000 64 65 /* 66 * Offset to alt-control register from base 67 */ 68 #define ATA_KAUAI_ALTOFFSET (ATA_KAUAI_REGOFFSET + 0x160) 69 70 /* 71 * Define the gap between registers 72 */ 73 #define ATA_KAUAI_REGGAP 16 74 75 /* 76 * PIO and DMA access registers 77 */ 78 #define PIO_CONFIG_REG (ATA_KAUAI_REGOFFSET + 0x200) 79 #define UDMA_CONFIG_REG (ATA_KAUAI_REGOFFSET + 0x210) 80 #define DMA_IRQ_REG (ATA_KAUAI_REGOFFSET + 0x300) 81 82 #define USE_DBDMA_IRQ 0 83 84 /* 85 * Define the kauai pci bus attachment. 86 */ 87 static int ata_kauai_probe(device_t dev); 88 static int ata_kauai_attach(device_t dev); 89 static int ata_kauai_setmode(device_t dev, int target, int mode); 90 static int ata_kauai_begin_transaction(struct ata_request *request); 91 92 static device_method_t ata_kauai_methods[] = { 93 /* Device interface */ 94 DEVMETHOD(device_probe, ata_kauai_probe), 95 DEVMETHOD(device_attach, ata_kauai_attach), 96 DEVMETHOD(device_detach, bus_generic_detach), 97 DEVMETHOD(device_shutdown, bus_generic_shutdown), 98 DEVMETHOD(device_suspend, bus_generic_suspend), 99 DEVMETHOD(device_resume, bus_generic_resume), 100 101 /* ATA interface */ 102 DEVMETHOD(ata_setmode, ata_kauai_setmode), 103 DEVMETHOD_END 104 }; 105 106 struct ata_kauai_softc { 107 struct ata_dbdma_channel sc_ch; 108 109 struct resource *sc_memr; 110 111 int shasta; 112 113 uint32_t udmaconf[2]; 114 uint32_t wdmaconf[2]; 115 uint32_t pioconf[2]; 116 }; 117 118 static driver_t ata_kauai_driver = { 119 "ata", 120 ata_kauai_methods, 121 sizeof(struct ata_kauai_softc), 122 }; 123 124 DRIVER_MODULE(ata, pci, ata_kauai_driver, ata_devclass, NULL, NULL); 125 MODULE_DEPEND(ata, ata, 1, 1, 1); 126 127 /* 128 * PCI ID search table 129 */ 130 static const struct kauai_pci_dev { 131 u_int32_t kpd_devid; 132 const char *kpd_desc; 133 } kauai_pci_devlist[] = { 134 { 0x0033106b, "Uninorth2 Kauai ATA Controller" }, 135 { 0x003b106b, "Intrepid Kauai ATA Controller" }, 136 { 0x0043106b, "K2 Kauai ATA Controller" }, 137 { 0x0050106b, "Shasta Kauai ATA Controller" }, 138 { 0x0069106b, "Intrepid-2 Kauai ATA Controller" }, 139 { 0, NULL } 140 }; 141 142 /* 143 * IDE transfer timings 144 */ 145 #define KAUAI_PIO_MASK 0xff000fff 146 #define KAUAI_DMA_MASK 0x00fff000 147 #define KAUAI_UDMA_MASK 0x0000ffff 148 149 static const u_int pio_timing_kauai[] = { 150 0x08000a92, /* PIO0 */ 151 0x0800060f, /* PIO1 */ 152 0x0800038b, /* PIO2 */ 153 0x05000249, /* PIO3 */ 154 0x04000148 /* PIO4 */ 155 }; 156 157 static const u_int pio_timing_shasta[] = { 158 0x0a000c97, /* PIO0 */ 159 0x07000712, /* PIO1 */ 160 0x040003cd, /* PIO2 */ 161 0x0400028b, /* PIO3 */ 162 0x0400010a /* PIO4 */ 163 }; 164 165 static const u_int dma_timing_kauai[] = { 166 0x00618000, /* WDMA0 */ 167 0x00209000, /* WDMA1 */ 168 0x00148000 /* WDMA2 */ 169 }; 170 171 static const u_int dma_timing_shasta[] = { 172 0x00820800, /* WDMA0 */ 173 0x0028b000, /* WDMA1 */ 174 0x001ca000 /* WDMA2 */ 175 }; 176 177 static const u_int udma_timing_kauai[] = { 178 0x000070c1, /* UDMA0 */ 179 0x00005d81, /* UDMA1 */ 180 0x00004a61, /* UDMA2 */ 181 0x00003a51, /* UDMA3 */ 182 0x00002a31, /* UDMA4 */ 183 0x00002921 /* UDMA5 */ 184 }; 185 186 static const u_int udma_timing_shasta[] = { 187 0x00035901, /* UDMA0 */ 188 0x000348b1, /* UDMA1 */ 189 0x00033881, /* UDMA2 */ 190 0x00033861, /* UDMA3 */ 191 0x00033841, /* UDMA4 */ 192 0x00033031, /* UDMA5 */ 193 0x00033021 /* UDMA6 */ 194 }; 195 196 static int 197 ata_kauai_probe(device_t dev) 198 { 199 struct ata_kauai_softc *sc; 200 u_int32_t devid; 201 phandle_t node; 202 const char *compatstring = NULL; 203 int i, found; 204 205 found = 0; 206 devid = pci_get_devid(dev); 207 for (i = 0; kauai_pci_devlist[i].kpd_desc != NULL; i++) { 208 if (devid == kauai_pci_devlist[i].kpd_devid) { 209 found = 1; 210 device_set_desc(dev, kauai_pci_devlist[i].kpd_desc); 211 } 212 } 213 214 if (!found) 215 return (ENXIO); 216 217 node = ofw_bus_get_node(dev); 218 sc = device_get_softc(dev); 219 bzero(sc, sizeof(struct ata_kauai_softc)); 220 221 compatstring = ofw_bus_get_compat(dev); 222 if (compatstring != NULL && strcmp(compatstring,"shasta-ata") == 0) 223 sc->shasta = 1; 224 225 /* Pre-K2 controllers apparently need this hack */ 226 if (!sc->shasta && 227 (compatstring == NULL || strcmp(compatstring, "K2-UATA") != 0)) 228 bus_set_resource(dev, SYS_RES_IRQ, 0, 39, 1); 229 230 return (ata_probe(dev)); 231 } 232 233 #if USE_DBDMA_IRQ 234 static int 235 ata_kauai_dma_interrupt(struct ata_kauai_softc *sc) 236 { 237 /* Clear the DMA interrupt bits */ 238 239 bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000); 240 241 return ata_interrupt(sc); 242 } 243 #endif 244 245 static int 246 ata_kauai_attach(device_t dev) 247 { 248 struct ata_kauai_softc *sc = device_get_softc(dev); 249 struct ata_channel *ch; 250 int i, rid; 251 #if USE_DBDMA_IRQ 252 int dbdma_irq_rid = 1; 253 struct resource *dbdma_irq; 254 void *cookie; 255 #endif 256 257 ch = &sc->sc_ch.sc_ch; 258 259 rid = PCIR_BARS; 260 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 261 RF_ACTIVE); 262 if (sc->sc_memr == NULL) { 263 device_printf(dev, "could not allocate memory\n"); 264 return (ENXIO); 265 } 266 267 /* 268 * Set up the resource vectors 269 */ 270 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 271 ch->r_io[i].res = sc->sc_memr; 272 ch->r_io[i].offset = i*ATA_KAUAI_REGGAP + ATA_KAUAI_REGOFFSET; 273 } 274 ch->r_io[ATA_CONTROL].res = sc->sc_memr; 275 ch->r_io[ATA_CONTROL].offset = ATA_KAUAI_ALTOFFSET; 276 ata_default_registers(dev); 277 278 ch->unit = 0; 279 ch->flags |= ATA_USE_16BIT; 280 281 /* XXX: ATAPI DMA is unreliable. We should find out why. */ 282 ch->flags |= ATA_NO_ATAPI_DMA; 283 ata_generic_hw(dev); 284 285 pci_enable_busmaster(dev); 286 287 /* Init DMA engine */ 288 289 sc->sc_ch.dbdma_rid = 1; 290 sc->sc_ch.dbdma_regs = sc->sc_memr; 291 sc->sc_ch.dbdma_offset = ATA_KAUAI_DBDMAOFFSET; 292 293 ata_dbdma_dmainit(dev); 294 295 #if USE_DBDMA_IRQ 296 /* Bind to DBDMA interrupt as well */ 297 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 298 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) { 299 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL, 300 (driver_intr_t *)ata_kauai_dma_interrupt, sc,&cookie); 301 } 302 #endif 303 304 /* Set up initial mode */ 305 sc->pioconf[0] = sc->pioconf[1] = 306 bus_read_4(sc->sc_memr, PIO_CONFIG_REG) & 0x0f000fff; 307 308 sc->udmaconf[0] = sc->udmaconf[1] = 0; 309 sc->wdmaconf[0] = sc->wdmaconf[1] = 0; 310 311 /* Magic FCR value from Apple */ 312 bus_write_4(sc->sc_memr, 0, 0x00000007); 313 314 /* Set begin_transaction */ 315 sc->sc_ch.sc_ch.hw.begin_transaction = ata_kauai_begin_transaction; 316 317 return ata_attach(dev); 318 } 319 320 static int 321 ata_kauai_setmode(device_t dev, int target, int mode) 322 { 323 struct ata_kauai_softc *sc = device_get_softc(dev); 324 325 mode = min(mode,sc->shasta ? ATA_UDMA6 : ATA_UDMA5); 326 327 if (sc->shasta) { 328 switch (mode & ATA_DMA_MASK) { 329 case ATA_UDMA0: 330 sc->udmaconf[target] 331 = udma_timing_shasta[mode & ATA_MODE_MASK]; 332 break; 333 case ATA_WDMA0: 334 sc->udmaconf[target] = 0; 335 sc->wdmaconf[target] 336 = dma_timing_shasta[mode & ATA_MODE_MASK]; 337 break; 338 default: 339 sc->pioconf[target] 340 = pio_timing_shasta[(mode & ATA_MODE_MASK) - 341 ATA_PIO0]; 342 break; 343 } 344 } else { 345 switch (mode & ATA_DMA_MASK) { 346 case ATA_UDMA0: 347 sc->udmaconf[target] 348 = udma_timing_kauai[mode & ATA_MODE_MASK]; 349 break; 350 case ATA_WDMA0: 351 sc->udmaconf[target] = 0; 352 sc->wdmaconf[target] 353 = dma_timing_kauai[mode & ATA_MODE_MASK]; 354 break; 355 default: 356 sc->pioconf[target] 357 = pio_timing_kauai[(mode & ATA_MODE_MASK) 358 - ATA_PIO0]; 359 break; 360 } 361 } 362 363 return (mode); 364 } 365 366 static int 367 ata_kauai_begin_transaction(struct ata_request *request) 368 { 369 struct ata_kauai_softc *sc = device_get_softc(request->parent); 370 371 bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[request->unit]); 372 bus_write_4(sc->sc_memr, PIO_CONFIG_REG, 373 sc->wdmaconf[request->unit] | sc->pioconf[request->unit]); 374 375 return ata_begin_transaction(request); 376 } 377