1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice unmodified, this list of conditions, and the following 15 * disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/libkern.h> 39 #include <sys/module.h> 40 #include <sys/pciio.h> 41 #include <sys/sbuf.h> 42 #include <sys/smp.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #include <dev/ofw/ofw_pci.h> 47 #include <dev/ofw/openfirm.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr_machdep.h> 51 #include <machine/resource.h> 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pci_private.h> 56 57 #include "ofw_pcibus.h" 58 #include "pcib_if.h" 59 #include "pci_if.h" 60 61 typedef uint32_t ofw_pci_intr_t; 62 63 /* Methods */ 64 static device_probe_t ofw_pcibus_probe; 65 static device_attach_t ofw_pcibus_attach; 66 static pci_alloc_devinfo_t ofw_pcibus_alloc_devinfo; 67 static pci_assign_interrupt_t ofw_pcibus_assign_interrupt; 68 static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo; 69 static bus_child_deleted_t ofw_pcibus_child_deleted; 70 static int ofw_pcibus_child_pnpinfo_method(device_t cbdev, device_t child, 71 struct sbuf *sb); 72 73 static void ofw_pcibus_enum_devtree(device_t dev, u_int domain, u_int busno); 74 static void ofw_pcibus_enum_bus(device_t dev, u_int domain, u_int busno); 75 76 static device_method_t ofw_pcibus_methods[] = { 77 /* Device interface */ 78 DEVMETHOD(device_probe, ofw_pcibus_probe), 79 DEVMETHOD(device_attach, ofw_pcibus_attach), 80 81 /* Bus interface */ 82 DEVMETHOD(bus_child_deleted, ofw_pcibus_child_deleted), 83 DEVMETHOD(bus_child_pnpinfo, ofw_pcibus_child_pnpinfo_method), 84 DEVMETHOD(bus_rescan, bus_null_rescan), 85 DEVMETHOD(bus_get_cpus, ofw_pcibus_get_cpus), 86 DEVMETHOD(bus_get_domain, ofw_pcibus_get_domain), 87 88 /* PCI interface */ 89 DEVMETHOD(pci_alloc_devinfo, ofw_pcibus_alloc_devinfo), 90 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt), 91 92 /* ofw_bus interface */ 93 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo), 94 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 95 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 96 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 97 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 98 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 99 100 DEVMETHOD_END 101 }; 102 103 DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 104 sizeof(struct pci_softc), pci_driver); 105 EARLY_DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, 0, 0, BUS_PASS_BUS); 106 MODULE_VERSION(ofw_pcibus, 1); 107 MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1); 108 109 static int ofw_devices_only = 0; 110 TUNABLE_INT("hw.pci.ofw_devices_only", &ofw_devices_only); 111 112 static int 113 ofw_pcibus_probe(device_t dev) 114 { 115 116 if (ofw_bus_get_node(dev) == -1) 117 return (ENXIO); 118 device_set_desc(dev, "OFW PCI bus"); 119 120 return (BUS_PROBE_DEFAULT); 121 } 122 123 static int 124 ofw_pcibus_attach(device_t dev) 125 { 126 u_int busno, domain; 127 int error; 128 129 error = pci_attach_common(dev); 130 if (error) 131 return (error); 132 domain = pcib_get_domain(dev); 133 busno = pcib_get_bus(dev); 134 135 /* 136 * Attach those children represented in the device tree. 137 */ 138 139 ofw_pcibus_enum_devtree(dev, domain, busno); 140 141 /* 142 * We now attach any laggard devices. FDT, for instance, allows 143 * the device tree to enumerate only some PCI devices. Apple's 144 * OF device tree on some Grackle-based hardware can also miss 145 * functions on multi-function cards. 146 */ 147 148 if (!ofw_devices_only) 149 ofw_pcibus_enum_bus(dev, domain, busno); 150 151 return (bus_generic_attach(dev)); 152 } 153 154 struct pci_devinfo * 155 ofw_pcibus_alloc_devinfo(device_t dev) 156 { 157 struct ofw_pcibus_devinfo *dinfo; 158 159 dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO); 160 return (&dinfo->opd_dinfo); 161 } 162 163 static void 164 ofw_pcibus_enum_devtree(device_t dev, u_int domain, u_int busno) 165 { 166 device_t pcib; 167 struct ofw_pci_register pcir; 168 struct ofw_pcibus_devinfo *dinfo; 169 phandle_t node, child; 170 u_int func, slot; 171 int intline; 172 173 pcib = device_get_parent(dev); 174 node = ofw_bus_get_node(dev); 175 176 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 177 if (OF_getencprop(child, "reg", (pcell_t *)&pcir, 178 sizeof(pcir)) == -1) 179 continue; 180 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 181 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 182 183 /* Some OFW device trees contain dupes. */ 184 if (pci_find_dbsf(domain, busno, slot, func) != NULL) 185 continue; 186 187 /* 188 * The preset in the intline register is usually bogus. Reset 189 * it such that the PCI code will reroute the interrupt if 190 * needed. 191 */ 192 193 intline = PCI_INVALID_IRQ; 194 if (OF_getproplen(child, "interrupts") > 0) 195 intline = 0; 196 PCIB_WRITE_CONFIG(pcib, busno, slot, func, PCIR_INTLINE, 197 intline, 1); 198 199 /* 200 * Now set up the PCI and OFW bus layer devinfo and add it 201 * to the PCI bus. 202 */ 203 204 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, dev, 205 domain, busno, slot, func); 206 if (dinfo == NULL) 207 continue; 208 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 209 0) { 210 pci_freecfg((struct pci_devinfo *)dinfo); 211 continue; 212 } 213 dinfo->opd_dma_tag = NULL; 214 pci_add_child(dev, (struct pci_devinfo *)dinfo); 215 216 /* 217 * Some devices don't have an intpin set, but do have 218 * interrupts. These are fully specified, and set in the 219 * interrupts property, so add that value to the device's 220 * resource list. 221 */ 222 if (dinfo->opd_dinfo.cfg.intpin == 0) 223 ofw_bus_intr_to_rl(dev, child, 224 &dinfo->opd_dinfo.resources, NULL); 225 } 226 } 227 228 /* 229 * The following is an almost exact clone of pci_add_children(), with the 230 * addition that it (a) will not add children that have already been added, 231 * and (b) will set up the OFW devinfo to point to invalid values. This is 232 * to handle non-enumerated PCI children as exist in FDT and on the second 233 * function of the Rage 128 in my Blue & White G3. 234 */ 235 236 static void 237 ofw_pcibus_enum_bus(device_t dev, u_int domain, u_int busno) 238 { 239 device_t pcib; 240 struct ofw_pcibus_devinfo *dinfo; 241 int maxslots; 242 int s, f, pcifunchigh; 243 uint8_t hdrtype; 244 245 pcib = device_get_parent(dev); 246 247 maxslots = PCIB_MAXSLOTS(pcib); 248 for (s = 0; s <= maxslots; s++) { 249 pcifunchigh = 0; 250 f = 0; 251 DELAY(1); 252 hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1); 253 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 254 continue; 255 if (hdrtype & PCIM_MFDEV) 256 pcifunchigh = PCI_FUNCMAX; 257 for (f = 0; f <= pcifunchigh; f++) { 258 /* Filter devices we have already added */ 259 if (pci_find_dbsf(domain, busno, s, f) != NULL) 260 continue; 261 262 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device( 263 pcib, dev, domain, busno, s, f); 264 if (dinfo == NULL) 265 continue; 266 267 dinfo->opd_dma_tag = NULL; 268 dinfo->opd_obdinfo.obd_node = -1; 269 270 dinfo->opd_obdinfo.obd_name = NULL; 271 dinfo->opd_obdinfo.obd_compat = NULL; 272 dinfo->opd_obdinfo.obd_type = NULL; 273 dinfo->opd_obdinfo.obd_model = NULL; 274 275 /* 276 * For non OFW-devices, don't believe 0 277 * for an interrupt. 278 */ 279 if (dinfo->opd_dinfo.cfg.intline == 0) { 280 dinfo->opd_dinfo.cfg.intline = PCI_INVALID_IRQ; 281 PCIB_WRITE_CONFIG(pcib, busno, s, f, 282 PCIR_INTLINE, PCI_INVALID_IRQ, 1); 283 } 284 285 pci_add_child(dev, (struct pci_devinfo *)dinfo); 286 } 287 } 288 } 289 290 static void 291 ofw_pcibus_child_deleted(device_t dev, device_t child) 292 { 293 struct ofw_pcibus_devinfo *dinfo; 294 295 dinfo = device_get_ivars(child); 296 ofw_bus_gen_destroy_devinfo(&dinfo->opd_obdinfo); 297 pci_child_deleted(dev, child); 298 } 299 300 static int 301 ofw_pcibus_child_pnpinfo_method(device_t cbdev, device_t child, struct sbuf *sb) 302 { 303 pci_child_pnpinfo_method(cbdev, child, sb); 304 305 if (ofw_bus_get_node(child) != -1) { 306 sbuf_cat(sb, " "); /* Separate info */ 307 ofw_bus_gen_child_pnpinfo(cbdev, child, sb); 308 } 309 310 return (0); 311 } 312 313 static int 314 ofw_pcibus_assign_interrupt(device_t dev, device_t child) 315 { 316 ofw_pci_intr_t intr[2]; 317 phandle_t node, iparent; 318 int isz, icells; 319 320 node = ofw_bus_get_node(child); 321 322 if (node == -1) { 323 /* Non-firmware enumerated child, use standard routing */ 324 325 intr[0] = pci_get_intpin(child); 326 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 327 intr[0])); 328 } 329 330 /* 331 * Try to determine the node's interrupt parent so we know which 332 * PIC to use. 333 */ 334 335 iparent = -1; 336 if (OF_getencprop(node, "interrupt-parent", &iparent, 337 sizeof(iparent)) < 0) 338 iparent = -1; 339 icells = 1; 340 if (iparent != -1) 341 OF_getencprop(OF_node_from_xref(iparent), "#interrupt-cells", 342 &icells, sizeof(icells)); 343 344 /* 345 * Any AAPL,interrupts property gets priority and is 346 * fully specified (i.e. does not need routing) 347 */ 348 349 isz = OF_getencprop(node, "AAPL,interrupts", intr, sizeof(intr)); 350 if (isz == sizeof(intr[0])*icells) 351 return ((iparent == -1) ? intr[0] : ofw_bus_map_intr(dev, 352 iparent, icells, intr)); 353 354 isz = OF_getencprop(node, "interrupts", intr, sizeof(intr)); 355 if (isz == sizeof(intr[0])*icells) { 356 if (iparent != -1) 357 intr[0] = ofw_bus_map_intr(dev, iparent, icells, intr); 358 } else { 359 /* No property: our best guess is the intpin. */ 360 intr[0] = pci_get_intpin(child); 361 } 362 363 /* 364 * If we got intr from a property, it may or may not be an intpin. 365 * For on-board devices, it frequently is not, and is completely out 366 * of the valid intpin range. For PCI slots, it hopefully is, 367 * otherwise we will have trouble interfacing with non-OFW buses 368 * such as cardbus. 369 * Since we cannot tell which it is without violating layering, we 370 * will always use the route_interrupt method, and treat exceptions 371 * on the level they become apparent. 372 */ 373 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr[0])); 374 } 375 376 static const struct ofw_bus_devinfo * 377 ofw_pcibus_get_devinfo(device_t bus, device_t dev) 378 { 379 struct ofw_pcibus_devinfo *dinfo; 380 381 dinfo = device_get_ivars(dev); 382 return (&dinfo->opd_obdinfo); 383 } 384 385 int 386 ofw_pcibus_get_cpus(device_t dev, device_t child, enum cpu_sets op, size_t setsize, 387 cpuset_t *cpuset) 388 { 389 int d, error; 390 391 d = platform_node_numa_domain(ofw_bus_get_node(dev)); 392 393 switch (op) { 394 case LOCAL_CPUS: 395 if (setsize != sizeof(cpuset_t)) 396 return (EINVAL); 397 *cpuset = cpuset_domain[d]; 398 return (0); 399 case INTR_CPUS: 400 error = bus_generic_get_cpus(dev, child, op, setsize, cpuset); 401 if (error != 0) 402 return (error); 403 if (setsize != sizeof(cpuset_t)) 404 return (EINVAL); 405 CPU_AND(cpuset, cpuset, &cpuset_domain[d]); 406 return (0); 407 default: 408 return (bus_generic_get_cpus(dev, child, op, setsize, cpuset)); 409 } 410 return (0); 411 } 412 413 /* 414 * Fetch the NUMA domain for the given device 'dev'. 415 * 416 * If a device has a _PXM method, map that to a NUMA domain. 417 * Otherwise, pass the request up to the parent. 418 * If there's no matching domain or the domain cannot be 419 * determined, return ENOENT. 420 */ 421 int 422 ofw_pcibus_get_domain(device_t dev, device_t child, int *domain) 423 { 424 *domain = platform_node_numa_domain(ofw_bus_get_node(child)); 425 426 return (0); 427 } 428