1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_platform.h" 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/pcpu.h> 38 #include <sys/proc.h> 39 #include <sys/smp.h> 40 41 #include <machine/bus.h> 42 #include <machine/cpu.h> 43 #include <machine/hid.h> 44 #include <machine/_inttypes.h> 45 #include <machine/machdep.h> 46 #include <machine/md_var.h> 47 #include <machine/platform.h> 48 #include <machine/platformvar.h> 49 #include <machine/smp.h> 50 #include <machine/spr.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/fdt/fdt_common.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/openfirm.h> 57 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 #include <vm/vm_extern.h> 61 62 #include <powerpc/mpc85xx/mpc85xx.h> 63 64 #include "platform_if.h" 65 66 #ifdef SMP 67 extern void *ap_pcpu; 68 extern vm_paddr_t kernload; /* Kernel physical load address */ 69 extern uint8_t __boot_page[]; /* Boot page body */ 70 extern uint32_t bp_kernload; 71 72 struct cpu_release { 73 uint32_t entry_h; 74 uint32_t entry_l; 75 uint32_t r3_h; 76 uint32_t r3_l; 77 uint32_t reserved; 78 uint32_t pir; 79 }; 80 #endif 81 82 extern uint32_t *bootinfo; 83 vm_paddr_t ccsrbar_pa; 84 vm_offset_t ccsrbar_va; 85 vm_size_t ccsrbar_size; 86 87 static int cpu, maxcpu; 88 89 static int mpc85xx_probe(platform_t); 90 static void mpc85xx_mem_regions(platform_t, struct mem_region *phys, 91 int *physsz, struct mem_region *avail, int *availsz); 92 static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref); 93 static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref); 94 static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref); 95 static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref); 96 static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu); 97 static void mpc85xx_smp_timebase_sync(platform_t, u_long tb, int ap); 98 99 static void mpc85xx_reset(platform_t); 100 101 static platform_method_t mpc85xx_methods[] = { 102 PLATFORMMETHOD(platform_probe, mpc85xx_probe), 103 PLATFORMMETHOD(platform_attach, mpc85xx_attach), 104 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions), 105 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq), 106 107 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu), 108 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu), 109 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp), 110 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu), 111 PLATFORMMETHOD(platform_smp_timebase_sync, mpc85xx_smp_timebase_sync), 112 113 PLATFORMMETHOD(platform_reset, mpc85xx_reset), 114 115 PLATFORMMETHOD_END 116 }; 117 118 DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0); 119 120 PLATFORM_DEF(mpc85xx_platform); 121 122 static int 123 mpc85xx_probe(platform_t plat) 124 { 125 u_int pvr = (mfpvr() >> 16) & 0xFFFF; 126 127 switch (pvr) { 128 case FSL_E500v1: 129 case FSL_E500v2: 130 case FSL_E500mc: 131 case FSL_E5500: 132 case FSL_E6500: 133 return (BUS_PROBE_DEFAULT); 134 } 135 return (ENXIO); 136 } 137 138 int 139 mpc85xx_attach(platform_t plat) 140 { 141 phandle_t cpus, child, ccsr; 142 const char *soc_name_guesses[] = {"/soc", "soc", NULL}; 143 const char **name; 144 pcell_t ranges[6], acells, pacells, scells; 145 uint64_t ccsrbar, ccsrsize; 146 int i; 147 148 if ((cpus = OF_finddevice("/cpus")) != -1) { 149 for (maxcpu = 0, child = OF_child(cpus); child != 0; 150 child = OF_peer(child), maxcpu++) 151 ; 152 } else 153 maxcpu = 1; 154 155 /* 156 * Locate CCSR region. Irritatingly, there is no way to find it 157 * unless you already know where it is. Try to infer its location 158 * from the device tree. 159 */ 160 161 ccsr = -1; 162 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++) 163 ccsr = OF_finddevice(*name); 164 if (ccsr == -1) { 165 char type[64]; 166 167 /* That didn't work. Search for devices of type "soc" */ 168 child = OF_child(OF_peer(0)); 169 for (OF_child(child); child != 0; child = OF_peer(child)) { 170 if (OF_getprop(child, "device_type", type, sizeof(type)) 171 <= 0) 172 continue; 173 174 if (strcmp(type, "soc") == 0) { 175 ccsr = child; 176 break; 177 } 178 } 179 } 180 181 if (ccsr == -1) 182 panic("Could not locate CCSR window!"); 183 184 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells)); 185 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells)); 186 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells, 187 sizeof(pacells)); 188 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges)); 189 ccsrbar = ccsrsize = 0; 190 for (i = acells; i < acells + pacells; i++) { 191 ccsrbar <<= 32; 192 ccsrbar |= ranges[i]; 193 } 194 for (i = acells + pacells; i < acells + pacells + scells; i++) { 195 ccsrsize <<= 32; 196 ccsrsize |= ranges[i]; 197 } 198 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize); 199 ccsrbar_pa = ccsrbar; 200 ccsrbar_size = ccsrsize; 201 202 mpc85xx_enable_l3_cache(); 203 204 return (0); 205 } 206 207 void 208 mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz, 209 struct mem_region *avail, int *availsz) 210 { 211 212 ofw_mem_regions(phys, physsz, avail, availsz); 213 } 214 215 static u_long 216 mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref) 217 { 218 u_long ticks; 219 phandle_t cpus, child; 220 pcell_t freq; 221 222 if (bootinfo != NULL) { 223 if (bootinfo[0] == 1) { 224 /* Backward compatibility. See 8-STABLE. */ 225 ticks = bootinfo[3] >> 3; 226 } else { 227 /* Compatibility with Juniper's loader. */ 228 ticks = bootinfo[5] >> 3; 229 } 230 } else 231 ticks = 0; 232 233 if ((cpus = OF_finddevice("/cpus")) == -1) 234 goto out; 235 236 if ((child = OF_child(cpus)) == 0) 237 goto out; 238 239 switch (OF_getproplen(child, "timebase-frequency")) { 240 case 4: 241 { 242 uint32_t tbase; 243 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); 244 ticks = tbase; 245 return (ticks); 246 } 247 case 8: 248 { 249 uint64_t tbase; 250 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); 251 ticks = tbase; 252 return (ticks); 253 } 254 default: 255 break; 256 } 257 258 freq = 0; 259 if (OF_getprop(child, "bus-frequency", (void *)&freq, 260 sizeof(freq)) <= 0) 261 goto out; 262 263 if (freq == 0) 264 goto out; 265 266 /* 267 * Time Base and Decrementer are updated every 8 CCB bus clocks. 268 * HID0[SEL_TBCLK] = 0 269 */ 270 if (mpc85xx_is_qoriq()) 271 ticks = freq / 32; 272 else 273 ticks = freq / 8; 274 275 out: 276 if (ticks <= 0) 277 panic("Unable to determine timebase frequency!"); 278 279 return (ticks); 280 } 281 282 static int 283 mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 284 { 285 286 cpu = 0; 287 cpuref->cr_cpuid = cpu; 288 cpuref->cr_hwref = cpuref->cr_cpuid; 289 if (bootverbose) 290 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 291 cpu++; 292 293 return (0); 294 } 295 296 static int 297 mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 298 { 299 300 if (cpu >= maxcpu) 301 return (ENOENT); 302 303 cpuref->cr_cpuid = cpu++; 304 cpuref->cr_hwref = cpuref->cr_cpuid; 305 if (bootverbose) 306 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 307 308 return (0); 309 } 310 311 static int 312 mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 313 { 314 315 cpuref->cr_cpuid = mfspr(SPR_PIR); 316 cpuref->cr_hwref = cpuref->cr_cpuid; 317 318 return (0); 319 } 320 321 #ifdef SMP 322 static int 323 mpc85xx_smp_start_cpu_epapr(platform_t plat, struct pcpu *pc) 324 { 325 vm_paddr_t rel_pa, bptr; 326 volatile struct cpu_release *rel; 327 vm_offset_t rel_va, rel_page; 328 phandle_t node; 329 int i; 330 331 /* If we're calling this, the node already exists. */ 332 node = OF_finddevice("/cpus"); 333 for (i = 0, node = OF_child(node); i < pc->pc_cpuid; 334 i++, node = OF_peer(node)) 335 ; 336 if (OF_getencprop(node, "cpu-release-addr", (pcell_t *)&rel_pa, 337 sizeof(rel_pa)) == -1) { 338 return (ENOENT); 339 } 340 341 rel_page = kva_alloc(PAGE_SIZE); 342 if (rel_page == 0) 343 return (ENOMEM); 344 345 critical_enter(); 346 rel_va = rel_page + (rel_pa & PAGE_MASK); 347 pmap_kenter(rel_page, rel_pa & ~PAGE_MASK); 348 rel = (struct cpu_release *)rel_va; 349 bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload; 350 cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel)); 351 rel->pir = pc->pc_cpuid; __asm __volatile("sync"); 352 rel->entry_h = (bptr >> 32); 353 rel->entry_l = bptr; __asm __volatile("sync"); 354 cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel)); 355 if (bootverbose) 356 printf("Waking up CPU %d via CPU release page %p\n", 357 pc->pc_cpuid, rel); 358 critical_exit(); 359 pmap_kremove(rel_page); 360 kva_free(rel_page, PAGE_SIZE); 361 362 return (0); 363 } 364 #endif 365 366 static int 367 mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc) 368 { 369 #ifdef SMP 370 vm_paddr_t bptr; 371 uint32_t reg; 372 int timeout; 373 uintptr_t brr; 374 int cpuid; 375 int epapr_boot = 0; 376 uint32_t tgt; 377 378 if (mpc85xx_is_qoriq()) { 379 reg = ccsr_read4(OCP85XX_COREDISR); 380 cpuid = pc->pc_cpuid; 381 382 if ((reg & (1 << cpuid)) != 0) { 383 printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid); 384 return (-1); 385 } 386 387 brr = OCP85XX_BRR; 388 } else { 389 brr = OCP85XX_EEBPCR; 390 cpuid = pc->pc_cpuid + 24; 391 } 392 bp_kernload = kernload; 393 /* 394 * bp_kernload is in the boot page. Sync the cache because ePAPR 395 * booting has the other core(s) already running. 396 */ 397 cpu_flush_dcache(&bp_kernload, sizeof(bp_kernload)); 398 399 ap_pcpu = pc; 400 __asm __volatile("msync; isync"); 401 402 /* First try the ePAPR way. */ 403 if (mpc85xx_smp_start_cpu_epapr(plat, pc) == 0) { 404 epapr_boot = 1; 405 goto spin_wait; 406 } 407 408 reg = ccsr_read4(brr); 409 if ((reg & (1 << cpuid)) != 0) { 410 printf("SMP: CPU %d already out of hold-off state!\n", 411 pc->pc_cpuid); 412 return (ENXIO); 413 } 414 415 /* Flush caches to have our changes hit DRAM. */ 416 cpu_flush_dcache(__boot_page, 4096); 417 418 bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload; 419 KASSERT((bptr & 0xfff) == 0, 420 ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr)); 421 if (mpc85xx_is_qoriq()) { 422 /* 423 * Read DDR controller configuration to select proper BPTR target ID. 424 * 425 * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers 426 * interleaving. If this bit is set, we have to use 427 * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs, 428 * this bit is reserved and always 0. 429 */ 430 431 reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG); 432 if (reg & (1 << 29)) 433 tgt = OCP85XX_TGTIF_RAM_INTL; 434 else 435 tgt = OCP85XX_TGTIF_RAM1; 436 437 /* 438 * Set BSTR to the physical address of the boot page 439 */ 440 ccsr_write4(OCP85XX_BSTRH, bptr >> 32); 441 ccsr_write4(OCP85XX_BSTRL, bptr); 442 ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK | 443 (tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2)); 444 445 /* Read back OCP85XX_BSTAR to synchronize write */ 446 ccsr_read4(OCP85XX_BSTAR); 447 448 /* 449 * Enable and configure time base on new CPU. 450 */ 451 452 /* Set TB clock source to platform clock / 32 */ 453 reg = ccsr_read4(CCSR_CTBCKSELR); 454 ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid)); 455 456 /* Enable TB */ 457 reg = ccsr_read4(CCSR_CTBENR); 458 ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid)); 459 } else { 460 /* 461 * Set BPTR to the physical address of the boot page 462 */ 463 bptr = (bptr >> 12) | 0x80000000u; 464 ccsr_write4(OCP85XX_BPTR, bptr); 465 __asm __volatile("isync; msync"); 466 } 467 468 /* 469 * Release AP from hold-off state 470 */ 471 reg = ccsr_read4(brr); 472 ccsr_write4(brr, reg | (1 << cpuid)); 473 __asm __volatile("isync; msync"); 474 475 spin_wait: 476 timeout = 500; 477 while (!pc->pc_awake && timeout--) 478 DELAY(1000); /* wait 1ms */ 479 480 /* 481 * Disable boot page translation so that the 4K page at the default 482 * address (= 0xfffff000) isn't permanently remapped and thus not 483 * usable otherwise. 484 */ 485 if (!epapr_boot) { 486 if (mpc85xx_is_qoriq()) 487 ccsr_write4(OCP85XX_BSTAR, 0); 488 else 489 ccsr_write4(OCP85XX_BPTR, 0); 490 __asm __volatile("isync; msync"); 491 } 492 493 if (!pc->pc_awake) 494 panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid); 495 return ((pc->pc_awake) ? 0 : EBUSY); 496 #else 497 /* No SMP support */ 498 return (ENXIO); 499 #endif 500 } 501 502 static void 503 mpc85xx_reset(platform_t plat) 504 { 505 506 /* 507 * Try the dedicated reset register first. 508 * If the SoC doesn't have one, we'll fall 509 * back to using the debug control register. 510 */ 511 ccsr_write4(OCP85XX_RSTCR, 2); 512 513 /* Clear DBCR0, disables debug interrupts and events. */ 514 mtspr(SPR_DBCR0, 0); 515 __asm __volatile("isync"); 516 517 /* Enable Debug Interrupts in MSR. */ 518 mtmsr(mfmsr() | PSL_DE); 519 520 /* Enable debug interrupts and issue reset. */ 521 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 522 523 printf("Reset failed...\n"); 524 while (1) 525 ; 526 } 527 528 static void 529 mpc85xx_smp_timebase_sync(platform_t plat, u_long tb, int ap) 530 { 531 532 mttb(tb); 533 } 534 535