1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_platform.h" 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/pcpu.h> 38 #include <sys/proc.h> 39 #include <sys/smp.h> 40 41 #include <machine/bus.h> 42 #include <machine/cpu.h> 43 #include <machine/hid.h> 44 #include <machine/_inttypes.h> 45 #include <machine/machdep.h> 46 #include <machine/md_var.h> 47 #include <machine/platform.h> 48 #include <machine/platformvar.h> 49 #include <machine/smp.h> 50 #include <machine/spr.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/fdt/fdt_common.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/openfirm.h> 57 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 #include <vm/vm_extern.h> 61 62 #include <powerpc/mpc85xx/mpc85xx.h> 63 64 #include "platform_if.h" 65 66 #ifdef SMP 67 extern void *ap_pcpu; 68 extern vm_paddr_t kernload; /* Kernel physical load address */ 69 extern uint8_t __boot_page[]; /* Boot page body */ 70 extern uint32_t bp_kernload; 71 extern vm_offset_t __startkernel; 72 73 struct cpu_release { 74 uint32_t entry_h; 75 uint32_t entry_l; 76 uint32_t r3_h; 77 uint32_t r3_l; 78 uint32_t reserved; 79 uint32_t pir; 80 }; 81 #endif 82 83 extern uint32_t *bootinfo; 84 vm_paddr_t ccsrbar_pa; 85 vm_offset_t ccsrbar_va; 86 vm_size_t ccsrbar_size; 87 88 static int cpu, maxcpu; 89 90 static int mpc85xx_probe(platform_t); 91 static void mpc85xx_mem_regions(platform_t, struct mem_region *phys, 92 int *physsz, struct mem_region *avail, int *availsz); 93 static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref); 94 static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref); 95 static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref); 96 static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref); 97 static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu); 98 static void mpc85xx_smp_timebase_sync(platform_t, u_long tb, int ap); 99 100 static void mpc85xx_reset(platform_t); 101 102 static platform_method_t mpc85xx_methods[] = { 103 PLATFORMMETHOD(platform_probe, mpc85xx_probe), 104 PLATFORMMETHOD(platform_attach, mpc85xx_attach), 105 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions), 106 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq), 107 108 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu), 109 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu), 110 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp), 111 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu), 112 PLATFORMMETHOD(platform_smp_timebase_sync, mpc85xx_smp_timebase_sync), 113 114 PLATFORMMETHOD(platform_reset, mpc85xx_reset), 115 116 PLATFORMMETHOD_END 117 }; 118 119 DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0); 120 121 PLATFORM_DEF(mpc85xx_platform); 122 123 static int 124 mpc85xx_probe(platform_t plat) 125 { 126 u_int pvr = (mfpvr() >> 16) & 0xFFFF; 127 128 switch (pvr) { 129 case FSL_E500v1: 130 case FSL_E500v2: 131 case FSL_E500mc: 132 case FSL_E5500: 133 case FSL_E6500: 134 return (BUS_PROBE_DEFAULT); 135 } 136 return (ENXIO); 137 } 138 139 int 140 mpc85xx_attach(platform_t plat) 141 { 142 phandle_t cpus, child, ccsr; 143 const char *soc_name_guesses[] = {"/soc", "soc", NULL}; 144 const char **name; 145 pcell_t ranges[6], acells, pacells, scells; 146 uint64_t ccsrbar, ccsrsize; 147 int i; 148 149 if ((cpus = OF_finddevice("/cpus")) != -1) { 150 for (maxcpu = 0, child = OF_child(cpus); child != 0; 151 child = OF_peer(child), maxcpu++) 152 ; 153 } else 154 maxcpu = 1; 155 156 /* 157 * Locate CCSR region. Irritatingly, there is no way to find it 158 * unless you already know where it is. Try to infer its location 159 * from the device tree. 160 */ 161 162 ccsr = -1; 163 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++) 164 ccsr = OF_finddevice(*name); 165 if (ccsr == -1) { 166 char type[64]; 167 168 /* That didn't work. Search for devices of type "soc" */ 169 child = OF_child(OF_peer(0)); 170 for (OF_child(child); child != 0; child = OF_peer(child)) { 171 if (OF_getprop(child, "device_type", type, sizeof(type)) 172 <= 0) 173 continue; 174 175 if (strcmp(type, "soc") == 0) { 176 ccsr = child; 177 break; 178 } 179 } 180 } 181 182 if (ccsr == -1) 183 panic("Could not locate CCSR window!"); 184 185 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells)); 186 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells)); 187 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells, 188 sizeof(pacells)); 189 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges)); 190 ccsrbar = ccsrsize = 0; 191 for (i = acells; i < acells + pacells; i++) { 192 ccsrbar <<= 32; 193 ccsrbar |= ranges[i]; 194 } 195 for (i = acells + pacells; i < acells + pacells + scells; i++) { 196 ccsrsize <<= 32; 197 ccsrsize |= ranges[i]; 198 } 199 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize); 200 ccsrbar_pa = ccsrbar; 201 ccsrbar_size = ccsrsize; 202 203 mpc85xx_enable_l3_cache(); 204 205 return (0); 206 } 207 208 void 209 mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz, 210 struct mem_region *avail, int *availsz) 211 { 212 213 ofw_mem_regions(phys, physsz, avail, availsz); 214 } 215 216 static u_long 217 mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref) 218 { 219 u_long ticks; 220 phandle_t cpus, child; 221 pcell_t freq; 222 223 if (bootinfo != NULL) { 224 if (bootinfo[0] == 1) { 225 /* Backward compatibility. See 8-STABLE. */ 226 ticks = bootinfo[3] >> 3; 227 } else { 228 /* Compatibility with Juniper's loader. */ 229 ticks = bootinfo[5] >> 3; 230 } 231 } else 232 ticks = 0; 233 234 if ((cpus = OF_finddevice("/cpus")) == -1) 235 goto out; 236 237 if ((child = OF_child(cpus)) == 0) 238 goto out; 239 240 switch (OF_getproplen(child, "timebase-frequency")) { 241 case 4: 242 { 243 uint32_t tbase; 244 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); 245 ticks = tbase; 246 return (ticks); 247 } 248 case 8: 249 { 250 uint64_t tbase; 251 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); 252 ticks = tbase; 253 return (ticks); 254 } 255 default: 256 break; 257 } 258 259 freq = 0; 260 if (OF_getprop(child, "bus-frequency", (void *)&freq, 261 sizeof(freq)) <= 0) 262 goto out; 263 264 if (freq == 0) 265 goto out; 266 267 /* 268 * Time Base and Decrementer are updated every 8 CCB bus clocks. 269 * HID0[SEL_TBCLK] = 0 270 */ 271 if (mpc85xx_is_qoriq()) 272 ticks = freq / 32; 273 else 274 ticks = freq / 8; 275 276 out: 277 if (ticks <= 0) 278 panic("Unable to determine timebase frequency!"); 279 280 return (ticks); 281 } 282 283 static int 284 mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 285 { 286 287 cpu = 0; 288 cpuref->cr_cpuid = cpu; 289 cpuref->cr_hwref = cpuref->cr_cpuid; 290 if (bootverbose) 291 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 292 cpu++; 293 294 return (0); 295 } 296 297 static int 298 mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 299 { 300 301 if (cpu >= maxcpu) 302 return (ENOENT); 303 304 cpuref->cr_cpuid = cpu++; 305 cpuref->cr_hwref = cpuref->cr_cpuid; 306 if (bootverbose) 307 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 308 309 return (0); 310 } 311 312 static int 313 mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 314 { 315 316 cpuref->cr_cpuid = mfspr(SPR_PIR); 317 cpuref->cr_hwref = cpuref->cr_cpuid; 318 319 return (0); 320 } 321 322 #ifdef SMP 323 static int 324 mpc85xx_smp_start_cpu_epapr(platform_t plat, struct pcpu *pc) 325 { 326 vm_paddr_t rel_pa, bptr; 327 volatile struct cpu_release *rel; 328 vm_offset_t rel_va, rel_page; 329 phandle_t node; 330 int i; 331 332 /* If we're calling this, the node already exists. */ 333 node = OF_finddevice("/cpus"); 334 for (i = 0, node = OF_child(node); i < pc->pc_cpuid; 335 i++, node = OF_peer(node)) 336 ; 337 if (OF_getencprop(node, "cpu-release-addr", (pcell_t *)&rel_pa, 338 sizeof(rel_pa)) == -1) { 339 return (ENOENT); 340 } 341 342 rel_page = kva_alloc(PAGE_SIZE); 343 if (rel_page == 0) 344 return (ENOMEM); 345 346 critical_enter(); 347 rel_va = rel_page + (rel_pa & PAGE_MASK); 348 pmap_kenter(rel_page, rel_pa & ~PAGE_MASK); 349 rel = (struct cpu_release *)rel_va; 350 bptr = pmap_kextract((uintptr_t)__boot_page); 351 cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel)); 352 rel->pir = pc->pc_cpuid; __asm __volatile("sync"); 353 rel->entry_h = (bptr >> 32); 354 rel->entry_l = bptr; __asm __volatile("sync"); 355 cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel)); 356 if (bootverbose) 357 printf("Waking up CPU %d via CPU release page %p\n", 358 pc->pc_cpuid, rel); 359 critical_exit(); 360 pmap_kremove(rel_page); 361 kva_free(rel_page, PAGE_SIZE); 362 363 return (0); 364 } 365 #endif 366 367 static int 368 mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc) 369 { 370 #ifdef SMP 371 vm_paddr_t bptr; 372 uint32_t reg; 373 int timeout; 374 uintptr_t brr; 375 int cpuid; 376 int epapr_boot = 0; 377 uint32_t tgt; 378 379 if (mpc85xx_is_qoriq()) { 380 reg = ccsr_read4(OCP85XX_COREDISR); 381 cpuid = pc->pc_cpuid; 382 383 if ((reg & (1 << cpuid)) != 0) { 384 printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid); 385 return (-1); 386 } 387 388 brr = OCP85XX_BRR; 389 } else { 390 brr = OCP85XX_EEBPCR; 391 cpuid = pc->pc_cpuid + 24; 392 } 393 bp_kernload = kernload; 394 /* 395 * bp_kernload is in the boot page. Sync the cache because ePAPR 396 * booting has the other core(s) already running. 397 */ 398 cpu_flush_dcache(&bp_kernload, sizeof(bp_kernload)); 399 400 ap_pcpu = pc; 401 __asm __volatile("msync; isync"); 402 403 /* First try the ePAPR way. */ 404 if (mpc85xx_smp_start_cpu_epapr(plat, pc) == 0) { 405 epapr_boot = 1; 406 goto spin_wait; 407 } 408 409 reg = ccsr_read4(brr); 410 if ((reg & (1 << cpuid)) != 0) { 411 printf("SMP: CPU %d already out of hold-off state!\n", 412 pc->pc_cpuid); 413 return (ENXIO); 414 } 415 416 /* Flush caches to have our changes hit DRAM. */ 417 cpu_flush_dcache(__boot_page, 4096); 418 419 bptr = pmap_kextract((uintptr_t)__boot_page); 420 KASSERT((bptr & 0xfff) == 0, 421 ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr)); 422 if (mpc85xx_is_qoriq()) { 423 /* 424 * Read DDR controller configuration to select proper BPTR target ID. 425 * 426 * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers 427 * interleaving. If this bit is set, we have to use 428 * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs, 429 * this bit is reserved and always 0. 430 */ 431 432 reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG); 433 if (reg & (1 << 29)) 434 tgt = OCP85XX_TGTIF_RAM_INTL; 435 else 436 tgt = OCP85XX_TGTIF_RAM1; 437 438 /* 439 * Set BSTR to the physical address of the boot page 440 */ 441 ccsr_write4(OCP85XX_BSTRH, bptr >> 32); 442 ccsr_write4(OCP85XX_BSTRL, bptr); 443 ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK | 444 (tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2)); 445 446 /* Read back OCP85XX_BSTAR to synchronize write */ 447 ccsr_read4(OCP85XX_BSTAR); 448 449 /* 450 * Enable and configure time base on new CPU. 451 */ 452 453 /* Set TB clock source to platform clock / 32 */ 454 reg = ccsr_read4(CCSR_CTBCKSELR); 455 ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid)); 456 457 /* Enable TB */ 458 reg = ccsr_read4(CCSR_CTBENR); 459 ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid)); 460 } else { 461 /* 462 * Set BPTR to the physical address of the boot page 463 */ 464 bptr = (bptr >> 12) | 0x80000000u; 465 ccsr_write4(OCP85XX_BPTR, bptr); 466 __asm __volatile("isync; msync"); 467 } 468 469 /* 470 * Release AP from hold-off state 471 */ 472 reg = ccsr_read4(brr); 473 ccsr_write4(brr, reg | (1 << cpuid)); 474 __asm __volatile("isync; msync"); 475 476 spin_wait: 477 timeout = 500; 478 while (!pc->pc_awake && timeout--) 479 DELAY(1000); /* wait 1ms */ 480 481 /* 482 * Disable boot page translation so that the 4K page at the default 483 * address (= 0xfffff000) isn't permanently remapped and thus not 484 * usable otherwise. 485 */ 486 if (!epapr_boot) { 487 if (mpc85xx_is_qoriq()) 488 ccsr_write4(OCP85XX_BSTAR, 0); 489 else 490 ccsr_write4(OCP85XX_BPTR, 0); 491 __asm __volatile("isync; msync"); 492 } 493 494 if (!pc->pc_awake) 495 panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid); 496 return ((pc->pc_awake) ? 0 : EBUSY); 497 #else 498 /* No SMP support */ 499 return (ENXIO); 500 #endif 501 } 502 503 static void 504 mpc85xx_reset(platform_t plat) 505 { 506 507 /* 508 * Try the dedicated reset register first. 509 * If the SoC doesn't have one, we'll fall 510 * back to using the debug control register. 511 */ 512 ccsr_write4(OCP85XX_RSTCR, 2); 513 514 /* Clear DBCR0, disables debug interrupts and events. */ 515 mtspr(SPR_DBCR0, 0); 516 __asm __volatile("isync"); 517 518 /* Enable Debug Interrupts in MSR. */ 519 mtmsr(mfmsr() | PSL_DE); 520 521 /* Enable debug interrupts and issue reset. */ 522 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 523 524 printf("Reset failed...\n"); 525 while (1) 526 ; 527 } 528 529 static void 530 mpc85xx_smp_timebase_sync(platform_t plat, u_long tb, int ap) 531 { 532 533 mttb(tb); 534 } 535 536