xref: /freebsd/sys/powerpc/mpc85xx/pci_mpc85xx.c (revision f18d3c411697ff46d85e579a72be54ca0cc67dd0)
1 /*-
2  * Copyright 2006-2007 by Juniper Networks.
3  * Copyright 2008 Semihalf.
4  * Copyright 2010 The FreeBSD Foundation
5  * All rights reserved.
6  *
7  * Portions of this software were developed by Semihalf
8  * under sponsorship from the FreeBSD Foundation.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  *
33  * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
34  */
35 
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38 
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/ktr.h>
42 #include <sys/sockio.h>
43 #include <sys/mbuf.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
49 #include <sys/bus.h>
50 #include <sys/lock.h>
51 #include <sys/mutex.h>
52 #include <sys/rman.h>
53 #include <sys/endian.h>
54 
55 #include <vm/vm.h>
56 #include <vm/pmap.h>
57 
58 #include <dev/ofw/ofw_pci.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcib_private.h>
64 
65 #include <powerpc/ofw/ofw_pci.h>
66 
67 #include "ofw_bus_if.h"
68 #include "pcib_if.h"
69 
70 #include <machine/resource.h>
71 #include <machine/bus.h>
72 #include <machine/intr_machdep.h>
73 
74 #include <powerpc/mpc85xx/mpc85xx.h>
75 
76 #define	REG_CFG_ADDR	0x0000
77 #define	CONFIG_ACCESS_ENABLE	0x80000000
78 
79 #define	REG_CFG_DATA	0x0004
80 #define	REG_INT_ACK	0x0008
81 
82 #define	REG_POTAR(n)	(0x0c00 + 0x20 * (n))
83 #define	REG_POTEAR(n)	(0x0c04 + 0x20 * (n))
84 #define	REG_POWBAR(n)	(0x0c08 + 0x20 * (n))
85 #define	REG_POWAR(n)	(0x0c10 + 0x20 * (n))
86 
87 #define	REG_PITAR(n)	(0x0e00 - 0x20 * (n))
88 #define	REG_PIWBAR(n)	(0x0e08 - 0x20 * (n))
89 #define	REG_PIWBEAR(n)	(0x0e0c - 0x20 * (n))
90 #define	REG_PIWAR(n)	(0x0e10 - 0x20 * (n))
91 
92 #define	REG_PEX_MES_DR	0x0020
93 #define	REG_PEX_MES_IER	0x0028
94 #define	REG_PEX_ERR_DR	0x0e00
95 #define	REG_PEX_ERR_EN	0x0e08
96 
97 #define PCIR_LTSSM	0x404
98 #define LTSSM_STAT_L0	0x16
99 
100 #define	DEVFN(b, s, f)	((b << 16) | (s << 8) | f)
101 
102 struct fsl_pcib_softc {
103 	struct ofw_pci_softc pci_sc;
104 	device_t	sc_dev;
105 
106 	int		sc_iomem_target;
107 	bus_addr_t	sc_iomem_alloc, sc_iomem_start, sc_iomem_end;
108 	int		sc_ioport_target;
109 	bus_addr_t	sc_ioport_alloc, sc_ioport_start, sc_ioport_end;
110 
111 	struct resource *sc_res;
112 	bus_space_handle_t sc_bsh;
113 	bus_space_tag_t	sc_bst;
114 	int		sc_rid;
115 
116 	int		sc_busnr;
117 	int		sc_pcie;
118 	uint8_t		sc_pcie_capreg;		/* PCI-E Capability Reg Set */
119 
120 	/* Devices that need special attention. */
121 	int		sc_devfn_tundra;
122 	int		sc_devfn_via_ide;
123 };
124 
125 /* Local forward declerations. */
126 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
127     u_int, int);
128 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
129     u_int, uint32_t, int);
130 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
131 static void fsl_pcib_err_init(device_t);
132 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long,
133     u_long, u_long);
134 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
135 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long,
136     u_long, u_long);
137 
138 /* Forward declerations. */
139 static int fsl_pcib_attach(device_t);
140 static int fsl_pcib_detach(device_t);
141 static int fsl_pcib_probe(device_t);
142 
143 static int fsl_pcib_maxslots(device_t);
144 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
145 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
146     uint32_t, int);
147 
148 /* Configuration r/w mutex. */
149 struct mtx pcicfg_mtx;
150 static int mtx_initialized = 0;
151 
152 /*
153  * Bus interface definitions.
154  */
155 static device_method_t fsl_pcib_methods[] = {
156 	/* Device interface */
157 	DEVMETHOD(device_probe,		fsl_pcib_probe),
158 	DEVMETHOD(device_attach,	fsl_pcib_attach),
159 	DEVMETHOD(device_detach,	fsl_pcib_detach),
160 
161 	/* pcib interface */
162 	DEVMETHOD(pcib_maxslots,	fsl_pcib_maxslots),
163 	DEVMETHOD(pcib_read_config,	fsl_pcib_read_config),
164 	DEVMETHOD(pcib_write_config,	fsl_pcib_write_config),
165 
166 	DEVMETHOD_END
167 };
168 
169 static devclass_t fsl_pcib_devclass;
170 
171 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
172     sizeof(struct fsl_pcib_softc), ofw_pci_driver);
173 DRIVER_MODULE(pcib, nexus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0);
174 
175 static int
176 fsl_pcib_probe(device_t dev)
177 {
178 
179 	if (ofw_bus_get_type(dev) == NULL ||
180 	    strcmp(ofw_bus_get_type(dev), "pci") != 0)
181 		return (ENXIO);
182 
183 	if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
184 	    ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
185 	    ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie")))
186 		return (ENXIO);
187 
188 	device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
189 	return (BUS_PROBE_DEFAULT);
190 }
191 
192 static int
193 fsl_pcib_attach(device_t dev)
194 {
195 	struct fsl_pcib_softc *sc;
196 	phandle_t node;
197 	uint32_t cfgreg;
198 	int maxslot, error;
199 	uint8_t ltssm, capptr;
200 
201 	sc = device_get_softc(dev);
202 	sc->sc_dev = dev;
203 
204 	sc->sc_rid = 0;
205 	sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
206 	    RF_ACTIVE);
207 	if (sc->sc_res == NULL) {
208 		device_printf(dev, "could not map I/O memory\n");
209 		return (ENXIO);
210 	}
211 	sc->sc_bst = rman_get_bustag(sc->sc_res);
212 	sc->sc_bsh = rman_get_bushandle(sc->sc_res);
213 	sc->sc_busnr = 0;
214 
215 	if (!mtx_initialized) {
216 		mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
217 		mtx_initialized = 1;
218 	}
219 
220 	cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
221 	if (cfgreg != 0x1057 && cfgreg != 0x1957)
222 		goto err;
223 
224 	capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
225 	while (capptr != 0) {
226 		cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
227 		switch (cfgreg & 0xff) {
228 		case PCIY_PCIX:
229 			break;
230 		case PCIY_EXPRESS:
231 			sc->sc_pcie = 1;
232 			sc->sc_pcie_capreg = capptr;
233 			break;
234 		}
235 		capptr = (cfgreg >> 8) & 0xff;
236 	}
237 
238 	node = ofw_bus_get_node(dev);
239 
240 	/*
241 	 * Initialize generic OF PCI interface (ranges, etc.)
242 	 */
243 
244 	error = ofw_pci_init(dev);
245 	if (error)
246 		return (error);
247 
248 	/*
249 	 * Configure decode windows for PCI(E) access.
250 	 */
251 	if (fsl_pcib_decode_win(node, sc) != 0)
252 		goto err;
253 
254 	cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
255 	cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
256 	    PCIM_CMD_PORTEN;
257 	fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
258 
259 	sc->sc_devfn_tundra = -1;
260 	sc->sc_devfn_via_ide = -1;
261 
262 
263 	/*
264 	 * Scan bus using firmware configured, 0 based bus numbering.
265 	 */
266 	sc->sc_busnr = 0;
267 	maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
268 	fsl_pcib_init(sc, sc->sc_busnr, maxslot);
269 
270 	if (sc->sc_pcie) {
271 		ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
272 		if (ltssm < LTSSM_STAT_L0) {
273 			if (bootverbose)
274 				printf("PCI %d: no PCIE link, skipping\n",
275 				    device_get_unit(dev));
276 			return (0);
277 		}
278 	}
279 
280 	fsl_pcib_err_init(dev);
281 
282 	return (ofw_pci_attach(dev));
283 
284 err:
285 	return (ENXIO);
286 }
287 
288 static uint32_t
289 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
290     u_int reg, int bytes)
291 {
292 	uint32_t addr, data;
293 
294 	if (bus == sc->sc_busnr - 1)
295 		bus = 0;
296 
297 	addr = CONFIG_ACCESS_ENABLE;
298 	addr |= (bus & 0xff) << 16;
299 	addr |= (slot & 0x1f) << 11;
300 	addr |= (func & 0x7) << 8;
301 	addr |= reg & 0xfc;
302 	if (sc->sc_pcie)
303 		addr |= (reg & 0xf00) << 16;
304 
305 	mtx_lock_spin(&pcicfg_mtx);
306 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
307 
308 	switch (bytes) {
309 	case 1:
310 		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
311 		    REG_CFG_DATA + (reg & 3));
312 		break;
313 	case 2:
314 		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
315 		    REG_CFG_DATA + (reg & 2)));
316 		break;
317 	case 4:
318 		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
319 		    REG_CFG_DATA));
320 		break;
321 	default:
322 		data = ~0;
323 		break;
324 	}
325 	mtx_unlock_spin(&pcicfg_mtx);
326 	return (data);
327 }
328 
329 static void
330 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
331     u_int reg, uint32_t data, int bytes)
332 {
333 	uint32_t addr;
334 
335 	if (bus == sc->sc_busnr - 1)
336 		bus = 0;
337 
338 	addr = CONFIG_ACCESS_ENABLE;
339 	addr |= (bus & 0xff) << 16;
340 	addr |= (slot & 0x1f) << 11;
341 	addr |= (func & 0x7) << 8;
342 	addr |= reg & 0xfc;
343 	if (sc->sc_pcie)
344 		addr |= (reg & 0xf00) << 16;
345 
346 	mtx_lock_spin(&pcicfg_mtx);
347 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
348 
349 	switch (bytes) {
350 	case 1:
351 		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
352 		    REG_CFG_DATA + (reg & 3), data);
353 		break;
354 	case 2:
355 		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
356 		    REG_CFG_DATA + (reg & 2), htole16(data));
357 		break;
358 	case 4:
359 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
360 		    REG_CFG_DATA, htole32(data));
361 		break;
362 	}
363 	mtx_unlock_spin(&pcicfg_mtx);
364 }
365 
366 #if 0
367 static void
368 dump(struct fsl_pcib_softc *sc)
369 {
370 	unsigned int i;
371 
372 #define RD(o)	bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
373 	for (i = 0; i < 5; i++) {
374 		printf("POTAR%u  =0x%08x\n", i, RD(REG_POTAR(i)));
375 		printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
376 		printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
377 		printf("POWAR%u  =0x%08x\n", i, RD(REG_POWAR(i)));
378 	}
379 	printf("\n");
380 	for (i = 1; i < 4; i++) {
381 		printf("PITAR%u  =0x%08x\n", i, RD(REG_PITAR(i)));
382 		printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
383 		printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
384 		printf("PIWAR%u  =0x%08x\n", i, RD(REG_PIWAR(i)));
385 	}
386 	printf("\n");
387 #undef RD
388 
389 	for (i = 0; i < 0x48; i += 4) {
390 		printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
391 		    i, 4));
392 	}
393 }
394 #endif
395 
396 static int
397 fsl_pcib_maxslots(device_t dev)
398 {
399 	struct fsl_pcib_softc *sc = device_get_softc(dev);
400 
401 	return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
402 }
403 
404 static uint32_t
405 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
406     u_int reg, int bytes)
407 {
408 	struct fsl_pcib_softc *sc = device_get_softc(dev);
409 	u_int devfn;
410 
411 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
412 		return (~0);
413 	devfn = DEVFN(bus, slot, func);
414 	if (devfn == sc->sc_devfn_tundra)
415 		return (~0);
416 	if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
417 		return (1);
418 	return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
419 }
420 
421 static void
422 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
423     u_int reg, uint32_t val, int bytes)
424 {
425 	struct fsl_pcib_softc *sc = device_get_softc(dev);
426 
427 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
428 		return;
429 	fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
430 }
431 
432 static void
433 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
434     int slot, int fn)
435 {
436 
437 	if (device == 0x0686) {
438 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
439 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
440 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
441 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
442 	} else if (device == 0x0571) {
443 		sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
444 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
445 	}
446 }
447 
448 static int
449 fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
450     int barno)
451 {
452 	bus_addr_t *allocp;
453 	uint32_t addr, mask, size;
454 	int reg, width;
455 
456 	reg = PCIR_BAR(barno);
457 
458 	if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
459 		switch (barno) {
460 		case 0:	addr = 0x1f0; break;
461 		case 1: addr = 0x3f4; break;
462 		case 2: addr = 0x170; break;
463 		case 3: addr = 0x374; break;
464 		case 4: addr = 0xcc0; break;
465 		default: return (1);
466 		}
467 		fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
468 		return (1);
469 	}
470 
471 	fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
472 	size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
473 	if (size == 0)
474 		return (1);
475 	width = ((size & 7) == 4) ? 2 : 1;
476 
477 	if (size & 1) {		/* I/O port */
478 		allocp = &sc->sc_ioport_alloc;
479 		size &= ~3;
480 		if ((size & 0xffff0000) == 0)
481 			size |= 0xffff0000;
482 	} else {		/* memory */
483 		allocp = &sc->sc_iomem_alloc;
484 		size &= ~15;
485 	}
486 	mask = ~size;
487 	size = mask + 1;
488 	/* Sanity check (must be a power of 2). */
489 	if (size & mask)
490 		return (width);
491 
492 	addr = (*allocp + mask) & ~mask;
493 	*allocp = addr + size;
494 
495 	if (bootverbose)
496 		printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
497 		    device_get_unit(sc->sc_dev), bus, slot, func, reg,
498 		    size, addr);
499 
500 	fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
501 	if (width == 2)
502 		fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
503 		    0, 4);
504 	return (width);
505 }
506 
507 static int
508 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
509 {
510 	int secbus;
511 	int old_pribus, old_secbus, old_subbus;
512 	int new_pribus, new_secbus, new_subbus;
513 	int slot, func, maxfunc;
514 	int bar, maxbar;
515 	uint16_t vendor, device;
516 	uint8_t command, hdrtype, class, subclass;
517 
518 	secbus = bus;
519 	for (slot = 0; slot <= maxslot; slot++) {
520 		maxfunc = 0;
521 		for (func = 0; func <= maxfunc; func++) {
522 			hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
523 			    func, PCIR_HDRTYPE, 1);
524 
525 			if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
526 				continue;
527 
528 			if (func == 0 && (hdrtype & PCIM_MFDEV))
529 				maxfunc = PCI_FUNCMAX;
530 
531 			vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
532 			    func, PCIR_VENDOR, 2);
533 			device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
534 			    func, PCIR_DEVICE, 2);
535 
536 			if (vendor == 0x1957 && device == 0x3fff) {
537 				sc->sc_devfn_tundra = DEVFN(bus, slot, func);
538 				continue;
539 			}
540 
541 			command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
542 			    func, PCIR_COMMAND, 1);
543 			command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
544 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
545 			    PCIR_COMMAND, command, 1);
546 
547 			if (vendor == 0x1106)
548 				fsl_pcib_init_via(sc, device, bus, slot, func);
549 
550 			/* Program the base address registers. */
551 			maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
552 			bar = 0;
553 			while (bar < maxbar)
554 				bar += fsl_pcib_init_bar(sc, bus, slot, func,
555 				    bar);
556 
557 			/* Put a placeholder interrupt value */
558 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
559 			    PCIR_INTLINE, PCI_INVALID_IRQ, 1);
560 
561 			command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
562 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
563 			    PCIR_COMMAND, command, 1);
564 
565 			/*
566 			 * Handle PCI-PCI bridges
567 			 */
568 			class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
569 			    func, PCIR_CLASS, 1);
570 			subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
571 			    func, PCIR_SUBCLASS, 1);
572 
573 			/* Allow only proper PCI-PCI briges */
574 			if (class != PCIC_BRIDGE)
575 				continue;
576 			if (subclass != PCIS_BRIDGE_PCI)
577 				continue;
578 
579 			secbus++;
580 
581 			/* Program I/O decoder. */
582 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
583 			    PCIR_IOBASEL_1, sc->sc_ioport_start >> 8, 1);
584 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
585 			    PCIR_IOLIMITL_1, sc->sc_ioport_end >> 8, 1);
586 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
587 			    PCIR_IOBASEH_1, sc->sc_ioport_start >> 16, 2);
588 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
589 			    PCIR_IOLIMITH_1, sc->sc_ioport_end >> 16, 2);
590 
591 			/* Program (non-prefetchable) memory decoder. */
592 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
593 			    PCIR_MEMBASE_1, sc->sc_iomem_start >> 16, 2);
594 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
595 			    PCIR_MEMLIMIT_1, sc->sc_iomem_end >> 16, 2);
596 
597 			/* Program prefetchable memory decoder. */
598 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
599 			    PCIR_PMBASEL_1, 0x0010, 2);
600 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
601 			    PCIR_PMLIMITL_1, 0x000f, 2);
602 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
603 			    PCIR_PMBASEH_1, 0x00000000, 4);
604 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
605 			    PCIR_PMLIMITH_1, 0x00000000, 4);
606 
607 			/* Read currect bus register configuration */
608 			old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
609 			    slot, func, PCIR_PRIBUS_1, 1);
610 			old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
611 			    slot, func, PCIR_SECBUS_1, 1);
612 			old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
613 			    slot, func, PCIR_SUBBUS_1, 1);
614 
615 			if (bootverbose)
616 				printf("PCI: reading firmware bus numbers for "
617 				    "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
618 				    secbus, old_pribus, old_secbus, old_subbus);
619 
620 			new_pribus = bus;
621 			new_secbus = secbus;
622 
623 			secbus = fsl_pcib_init(sc, secbus,
624 			    (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
625 
626 			new_subbus = secbus;
627 
628 			if (bootverbose)
629 				printf("PCI: translate firmware bus numbers "
630 				    "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
631 				    secbus, old_pribus, old_secbus, old_subbus,
632 				    new_pribus, new_secbus, new_subbus);
633 
634 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
635 			    PCIR_PRIBUS_1, new_pribus, 1);
636 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
637 			    PCIR_SECBUS_1, new_secbus, 1);
638 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
639 			    PCIR_SUBBUS_1, new_subbus, 1);
640 		}
641 	}
642 
643 	return (secbus);
644 }
645 
646 static void
647 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start,
648     u_long size, u_long pci_start)
649 {
650 	uint32_t attr, bar, tar;
651 
652 	KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
653 
654 	switch (tgt) {
655 	/* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
656 	case OCP85XX_TGTIF_RAM1:
657 		attr = 0xa0f55000 | (ffsl(size) - 2);
658 		break;
659 	default:
660 		attr = 0;
661 		break;
662 	}
663 	tar = start >> 12;
664 	bar = pci_start >> 12;
665 
666 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
667 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
668 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
669 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
670 }
671 
672 static void
673 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start,
674     u_long size, u_long pci_start)
675 {
676 	uint32_t attr, bar, tar;
677 
678 	switch (res) {
679 	case SYS_RES_MEMORY:
680 		attr = 0x80044000 | (ffsl(size) - 2);
681 		break;
682 	case SYS_RES_IOPORT:
683 		attr = 0x80088000 | (ffsl(size) - 2);
684 		break;
685 	default:
686 		attr = 0x0004401f;
687 		break;
688 	}
689 	bar = start >> 12;
690 	tar = pci_start >> 12;
691 
692 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
693 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
694 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
695 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
696 }
697 
698 
699 static void
700 fsl_pcib_err_init(device_t dev)
701 {
702 	struct fsl_pcib_softc *sc;
703 	uint16_t sec_stat, dsr;
704 	uint32_t dcr, err_en;
705 
706 	sc = device_get_softc(dev);
707 
708 	sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
709 	if (sec_stat)
710 		fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
711 	if (sc->sc_pcie) {
712 		/* Clear error bits */
713 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
714 		    0xffffffff);
715 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
716 		    0xffffffff);
717 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
718 		    0xffffffff);
719 
720 		dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
721 		    sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
722 		if (dsr)
723 			fsl_pcib_cfgwrite(sc, 0, 0, 0,
724 			    sc->sc_pcie_capreg + PCIER_DEVICE_STA,
725 			    0xffff, 2);
726 
727 		/* Enable all errors reporting */
728 		err_en = 0x00bfff00;
729 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
730 		    err_en);
731 
732 		/* Enable error reporting: URR, FER, NFER */
733 		dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
734 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
735 		dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
736 		    PCIEM_CTL_NFER_ENABLE;
737 		fsl_pcib_cfgwrite(sc, 0, 0, 0,
738 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
739 	}
740 }
741 
742 static int
743 fsl_pcib_detach(device_t dev)
744 {
745 
746 	if (mtx_initialized) {
747 		mtx_destroy(&pcicfg_mtx);
748 		mtx_initialized = 0;
749 	}
750 	return (bus_generic_detach(dev));
751 }
752 
753 static int
754 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
755 {
756 	device_t dev;
757 	int error, i, trgt;
758 
759 	dev = sc->sc_dev;
760 
761 	fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
762 
763 	/*
764 	 * Configure LAW decode windows.
765 	 */
766 	error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
767 	    &sc->sc_ioport_target);
768 	if (error != 0) {
769 		device_printf(dev, "could not retrieve PCI LAW target info\n");
770 		return (error);
771 	}
772 
773 	for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
774 		switch (sc->pci_sc.sc_range[i].pci_hi &
775 		    OFW_PCI_PHYS_HI_SPACEMASK) {
776 		case OFW_PCI_PHYS_HI_SPACE_CONFIG:
777 			continue;
778 		case OFW_PCI_PHYS_HI_SPACE_IO:
779 			trgt = sc->sc_ioport_target;
780 			fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
781 			    sc->pci_sc.sc_range[i].host,
782 			    sc->pci_sc.sc_range[i].size,
783 			    sc->pci_sc.sc_range[i].pci);
784 			sc->sc_ioport_start = sc->pci_sc.sc_range[i].host;
785 			sc->sc_ioport_end = sc->pci_sc.sc_range[i].host +
786 			    sc->pci_sc.sc_range[i].size;
787 			sc->sc_ioport_alloc = 0x1000 + sc->pci_sc.sc_range[i].pci;
788 			break;
789 		case OFW_PCI_PHYS_HI_SPACE_MEM32:
790 		case OFW_PCI_PHYS_HI_SPACE_MEM64:
791 			trgt = sc->sc_iomem_target;
792 			fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
793 			    sc->pci_sc.sc_range[i].host,
794 			    sc->pci_sc.sc_range[i].size,
795 			    sc->pci_sc.sc_range[i].pci);
796 			sc->sc_iomem_start = sc->pci_sc.sc_range[i].host;
797 			sc->sc_iomem_end = sc->pci_sc.sc_range[i].host +
798 			    sc->pci_sc.sc_range[i].size;
799 			sc->sc_iomem_alloc = sc->pci_sc.sc_range[i].pci;
800 			break;
801 		default:
802 			panic("Unknown range type %#x\n",
803 			    sc->pci_sc.sc_range[i].pci_hi &
804 			    OFW_PCI_PHYS_HI_SPACEMASK);
805 		}
806 		error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
807 		    sc->pci_sc.sc_range[i].size);
808 		if (error != 0) {
809 			device_printf(dev, "could not program LAW for range "
810 			    "%d\n", i);
811 			return (error);
812 		}
813 	}
814 
815 	/*
816 	 * Set outbout and inbound windows.
817 	 */
818 	fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
819 	fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
820 
821 	fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
822 	fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
823 	fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
824 	    2U * 1024U * 1024U * 1024U, 0);
825 
826 	return (0);
827 }
828 
829