xref: /freebsd/sys/powerpc/mpc85xx/pci_mpc85xx.c (revision d70b36edb58ce06ef311ef4bfec5004f300929a5)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright 2006-2007 by Juniper Networks.
5  * Copyright 2008 Semihalf.
6  * Copyright 2010 The FreeBSD Foundation
7  * All rights reserved.
8  *
9  * Portions of this software were developed by Semihalf
10  * under sponsorship from the FreeBSD Foundation.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
36  */
37 
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/ktr.h>
44 #include <sys/sockio.h>
45 #include <sys/mbuf.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/queue.h>
51 #include <sys/bus.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/rman.h>
55 #include <sys/endian.h>
56 
57 #include <vm/vm.h>
58 #include <vm/pmap.h>
59 
60 #include <dev/ofw/ofw_pci.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/ofw/ofwpci.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcib_private.h>
67 
68 #include "ofw_bus_if.h"
69 #include "pcib_if.h"
70 
71 #include <machine/resource.h>
72 #include <machine/bus.h>
73 #include <machine/intr_machdep.h>
74 
75 #include <powerpc/mpc85xx/mpc85xx.h>
76 
77 #define	REG_CFG_ADDR	0x0000
78 #define	CONFIG_ACCESS_ENABLE	0x80000000
79 
80 #define	REG_CFG_DATA	0x0004
81 #define	REG_INT_ACK	0x0008
82 
83 #define	REG_POTAR(n)	(0x0c00 + 0x20 * (n))
84 #define	REG_POTEAR(n)	(0x0c04 + 0x20 * (n))
85 #define	REG_POWBAR(n)	(0x0c08 + 0x20 * (n))
86 #define	REG_POWAR(n)	(0x0c10 + 0x20 * (n))
87 
88 #define	REG_PITAR(n)	(0x0e00 - 0x20 * (n))
89 #define	REG_PIWBAR(n)	(0x0e08 - 0x20 * (n))
90 #define	REG_PIWBEAR(n)	(0x0e0c - 0x20 * (n))
91 #define	REG_PIWAR(n)	(0x0e10 - 0x20 * (n))
92 
93 #define	REG_PEX_MES_DR	0x0020
94 #define	REG_PEX_MES_IER	0x0028
95 #define	REG_PEX_ERR_DR	0x0e00
96 #define	REG_PEX_ERR_EN	0x0e08
97 
98 #define	REG_PEX_ERR_DR		0x0e00
99 #define	REG_PEX_ERR_DR_ME	0x80000000
100 #define	REG_PEX_ERR_DR_PCT	0x800000
101 #define	REG_PEX_ERR_DR_PAT	0x400000
102 #define	REG_PEX_ERR_DR_PCAC	0x200000
103 #define	REG_PEX_ERR_DR_PNM	0x100000
104 #define	REG_PEX_ERR_DR_CDNSC	0x80000
105 #define	REG_PEX_ERR_DR_CRSNC	0x40000
106 #define	REG_PEX_ERR_DR_ICCA	0x20000
107 #define	REG_PEX_ERR_DR_IACA	0x10000
108 #define	REG_PEX_ERR_DR_CRST	0x8000
109 #define	REG_PEX_ERR_DR_MIS	0x4000
110 #define	REG_PEX_ERR_DR_IOIS	0x2000
111 #define	REG_PEX_ERR_DR_CIS	0x1000
112 #define	REG_PEX_ERR_DR_CIEP	0x800
113 #define	REG_PEX_ERR_DR_IOIEP	0x400
114 #define	REG_PEX_ERR_DR_OAC	0x200
115 #define	REG_PEX_ERR_DR_IOIA	0x100
116 #define	REG_PEX_ERR_DR_IMBA	0x80
117 #define	REG_PEX_ERR_DR_IIOBA	0x40
118 #define	REG_PEX_ERR_DR_LDDE	0x20
119 #define	REG_PEX_ERR_EN		0x0e08
120 
121 #define PCIR_LTSSM	0x404
122 #define LTSSM_STAT_L0	0x16
123 
124 #define	DEVFN(b, s, f)	((b << 16) | (s << 8) | f)
125 
126 struct fsl_pcib_softc {
127 	struct ofw_pci_softc pci_sc;
128 	device_t	sc_dev;
129 
130 	int		sc_iomem_target;
131 	bus_addr_t	sc_iomem_start, sc_iomem_end;
132 	int		sc_ioport_target;
133 	bus_addr_t	sc_ioport_start, sc_ioport_end;
134 
135 	struct resource *sc_res;
136 	bus_space_handle_t sc_bsh;
137 	bus_space_tag_t	sc_bst;
138 	int		sc_rid;
139 
140 	struct resource	*sc_irq_res;
141 	void		*sc_ih;
142 
143 	int		sc_busnr;
144 	int		sc_pcie;
145 	uint8_t		sc_pcie_capreg;		/* PCI-E Capability Reg Set */
146 
147 	/* Devices that need special attention. */
148 	int		sc_devfn_tundra;
149 	int		sc_devfn_via_ide;
150 };
151 
152 struct fsl_pcib_err_dr {
153 	const char	*msg;
154 	uint32_t	err_dr_mask;
155 };
156 
157 static const struct fsl_pcib_err_dr pci_err[] = {
158 	{"ME",		REG_PEX_ERR_DR_ME},
159 	{"PCT",		REG_PEX_ERR_DR_PCT},
160 	{"PAT",		REG_PEX_ERR_DR_PAT},
161 	{"PCAC",	REG_PEX_ERR_DR_PCAC},
162 	{"PNM",		REG_PEX_ERR_DR_PNM},
163 	{"CDNSC",	REG_PEX_ERR_DR_CDNSC},
164 	{"CRSNC",	REG_PEX_ERR_DR_CRSNC},
165 	{"ICCA",	REG_PEX_ERR_DR_ICCA},
166 	{"IACA",	REG_PEX_ERR_DR_IACA},
167 	{"CRST",	REG_PEX_ERR_DR_CRST},
168 	{"MIS",		REG_PEX_ERR_DR_MIS},
169 	{"IOIS",	REG_PEX_ERR_DR_IOIS},
170 	{"CIS",		REG_PEX_ERR_DR_CIS},
171 	{"CIEP",	REG_PEX_ERR_DR_CIEP},
172 	{"IOIEP",	REG_PEX_ERR_DR_IOIEP},
173 	{"OAC",		REG_PEX_ERR_DR_OAC},
174 	{"IOIA",	REG_PEX_ERR_DR_IOIA},
175 	{"IMBA",	REG_PEX_ERR_DR_IMBA},
176 	{"IIOBA",	REG_PEX_ERR_DR_IIOBA},
177 	{"LDDE",	REG_PEX_ERR_DR_LDDE}
178 };
179 
180 /* Local forward declerations. */
181 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
182     u_int, int);
183 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
184     u_int, uint32_t, int);
185 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
186 static void fsl_pcib_err_init(device_t);
187 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
188     uint64_t, uint64_t);
189 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
190 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
191     uint64_t, uint64_t);
192 
193 /* Forward declerations. */
194 static int fsl_pcib_attach(device_t);
195 static int fsl_pcib_detach(device_t);
196 static int fsl_pcib_probe(device_t);
197 
198 static int fsl_pcib_maxslots(device_t);
199 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
200 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
201     uint32_t, int);
202 
203 /* Configuration r/w mutex. */
204 struct mtx pcicfg_mtx;
205 static int mtx_initialized = 0;
206 
207 /*
208  * Bus interface definitions.
209  */
210 static device_method_t fsl_pcib_methods[] = {
211 	/* Device interface */
212 	DEVMETHOD(device_probe,		fsl_pcib_probe),
213 	DEVMETHOD(device_attach,	fsl_pcib_attach),
214 	DEVMETHOD(device_detach,	fsl_pcib_detach),
215 
216 	/* pcib interface */
217 	DEVMETHOD(pcib_maxslots,	fsl_pcib_maxslots),
218 	DEVMETHOD(pcib_read_config,	fsl_pcib_read_config),
219 	DEVMETHOD(pcib_write_config,	fsl_pcib_write_config),
220 
221 	DEVMETHOD_END
222 };
223 
224 static devclass_t fsl_pcib_devclass;
225 
226 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
227     sizeof(struct fsl_pcib_softc), ofw_pci_driver);
228 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0,
229     BUS_PASS_BUS);
230 
231 static void
232 fsl_pcib_err_intr(void *v)
233 {
234 	struct fsl_pcib_softc *sc;
235 	device_t dev;
236 	uint32_t err_reg, clear_reg;
237 	uint8_t i;
238 
239 	dev = (device_t)v;
240 	sc = device_get_softc(dev);
241 
242 	clear_reg = 0;
243 	err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);
244 
245 	/* Check which one error occurred */
246 	for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) {
247 		if (err_reg & pci_err[i].err_dr_mask) {
248 			device_printf(dev, "PCI %d: report %s error\n",
249 			    device_get_unit(dev), pci_err[i].msg);
250 			clear_reg |= pci_err[i].err_dr_mask;
251 		}
252 	}
253 
254 	/* Clear pending errors */
255 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);
256 }
257 
258 static int
259 fsl_pcib_probe(device_t dev)
260 {
261 
262 	if (ofw_bus_get_type(dev) == NULL ||
263 	    strcmp(ofw_bus_get_type(dev), "pci") != 0)
264 		return (ENXIO);
265 
266 	if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
267 	    ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
268 	    ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||
269 	    ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||
270 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||
271 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))
272 		return (ENXIO);
273 
274 	device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
275 	return (BUS_PROBE_DEFAULT);
276 }
277 
278 static int
279 fsl_pcib_attach(device_t dev)
280 {
281 	struct fsl_pcib_softc *sc;
282 	phandle_t node;
283 	uint32_t cfgreg;
284 	int error, maxslot, rid;
285 	uint8_t ltssm, capptr;
286 
287 	sc = device_get_softc(dev);
288 	sc->sc_dev = dev;
289 
290 	sc->sc_rid = 0;
291 	sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
292 	    RF_ACTIVE);
293 	if (sc->sc_res == NULL) {
294 		device_printf(dev, "could not map I/O memory\n");
295 		return (ENXIO);
296 	}
297 	sc->sc_bst = rman_get_bustag(sc->sc_res);
298 	sc->sc_bsh = rman_get_bushandle(sc->sc_res);
299 	sc->sc_busnr = 0;
300 
301 	if (!mtx_initialized) {
302 		mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
303 		mtx_initialized = 1;
304 	}
305 
306 	cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
307 	if (cfgreg != 0x1057 && cfgreg != 0x1957)
308 		goto err;
309 
310 	capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
311 	while (capptr != 0) {
312 		cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
313 		switch (cfgreg & 0xff) {
314 		case PCIY_PCIX:
315 			break;
316 		case PCIY_EXPRESS:
317 			sc->sc_pcie = 1;
318 			sc->sc_pcie_capreg = capptr;
319 			break;
320 		}
321 		capptr = (cfgreg >> 8) & 0xff;
322 	}
323 
324 	node = ofw_bus_get_node(dev);
325 
326 	/*
327 	 * Initialize generic OF PCI interface (ranges, etc.)
328 	 */
329 
330 	error = ofw_pci_init(dev);
331 	if (error)
332 		return (error);
333 
334 	/*
335 	 * Configure decode windows for PCI(E) access.
336 	 */
337 	if (fsl_pcib_decode_win(node, sc) != 0)
338 		goto err;
339 
340 	cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
341 	cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
342 	    PCIM_CMD_PORTEN;
343 	fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
344 
345 	sc->sc_devfn_tundra = -1;
346 	sc->sc_devfn_via_ide = -1;
347 
348 
349 	/*
350 	 * Scan bus using firmware configured, 0 based bus numbering.
351 	 */
352 	maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
353 	fsl_pcib_init(sc, sc->sc_busnr, maxslot);
354 
355 	if (sc->sc_pcie) {
356 		ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
357 		if (ltssm < LTSSM_STAT_L0) {
358 			if (bootverbose)
359 				printf("PCI %d: no PCIE link, skipping\n",
360 				    device_get_unit(dev));
361 			return (0);
362 		}
363 	}
364 
365 	/* Allocate irq */
366 	rid = 0;
367 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
368 	    RF_ACTIVE | RF_SHAREABLE);
369 	if (sc->sc_irq_res == NULL) {
370 		error = fsl_pcib_detach(dev);
371 		if (error != 0) {
372 			device_printf(dev,
373 			    "Detach of the driver failed with error %d\n",
374 			    error);
375 		}
376 		return (ENXIO);
377 	}
378 
379 	/* Setup interrupt handler */
380 	error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
381 	    NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);
382 	if (error != 0) {
383 		device_printf(dev, "Could not setup irq, %d\n", error);
384 		sc->sc_ih = NULL;
385 		error = fsl_pcib_detach(dev);
386 		if (error != 0) {
387 			device_printf(dev,
388 			    "Detach of the driver failed with error %d\n",
389 			    error);
390 		}
391 		return (ENXIO);
392 	}
393 
394 	fsl_pcib_err_init(dev);
395 
396 	return (ofw_pci_attach(dev));
397 
398 err:
399 	return (ENXIO);
400 }
401 
402 static uint32_t
403 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
404     u_int reg, int bytes)
405 {
406 	uint32_t addr, data;
407 
408 	addr = CONFIG_ACCESS_ENABLE;
409 	addr |= (bus & 0xff) << 16;
410 	addr |= (slot & 0x1f) << 11;
411 	addr |= (func & 0x7) << 8;
412 	addr |= reg & 0xfc;
413 	if (sc->sc_pcie)
414 		addr |= (reg & 0xf00) << 16;
415 
416 	mtx_lock_spin(&pcicfg_mtx);
417 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
418 
419 	switch (bytes) {
420 	case 1:
421 		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
422 		    REG_CFG_DATA + (reg & 3));
423 		break;
424 	case 2:
425 		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
426 		    REG_CFG_DATA + (reg & 2)));
427 		break;
428 	case 4:
429 		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
430 		    REG_CFG_DATA));
431 		break;
432 	default:
433 		data = ~0;
434 		break;
435 	}
436 	mtx_unlock_spin(&pcicfg_mtx);
437 	return (data);
438 }
439 
440 static void
441 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
442     u_int reg, uint32_t data, int bytes)
443 {
444 	uint32_t addr;
445 
446 	addr = CONFIG_ACCESS_ENABLE;
447 	addr |= (bus & 0xff) << 16;
448 	addr |= (slot & 0x1f) << 11;
449 	addr |= (func & 0x7) << 8;
450 	addr |= reg & 0xfc;
451 	if (sc->sc_pcie)
452 		addr |= (reg & 0xf00) << 16;
453 
454 	mtx_lock_spin(&pcicfg_mtx);
455 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
456 
457 	switch (bytes) {
458 	case 1:
459 		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
460 		    REG_CFG_DATA + (reg & 3), data);
461 		break;
462 	case 2:
463 		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
464 		    REG_CFG_DATA + (reg & 2), htole16(data));
465 		break;
466 	case 4:
467 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
468 		    REG_CFG_DATA, htole32(data));
469 		break;
470 	}
471 	mtx_unlock_spin(&pcicfg_mtx);
472 }
473 
474 #if 0
475 static void
476 dump(struct fsl_pcib_softc *sc)
477 {
478 	unsigned int i;
479 
480 #define RD(o)	bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
481 	for (i = 0; i < 5; i++) {
482 		printf("POTAR%u  =0x%08x\n", i, RD(REG_POTAR(i)));
483 		printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
484 		printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
485 		printf("POWAR%u  =0x%08x\n", i, RD(REG_POWAR(i)));
486 	}
487 	printf("\n");
488 	for (i = 1; i < 4; i++) {
489 		printf("PITAR%u  =0x%08x\n", i, RD(REG_PITAR(i)));
490 		printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
491 		printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
492 		printf("PIWAR%u  =0x%08x\n", i, RD(REG_PIWAR(i)));
493 	}
494 	printf("\n");
495 #undef RD
496 
497 	for (i = 0; i < 0x48; i += 4) {
498 		printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
499 		    i, 4));
500 	}
501 }
502 #endif
503 
504 static int
505 fsl_pcib_maxslots(device_t dev)
506 {
507 	struct fsl_pcib_softc *sc = device_get_softc(dev);
508 
509 	return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
510 }
511 
512 static uint32_t
513 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
514     u_int reg, int bytes)
515 {
516 	struct fsl_pcib_softc *sc = device_get_softc(dev);
517 	u_int devfn;
518 
519 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
520 		return (~0);
521 	devfn = DEVFN(bus, slot, func);
522 	if (devfn == sc->sc_devfn_tundra)
523 		return (~0);
524 	if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
525 		return (1);
526 	return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
527 }
528 
529 static void
530 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
531     u_int reg, uint32_t val, int bytes)
532 {
533 	struct fsl_pcib_softc *sc = device_get_softc(dev);
534 
535 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
536 		return;
537 	fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
538 }
539 
540 static void
541 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
542     int slot, int fn)
543 {
544 
545 	if (device == 0x0686) {
546 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
547 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
548 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
549 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
550 	} else if (device == 0x0571) {
551 		sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
552 		fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
553 	}
554 }
555 
556 static int
557 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
558 {
559 	int secbus;
560 	int old_pribus, old_secbus, old_subbus;
561 	int new_pribus, new_secbus, new_subbus;
562 	int slot, func, maxfunc;
563 	uint16_t vendor, device;
564 	uint8_t brctl, command, hdrtype, subclass;
565 
566 	secbus = bus;
567 	for (slot = 0; slot <= maxslot; slot++) {
568 		maxfunc = 0;
569 		for (func = 0; func <= maxfunc; func++) {
570 			hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
571 			    func, PCIR_HDRTYPE, 1);
572 
573 			if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
574 				continue;
575 
576 			if (func == 0 && (hdrtype & PCIM_MFDEV))
577 				maxfunc = PCI_FUNCMAX;
578 
579 			vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
580 			    func, PCIR_VENDOR, 2);
581 			device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
582 			    func, PCIR_DEVICE, 2);
583 
584 			if (vendor == 0x1957 && device == 0x3fff) {
585 				sc->sc_devfn_tundra = DEVFN(bus, slot, func);
586 				continue;
587 			}
588 
589 			command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
590 			    func, PCIR_COMMAND, 1);
591 			command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
592 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
593 			    PCIR_COMMAND, command, 1);
594 
595 			if (vendor == 0x1106)
596 				fsl_pcib_init_via(sc, device, bus, slot, func);
597 
598 			/*
599 			 * Handle PCI-PCI bridges
600 			 */
601 			subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
602 			    func, PCIR_SUBCLASS, 1);
603 
604 			/* Allow all DEVTYPE 1 devices */
605 			if (hdrtype != PCIM_HDRTYPE_BRIDGE)
606 				continue;
607 
608 			brctl = fsl_pcib_read_config(sc->sc_dev, bus, slot, func,
609 			    PCIR_BRIDGECTL_1, 1);
610 			brctl |= PCIB_BCR_SECBUS_RESET;
611 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
612 			    PCIR_BRIDGECTL_1, brctl, 1);
613 			DELAY(100000);
614 			brctl &= ~PCIB_BCR_SECBUS_RESET;
615 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
616 			    PCIR_BRIDGECTL_1, brctl, 1);
617 			DELAY(100000);
618 
619 			secbus++;
620 
621 			/* Read currect bus register configuration */
622 			old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
623 			    slot, func, PCIR_PRIBUS_1, 1);
624 			old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
625 			    slot, func, PCIR_SECBUS_1, 1);
626 			old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
627 			    slot, func, PCIR_SUBBUS_1, 1);
628 
629 			if (bootverbose)
630 				printf("PCI: reading firmware bus numbers for "
631 				    "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
632 				    secbus, old_pribus, old_secbus, old_subbus);
633 
634 			new_pribus = bus;
635 			new_secbus = secbus;
636 
637 			secbus = fsl_pcib_init(sc, secbus,
638 			    (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
639 
640 			new_subbus = secbus;
641 
642 			if (bootverbose)
643 				printf("PCI: translate firmware bus numbers "
644 				    "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
645 				    secbus, old_pribus, old_secbus, old_subbus,
646 				    new_pribus, new_secbus, new_subbus);
647 
648 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
649 			    PCIR_PRIBUS_1, new_pribus, 1);
650 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
651 			    PCIR_SECBUS_1, new_secbus, 1);
652 			fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
653 			    PCIR_SUBBUS_1, new_subbus, 1);
654 		}
655 	}
656 
657 	return (secbus);
658 }
659 
660 static void
661 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
662     uint64_t size, uint64_t pci_start)
663 {
664 	uint32_t attr, bar, tar;
665 
666 	KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
667 
668 	switch (tgt) {
669 	/* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
670 	case OCP85XX_TGTIF_RAM1_85XX:
671 	case OCP85XX_TGTIF_RAM1_QORIQ:
672 		attr = 0xa0f55000 | (ffsl(size) - 2);
673 		break;
674 	default:
675 		attr = 0;
676 		break;
677 	}
678 	tar = start >> 12;
679 	bar = pci_start >> 12;
680 
681 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
682 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
683 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
684 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
685 }
686 
687 static void
688 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
689     uint64_t size, uint64_t pci_start)
690 {
691 	uint32_t attr, bar, tar;
692 
693 	switch (res) {
694 	case SYS_RES_MEMORY:
695 		attr = 0x80044000 | (ffsll(size) - 2);
696 		break;
697 	case SYS_RES_IOPORT:
698 		attr = 0x80088000 | (ffsll(size) - 2);
699 		break;
700 	default:
701 		attr = 0x0004401f;
702 		break;
703 	}
704 	bar = start >> 12;
705 	tar = pci_start >> 12;
706 
707 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
708 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
709 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
710 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
711 }
712 
713 
714 static void
715 fsl_pcib_err_init(device_t dev)
716 {
717 	struct fsl_pcib_softc *sc;
718 	uint16_t sec_stat, dsr;
719 	uint32_t dcr, err_en;
720 
721 	sc = device_get_softc(dev);
722 
723 	sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
724 	if (sec_stat)
725 		fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
726 	if (sc->sc_pcie) {
727 		/* Clear error bits */
728 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
729 		    0xffffffff);
730 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
731 		    0xffffffff);
732 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
733 		    0xffffffff);
734 
735 		dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
736 		    sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
737 		if (dsr)
738 			fsl_pcib_cfgwrite(sc, 0, 0, 0,
739 			    sc->sc_pcie_capreg + PCIER_DEVICE_STA,
740 			    0xffff, 2);
741 
742 		/* Enable all errors reporting */
743 		err_en = 0x00bfff00;
744 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
745 		    err_en);
746 
747 		/* Enable error reporting: URR, FER, NFER */
748 		dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
749 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
750 		dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
751 		    PCIEM_CTL_NFER_ENABLE;
752 		fsl_pcib_cfgwrite(sc, 0, 0, 0,
753 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
754 	}
755 }
756 
757 static int
758 fsl_pcib_detach(device_t dev)
759 {
760 
761 	if (mtx_initialized) {
762 		mtx_destroy(&pcicfg_mtx);
763 		mtx_initialized = 0;
764 	}
765 	return (bus_generic_detach(dev));
766 }
767 
768 static int
769 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
770 {
771 	device_t dev;
772 	int error, i, trgt;
773 
774 	dev = sc->sc_dev;
775 
776 	fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
777 
778 	/*
779 	 * Configure LAW decode windows.
780 	 */
781 	error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
782 	    &sc->sc_ioport_target);
783 	if (error != 0) {
784 		device_printf(dev, "could not retrieve PCI LAW target info\n");
785 		return (error);
786 	}
787 
788 	for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
789 		switch (sc->pci_sc.sc_range[i].pci_hi &
790 		    OFW_PCI_PHYS_HI_SPACEMASK) {
791 		case OFW_PCI_PHYS_HI_SPACE_CONFIG:
792 			continue;
793 		case OFW_PCI_PHYS_HI_SPACE_IO:
794 			trgt = sc->sc_ioport_target;
795 			fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
796 			    sc->pci_sc.sc_range[i].host,
797 			    sc->pci_sc.sc_range[i].size,
798 			    sc->pci_sc.sc_range[i].pci);
799 			sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
800 			sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
801 			    sc->pci_sc.sc_range[i].size - 1;
802 			break;
803 		case OFW_PCI_PHYS_HI_SPACE_MEM32:
804 		case OFW_PCI_PHYS_HI_SPACE_MEM64:
805 			trgt = sc->sc_iomem_target;
806 			fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
807 			    sc->pci_sc.sc_range[i].host,
808 			    sc->pci_sc.sc_range[i].size,
809 			    sc->pci_sc.sc_range[i].pci);
810 			sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
811 			sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
812 			    sc->pci_sc.sc_range[i].size - 1;
813 			break;
814 		default:
815 			panic("Unknown range type %#x\n",
816 			    sc->pci_sc.sc_range[i].pci_hi &
817 			    OFW_PCI_PHYS_HI_SPACEMASK);
818 		}
819 		error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
820 		    sc->pci_sc.sc_range[i].size);
821 		if (error != 0) {
822 			device_printf(dev, "could not program LAW for range "
823 			    "%d\n", i);
824 			return (error);
825 		}
826 	}
827 
828 	/*
829 	 * Set outbout and inbound windows.
830 	 */
831 	fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
832 	fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
833 
834 	fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
835 	fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
836 	fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
837 	    2U * 1024U * 1024U * 1024U, 0);
838 
839 	return (0);
840 }
841