1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ktr.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/socket.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/rman.h> 55 #include <sys/endian.h> 56 57 #include <vm/vm.h> 58 #include <vm/pmap.h> 59 60 #include <dev/ofw/ofw_pci.h> 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 #include <dev/ofw/ofwpci.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcib_private.h> 67 68 #include "ofw_bus_if.h" 69 #include "pcib_if.h" 70 71 #include <machine/resource.h> 72 #include <machine/bus.h> 73 #include <machine/intr_machdep.h> 74 75 #include <powerpc/mpc85xx/mpc85xx.h> 76 77 #define REG_CFG_ADDR 0x0000 78 #define CONFIG_ACCESS_ENABLE 0x80000000 79 80 #define REG_CFG_DATA 0x0004 81 #define REG_INT_ACK 0x0008 82 83 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 84 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 85 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 86 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 87 88 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 89 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 90 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 91 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 92 93 #define REG_PEX_MES_DR 0x0020 94 #define REG_PEX_MES_IER 0x0028 95 #define REG_PEX_ERR_DR 0x0e00 96 #define REG_PEX_ERR_EN 0x0e08 97 98 #define REG_PEX_ERR_DR 0x0e00 99 #define REG_PEX_ERR_DR_ME 0x80000000 100 #define REG_PEX_ERR_DR_PCT 0x800000 101 #define REG_PEX_ERR_DR_PAT 0x400000 102 #define REG_PEX_ERR_DR_PCAC 0x200000 103 #define REG_PEX_ERR_DR_PNM 0x100000 104 #define REG_PEX_ERR_DR_CDNSC 0x80000 105 #define REG_PEX_ERR_DR_CRSNC 0x40000 106 #define REG_PEX_ERR_DR_ICCA 0x20000 107 #define REG_PEX_ERR_DR_IACA 0x10000 108 #define REG_PEX_ERR_DR_CRST 0x8000 109 #define REG_PEX_ERR_DR_MIS 0x4000 110 #define REG_PEX_ERR_DR_IOIS 0x2000 111 #define REG_PEX_ERR_DR_CIS 0x1000 112 #define REG_PEX_ERR_DR_CIEP 0x800 113 #define REG_PEX_ERR_DR_IOIEP 0x400 114 #define REG_PEX_ERR_DR_OAC 0x200 115 #define REG_PEX_ERR_DR_IOIA 0x100 116 #define REG_PEX_ERR_DR_IMBA 0x80 117 #define REG_PEX_ERR_DR_IIOBA 0x40 118 #define REG_PEX_ERR_DR_LDDE 0x20 119 #define REG_PEX_ERR_EN 0x0e08 120 121 #define PCIR_LTSSM 0x404 122 #define LTSSM_STAT_L0 0x16 123 124 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 125 126 struct fsl_pcib_softc { 127 struct ofw_pci_softc pci_sc; 128 device_t sc_dev; 129 130 int sc_iomem_target; 131 bus_addr_t sc_iomem_start, sc_iomem_end; 132 int sc_ioport_target; 133 bus_addr_t sc_ioport_start, sc_ioport_end; 134 135 struct resource *sc_res; 136 bus_space_handle_t sc_bsh; 137 bus_space_tag_t sc_bst; 138 int sc_rid; 139 140 struct resource *sc_irq_res; 141 void *sc_ih; 142 143 int sc_busnr; 144 int sc_pcie; 145 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 146 147 /* Devices that need special attention. */ 148 int sc_devfn_tundra; 149 int sc_devfn_via_ide; 150 }; 151 152 struct fsl_pcib_err_dr { 153 const char *msg; 154 uint32_t err_dr_mask; 155 }; 156 157 static const struct fsl_pcib_err_dr pci_err[] = { 158 {"ME", REG_PEX_ERR_DR_ME}, 159 {"PCT", REG_PEX_ERR_DR_PCT}, 160 {"PAT", REG_PEX_ERR_DR_PAT}, 161 {"PCAC", REG_PEX_ERR_DR_PCAC}, 162 {"PNM", REG_PEX_ERR_DR_PNM}, 163 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 164 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 165 {"ICCA", REG_PEX_ERR_DR_ICCA}, 166 {"IACA", REG_PEX_ERR_DR_IACA}, 167 {"CRST", REG_PEX_ERR_DR_CRST}, 168 {"MIS", REG_PEX_ERR_DR_MIS}, 169 {"IOIS", REG_PEX_ERR_DR_IOIS}, 170 {"CIS", REG_PEX_ERR_DR_CIS}, 171 {"CIEP", REG_PEX_ERR_DR_CIEP}, 172 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 173 {"OAC", REG_PEX_ERR_DR_OAC}, 174 {"IOIA", REG_PEX_ERR_DR_IOIA}, 175 {"IMBA", REG_PEX_ERR_DR_IMBA}, 176 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 177 {"LDDE", REG_PEX_ERR_DR_LDDE} 178 }; 179 180 /* Local forward declerations. */ 181 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 182 u_int, int); 183 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 184 u_int, uint32_t, int); 185 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 186 static void fsl_pcib_err_init(device_t); 187 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 188 uint64_t, uint64_t); 189 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 190 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 191 uint64_t, uint64_t); 192 193 /* Forward declerations. */ 194 static int fsl_pcib_attach(device_t); 195 static int fsl_pcib_detach(device_t); 196 static int fsl_pcib_probe(device_t); 197 198 static int fsl_pcib_maxslots(device_t); 199 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 200 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 201 uint32_t, int); 202 203 /* Configuration r/w mutex. */ 204 struct mtx pcicfg_mtx; 205 static int mtx_initialized = 0; 206 207 /* 208 * Bus interface definitions. 209 */ 210 static device_method_t fsl_pcib_methods[] = { 211 /* Device interface */ 212 DEVMETHOD(device_probe, fsl_pcib_probe), 213 DEVMETHOD(device_attach, fsl_pcib_attach), 214 DEVMETHOD(device_detach, fsl_pcib_detach), 215 216 /* pcib interface */ 217 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 218 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 219 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 220 221 DEVMETHOD_END 222 }; 223 224 static devclass_t fsl_pcib_devclass; 225 226 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 227 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 228 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0, 229 BUS_PASS_BUS); 230 231 static int 232 fsl_pcib_err_intr(void *v) 233 { 234 struct fsl_pcib_softc *sc; 235 device_t dev; 236 uint32_t err_reg, clear_reg; 237 uint8_t i; 238 239 dev = (device_t)v; 240 sc = device_get_softc(dev); 241 242 clear_reg = 0; 243 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 244 245 /* Check which one error occurred */ 246 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 247 if (err_reg & pci_err[i].err_dr_mask) { 248 device_printf(dev, "PCI %d: report %s error\n", 249 device_get_unit(dev), pci_err[i].msg); 250 clear_reg |= pci_err[i].err_dr_mask; 251 } 252 } 253 254 /* Clear pending errors */ 255 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 256 257 return (0); 258 } 259 260 static int 261 fsl_pcib_probe(device_t dev) 262 { 263 264 if (ofw_bus_get_type(dev) == NULL || 265 strcmp(ofw_bus_get_type(dev), "pci") != 0) 266 return (ENXIO); 267 268 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 269 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 270 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 271 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 272 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 273 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 274 return (ENXIO); 275 276 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 277 return (BUS_PROBE_DEFAULT); 278 } 279 280 static int 281 fsl_pcib_attach(device_t dev) 282 { 283 struct fsl_pcib_softc *sc; 284 phandle_t node; 285 uint32_t cfgreg; 286 int error, maxslot, rid; 287 uint8_t ltssm, capptr; 288 289 sc = device_get_softc(dev); 290 sc->sc_dev = dev; 291 292 sc->sc_rid = 0; 293 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 294 RF_ACTIVE); 295 if (sc->sc_res == NULL) { 296 device_printf(dev, "could not map I/O memory\n"); 297 return (ENXIO); 298 } 299 sc->sc_bst = rman_get_bustag(sc->sc_res); 300 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 301 sc->sc_busnr = 0; 302 303 if (!mtx_initialized) { 304 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 305 mtx_initialized = 1; 306 } 307 308 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 309 if (cfgreg != 0x1057 && cfgreg != 0x1957) 310 goto err; 311 312 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 313 while (capptr != 0) { 314 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 315 switch (cfgreg & 0xff) { 316 case PCIY_PCIX: 317 break; 318 case PCIY_EXPRESS: 319 sc->sc_pcie = 1; 320 sc->sc_pcie_capreg = capptr; 321 break; 322 } 323 capptr = (cfgreg >> 8) & 0xff; 324 } 325 326 node = ofw_bus_get_node(dev); 327 328 /* 329 * Initialize generic OF PCI interface (ranges, etc.) 330 */ 331 332 error = ofw_pci_init(dev); 333 if (error) 334 return (error); 335 336 /* 337 * Configure decode windows for PCI(E) access. 338 */ 339 if (fsl_pcib_decode_win(node, sc) != 0) 340 goto err; 341 342 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 343 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 344 PCIM_CMD_PORTEN; 345 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 346 347 sc->sc_devfn_tundra = -1; 348 sc->sc_devfn_via_ide = -1; 349 350 351 /* 352 * Scan bus using firmware configured, 0 based bus numbering. 353 */ 354 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 355 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 356 357 if (sc->sc_pcie) { 358 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 359 if (ltssm < LTSSM_STAT_L0) { 360 if (bootverbose) 361 printf("PCI %d: no PCIE link, skipping\n", 362 device_get_unit(dev)); 363 return (0); 364 } 365 } 366 367 /* Allocate irq */ 368 rid = 0; 369 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 370 RF_ACTIVE | RF_SHAREABLE); 371 if (sc->sc_irq_res == NULL) { 372 error = fsl_pcib_detach(dev); 373 if (error != 0) { 374 device_printf(dev, 375 "Detach of the driver failed with error %d\n", 376 error); 377 } 378 return (ENXIO); 379 } 380 381 /* Setup interrupt handler */ 382 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 383 NULL, (driver_intr_t *)fsl_pcib_err_intr, dev, &sc->sc_ih); 384 if (error != 0) { 385 device_printf(dev, "Could not setup irq, %d\n", error); 386 sc->sc_ih = NULL; 387 error = fsl_pcib_detach(dev); 388 if (error != 0) { 389 device_printf(dev, 390 "Detach of the driver failed with error %d\n", 391 error); 392 } 393 return (ENXIO); 394 } 395 396 fsl_pcib_err_init(dev); 397 398 return (ofw_pci_attach(dev)); 399 400 err: 401 return (ENXIO); 402 } 403 404 static uint32_t 405 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 406 u_int reg, int bytes) 407 { 408 uint32_t addr, data; 409 410 addr = CONFIG_ACCESS_ENABLE; 411 addr |= (bus & 0xff) << 16; 412 addr |= (slot & 0x1f) << 11; 413 addr |= (func & 0x7) << 8; 414 addr |= reg & 0xfc; 415 if (sc->sc_pcie) 416 addr |= (reg & 0xf00) << 16; 417 418 mtx_lock_spin(&pcicfg_mtx); 419 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 420 421 switch (bytes) { 422 case 1: 423 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 424 REG_CFG_DATA + (reg & 3)); 425 break; 426 case 2: 427 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 428 REG_CFG_DATA + (reg & 2))); 429 break; 430 case 4: 431 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 432 REG_CFG_DATA)); 433 break; 434 default: 435 data = ~0; 436 break; 437 } 438 mtx_unlock_spin(&pcicfg_mtx); 439 return (data); 440 } 441 442 static void 443 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 444 u_int reg, uint32_t data, int bytes) 445 { 446 uint32_t addr; 447 448 addr = CONFIG_ACCESS_ENABLE; 449 addr |= (bus & 0xff) << 16; 450 addr |= (slot & 0x1f) << 11; 451 addr |= (func & 0x7) << 8; 452 addr |= reg & 0xfc; 453 if (sc->sc_pcie) 454 addr |= (reg & 0xf00) << 16; 455 456 mtx_lock_spin(&pcicfg_mtx); 457 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 458 459 switch (bytes) { 460 case 1: 461 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 462 REG_CFG_DATA + (reg & 3), data); 463 break; 464 case 2: 465 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 466 REG_CFG_DATA + (reg & 2), htole16(data)); 467 break; 468 case 4: 469 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 470 REG_CFG_DATA, htole32(data)); 471 break; 472 } 473 mtx_unlock_spin(&pcicfg_mtx); 474 } 475 476 #if 0 477 static void 478 dump(struct fsl_pcib_softc *sc) 479 { 480 unsigned int i; 481 482 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 483 for (i = 0; i < 5; i++) { 484 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 485 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 486 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 487 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 488 } 489 printf("\n"); 490 for (i = 1; i < 4; i++) { 491 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 492 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 493 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 494 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 495 } 496 printf("\n"); 497 #undef RD 498 499 for (i = 0; i < 0x48; i += 4) { 500 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 501 i, 4)); 502 } 503 } 504 #endif 505 506 static int 507 fsl_pcib_maxslots(device_t dev) 508 { 509 struct fsl_pcib_softc *sc = device_get_softc(dev); 510 511 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 512 } 513 514 static uint32_t 515 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 516 u_int reg, int bytes) 517 { 518 struct fsl_pcib_softc *sc = device_get_softc(dev); 519 u_int devfn; 520 521 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 522 return (~0); 523 devfn = DEVFN(bus, slot, func); 524 if (devfn == sc->sc_devfn_tundra) 525 return (~0); 526 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 527 return (1); 528 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 529 } 530 531 static void 532 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 533 u_int reg, uint32_t val, int bytes) 534 { 535 struct fsl_pcib_softc *sc = device_get_softc(dev); 536 537 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 538 return; 539 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 540 } 541 542 static void 543 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 544 int slot, int fn) 545 { 546 547 if (device == 0x0686) { 548 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 549 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 550 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 551 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 552 } else if (device == 0x0571) { 553 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 554 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 555 } 556 } 557 558 static int 559 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 560 { 561 int secbus; 562 int old_pribus, old_secbus, old_subbus; 563 int new_pribus, new_secbus, new_subbus; 564 int slot, func, maxfunc; 565 uint16_t vendor, device; 566 uint8_t brctl, command, hdrtype, subclass; 567 568 secbus = bus; 569 for (slot = 0; slot <= maxslot; slot++) { 570 maxfunc = 0; 571 for (func = 0; func <= maxfunc; func++) { 572 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 573 func, PCIR_HDRTYPE, 1); 574 575 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 576 continue; 577 578 if (func == 0 && (hdrtype & PCIM_MFDEV)) 579 maxfunc = PCI_FUNCMAX; 580 581 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 582 func, PCIR_VENDOR, 2); 583 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 584 func, PCIR_DEVICE, 2); 585 586 if (vendor == 0x1957 && device == 0x3fff) { 587 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 588 continue; 589 } 590 591 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 592 func, PCIR_COMMAND, 1); 593 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 594 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 595 PCIR_COMMAND, command, 1); 596 597 if (vendor == 0x1106) 598 fsl_pcib_init_via(sc, device, bus, slot, func); 599 600 /* 601 * Handle PCI-PCI bridges 602 */ 603 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 604 func, PCIR_SUBCLASS, 1); 605 606 /* Allow all DEVTYPE 1 devices */ 607 if (hdrtype != PCIM_HDRTYPE_BRIDGE) 608 continue; 609 610 brctl = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, 611 PCIR_BRIDGECTL_1, 1); 612 brctl |= PCIB_BCR_SECBUS_RESET; 613 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 614 PCIR_BRIDGECTL_1, brctl, 1); 615 DELAY(100000); 616 brctl &= ~PCIB_BCR_SECBUS_RESET; 617 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 618 PCIR_BRIDGECTL_1, brctl, 1); 619 DELAY(100000); 620 621 secbus++; 622 623 /* Read currect bus register configuration */ 624 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 625 slot, func, PCIR_PRIBUS_1, 1); 626 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 627 slot, func, PCIR_SECBUS_1, 1); 628 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 629 slot, func, PCIR_SUBBUS_1, 1); 630 631 if (bootverbose) 632 printf("PCI: reading firmware bus numbers for " 633 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 634 secbus, old_pribus, old_secbus, old_subbus); 635 636 new_pribus = bus; 637 new_secbus = secbus; 638 639 secbus = fsl_pcib_init(sc, secbus, 640 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 641 642 new_subbus = secbus; 643 644 if (bootverbose) 645 printf("PCI: translate firmware bus numbers " 646 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 647 secbus, old_pribus, old_secbus, old_subbus, 648 new_pribus, new_secbus, new_subbus); 649 650 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 651 PCIR_PRIBUS_1, new_pribus, 1); 652 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 653 PCIR_SECBUS_1, new_secbus, 1); 654 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 655 PCIR_SUBBUS_1, new_subbus, 1); 656 } 657 } 658 659 return (secbus); 660 } 661 662 static void 663 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 664 uint64_t size, uint64_t pci_start) 665 { 666 uint32_t attr, bar, tar; 667 668 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 669 670 switch (tgt) { 671 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 672 case OCP85XX_TGTIF_RAM1_85XX: 673 case OCP85XX_TGTIF_RAM1_QORIQ: 674 attr = 0xa0f55000 | (ffsl(size) - 2); 675 break; 676 default: 677 attr = 0; 678 break; 679 } 680 tar = start >> 12; 681 bar = pci_start >> 12; 682 683 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 684 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 685 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 686 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 687 } 688 689 static void 690 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 691 uint64_t size, uint64_t pci_start) 692 { 693 uint32_t attr, bar, tar; 694 695 switch (res) { 696 case SYS_RES_MEMORY: 697 attr = 0x80044000 | (ffsll(size) - 2); 698 break; 699 case SYS_RES_IOPORT: 700 attr = 0x80088000 | (ffsll(size) - 2); 701 break; 702 default: 703 attr = 0x0004401f; 704 break; 705 } 706 bar = start >> 12; 707 tar = pci_start >> 12; 708 709 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 710 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 711 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 712 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 713 } 714 715 716 static void 717 fsl_pcib_err_init(device_t dev) 718 { 719 struct fsl_pcib_softc *sc; 720 uint16_t sec_stat, dsr; 721 uint32_t dcr, err_en; 722 723 sc = device_get_softc(dev); 724 725 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 726 if (sec_stat) 727 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 728 if (sc->sc_pcie) { 729 /* Clear error bits */ 730 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 731 0xffffffff); 732 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 733 0xffffffff); 734 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 735 0xffffffff); 736 737 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 738 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 739 if (dsr) 740 fsl_pcib_cfgwrite(sc, 0, 0, 0, 741 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 742 0xffff, 2); 743 744 /* Enable all errors reporting */ 745 err_en = 0x00bfff00; 746 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 747 err_en); 748 749 /* Enable error reporting: URR, FER, NFER */ 750 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 751 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 752 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 753 PCIEM_CTL_NFER_ENABLE; 754 fsl_pcib_cfgwrite(sc, 0, 0, 0, 755 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 756 } 757 } 758 759 static int 760 fsl_pcib_detach(device_t dev) 761 { 762 763 if (mtx_initialized) { 764 mtx_destroy(&pcicfg_mtx); 765 mtx_initialized = 0; 766 } 767 return (bus_generic_detach(dev)); 768 } 769 770 static int 771 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 772 { 773 device_t dev; 774 int error, i, trgt; 775 776 dev = sc->sc_dev; 777 778 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 779 780 /* 781 * Configure LAW decode windows. 782 */ 783 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 784 &sc->sc_ioport_target); 785 if (error != 0) { 786 device_printf(dev, "could not retrieve PCI LAW target info\n"); 787 return (error); 788 } 789 790 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 791 switch (sc->pci_sc.sc_range[i].pci_hi & 792 OFW_PCI_PHYS_HI_SPACEMASK) { 793 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 794 continue; 795 case OFW_PCI_PHYS_HI_SPACE_IO: 796 trgt = sc->sc_ioport_target; 797 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 798 sc->pci_sc.sc_range[i].host, 799 sc->pci_sc.sc_range[i].size, 800 sc->pci_sc.sc_range[i].pci); 801 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 802 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 803 sc->pci_sc.sc_range[i].size - 1; 804 break; 805 case OFW_PCI_PHYS_HI_SPACE_MEM32: 806 case OFW_PCI_PHYS_HI_SPACE_MEM64: 807 trgt = sc->sc_iomem_target; 808 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 809 sc->pci_sc.sc_range[i].host, 810 sc->pci_sc.sc_range[i].size, 811 sc->pci_sc.sc_range[i].pci); 812 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 813 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 814 sc->pci_sc.sc_range[i].size - 1; 815 break; 816 default: 817 panic("Unknown range type %#x\n", 818 sc->pci_sc.sc_range[i].pci_hi & 819 OFW_PCI_PHYS_HI_SPACEMASK); 820 } 821 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 822 sc->pci_sc.sc_range[i].size); 823 if (error != 0) { 824 device_printf(dev, "could not program LAW for range " 825 "%d\n", i); 826 return (error); 827 } 828 } 829 830 /* 831 * Set outbout and inbound windows. 832 */ 833 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 834 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 835 836 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 837 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 838 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 839 2U * 1024U * 1024U * 1024U, 0); 840 841 return (0); 842 } 843