1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ktr.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/socket.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/queue.h> 55 #include <sys/rman.h> 56 #include <sys/endian.h> 57 #include <sys/vmem.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/ofw/ofw_pci.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofwpci.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 74 #include <machine/resource.h> 75 #include <machine/bus.h> 76 #include <machine/intr_machdep.h> 77 78 #include <powerpc/mpc85xx/mpc85xx.h> 79 80 #define REG_CFG_ADDR 0x0000 81 #define CONFIG_ACCESS_ENABLE 0x80000000 82 83 #define REG_CFG_DATA 0x0004 84 #define REG_INT_ACK 0x0008 85 86 #define REG_PEX_IP_BLK_REV1 0x0bf8 87 #define IP_MJ_M 0x0000ff00 88 #define IP_MJ_S 8 89 #define IP_MN_M 0x000000ff 90 #define IP_MN_S 0 91 92 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 93 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 94 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 95 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 96 97 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 98 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 99 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 100 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 101 #define PIWAR_EN 0x80000000 102 #define PIWAR_PF 0x40000000 103 #define PIWAR_TRGT_M 0x00f00000 104 #define PIWAR_TRGT_S 20 105 #define PIWAR_TRGT_CCSR 0xe 106 #define PIWAR_TRGT_LOCAL 0xf 107 108 #define REG_PEX_MES_DR 0x0020 109 #define REG_PEX_MES_IER 0x0028 110 #define REG_PEX_ERR_DR 0x0e00 111 #define REG_PEX_ERR_EN 0x0e08 112 113 #define REG_PEX_ERR_DR 0x0e00 114 #define REG_PEX_ERR_DR_ME 0x80000000 115 #define REG_PEX_ERR_DR_PCT 0x800000 116 #define REG_PEX_ERR_DR_PAT 0x400000 117 #define REG_PEX_ERR_DR_PCAC 0x200000 118 #define REG_PEX_ERR_DR_PNM 0x100000 119 #define REG_PEX_ERR_DR_CDNSC 0x80000 120 #define REG_PEX_ERR_DR_CRSNC 0x40000 121 #define REG_PEX_ERR_DR_ICCA 0x20000 122 #define REG_PEX_ERR_DR_IACA 0x10000 123 #define REG_PEX_ERR_DR_CRST 0x8000 124 #define REG_PEX_ERR_DR_MIS 0x4000 125 #define REG_PEX_ERR_DR_IOIS 0x2000 126 #define REG_PEX_ERR_DR_CIS 0x1000 127 #define REG_PEX_ERR_DR_CIEP 0x800 128 #define REG_PEX_ERR_DR_IOIEP 0x400 129 #define REG_PEX_ERR_DR_OAC 0x200 130 #define REG_PEX_ERR_DR_IOIA 0x100 131 #define REG_PEX_ERR_DR_IMBA 0x80 132 #define REG_PEX_ERR_DR_IIOBA 0x40 133 #define REG_PEX_ERR_DR_LDDE 0x20 134 #define REG_PEX_ERR_EN 0x0e08 135 136 #define PCIR_LTSSM 0x404 137 #define LTSSM_STAT_L0 0x16 138 139 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 140 141 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */ 142 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */ 143 144 struct fsl_pcib_softc { 145 struct ofw_pci_softc pci_sc; 146 device_t sc_dev; 147 struct mtx sc_cfg_mtx; 148 int sc_ip_maj; 149 int sc_ip_min; 150 151 int sc_iomem_target; 152 bus_addr_t sc_iomem_start, sc_iomem_end; 153 int sc_ioport_target; 154 bus_addr_t sc_ioport_start, sc_ioport_end; 155 156 struct resource *sc_res; 157 bus_space_handle_t sc_bsh; 158 bus_space_tag_t sc_bst; 159 int sc_rid; 160 161 struct resource *sc_irq_res; 162 void *sc_ih; 163 164 int sc_busnr; 165 int sc_pcie; 166 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 167 }; 168 169 struct fsl_pcib_err_dr { 170 const char *msg; 171 uint32_t err_dr_mask; 172 }; 173 174 struct fsl_msi_map { 175 SLIST_ENTRY(fsl_msi_map) slist; 176 uint32_t irq_base; 177 bus_addr_t target; 178 }; 179 180 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head); 181 182 static const struct fsl_pcib_err_dr pci_err[] = { 183 {"ME", REG_PEX_ERR_DR_ME}, 184 {"PCT", REG_PEX_ERR_DR_PCT}, 185 {"PAT", REG_PEX_ERR_DR_PAT}, 186 {"PCAC", REG_PEX_ERR_DR_PCAC}, 187 {"PNM", REG_PEX_ERR_DR_PNM}, 188 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 189 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 190 {"ICCA", REG_PEX_ERR_DR_ICCA}, 191 {"IACA", REG_PEX_ERR_DR_IACA}, 192 {"CRST", REG_PEX_ERR_DR_CRST}, 193 {"MIS", REG_PEX_ERR_DR_MIS}, 194 {"IOIS", REG_PEX_ERR_DR_IOIS}, 195 {"CIS", REG_PEX_ERR_DR_CIS}, 196 {"CIEP", REG_PEX_ERR_DR_CIEP}, 197 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 198 {"OAC", REG_PEX_ERR_DR_OAC}, 199 {"IOIA", REG_PEX_ERR_DR_IOIA}, 200 {"IMBA", REG_PEX_ERR_DR_IMBA}, 201 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 202 {"LDDE", REG_PEX_ERR_DR_LDDE} 203 }; 204 205 /* Local forward declerations. */ 206 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 207 u_int, int); 208 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 209 u_int, uint32_t, int); 210 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 211 static void fsl_pcib_err_init(device_t); 212 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 213 uint64_t, uint64_t); 214 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 215 uint64_t, uint64_t); 216 217 /* Forward declerations. */ 218 static int fsl_pcib_attach(device_t); 219 static int fsl_pcib_detach(device_t); 220 static int fsl_pcib_probe(device_t); 221 222 static int fsl_pcib_maxslots(device_t); 223 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 224 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 225 uint32_t, int); 226 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 227 int count, int maxcount, int *irqs); 228 static int fsl_pcib_release_msi(device_t dev, device_t child, 229 int count, int *irqs); 230 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq); 231 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq); 232 static int fsl_pcib_map_msi(device_t dev, device_t child, 233 int irq, uint64_t *addr, uint32_t *data); 234 235 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */ 236 237 /* 238 * Bus interface definitions. 239 */ 240 static device_method_t fsl_pcib_methods[] = { 241 /* Device interface */ 242 DEVMETHOD(device_probe, fsl_pcib_probe), 243 DEVMETHOD(device_attach, fsl_pcib_attach), 244 DEVMETHOD(device_detach, fsl_pcib_detach), 245 246 /* pcib interface */ 247 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 248 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 249 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 250 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi), 251 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi), 252 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix), 253 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix), 254 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi), 255 256 DEVMETHOD_END 257 }; 258 259 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 260 sizeof(struct fsl_pcib_softc), ofw_pcib_driver); 261 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS); 262 263 static void 264 fsl_pcib_err_intr(void *v) 265 { 266 struct fsl_pcib_softc *sc; 267 device_t dev; 268 uint32_t err_reg, clear_reg; 269 uint8_t i; 270 271 dev = (device_t)v; 272 sc = device_get_softc(dev); 273 274 clear_reg = 0; 275 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 276 277 /* Check which one error occurred */ 278 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 279 if (err_reg & pci_err[i].err_dr_mask) { 280 device_printf(dev, "PCI %d: report %s error\n", 281 device_get_unit(dev), pci_err[i].msg); 282 clear_reg |= pci_err[i].err_dr_mask; 283 } 284 } 285 286 /* Clear pending errors */ 287 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 288 } 289 290 static int 291 fsl_pcib_probe(device_t dev) 292 { 293 294 if (ofw_bus_get_type(dev) == NULL || 295 strcmp(ofw_bus_get_type(dev), "pci") != 0) 296 return (ENXIO); 297 298 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 299 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 300 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 301 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 302 ofw_bus_is_compatible(dev, "fsl,p5040-pcie") || 303 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 304 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.4") || 305 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 306 return (ENXIO); 307 308 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 309 return (BUS_PROBE_DEFAULT); 310 } 311 312 static int 313 fsl_pcib_attach(device_t dev) 314 { 315 struct fsl_pcib_softc *sc; 316 phandle_t node; 317 uint32_t cfgreg, brctl, ipreg; 318 int do_reset, error, rid; 319 uint8_t ltssm, capptr; 320 321 sc = device_get_softc(dev); 322 sc->sc_dev = dev; 323 324 sc->sc_rid = 0; 325 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 326 RF_ACTIVE); 327 if (sc->sc_res == NULL) { 328 device_printf(dev, "could not map I/O memory\n"); 329 return (ENXIO); 330 } 331 sc->sc_bst = rman_get_bustag(sc->sc_res); 332 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 333 sc->sc_busnr = 0; 334 335 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1); 336 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S; 337 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S; 338 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN); 339 340 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 341 if (cfgreg != 0x1057 && cfgreg != 0x1957) 342 goto err; 343 344 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 345 while (capptr != 0) { 346 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 347 switch (cfgreg & 0xff) { 348 case PCIY_PCIX: 349 break; 350 case PCIY_EXPRESS: 351 sc->sc_pcie = 1; 352 sc->sc_pcie_capreg = capptr; 353 break; 354 } 355 capptr = (cfgreg >> 8) & 0xff; 356 } 357 358 node = ofw_bus_get_node(dev); 359 360 /* 361 * Initialize generic OF PCI interface (ranges, etc.) 362 */ 363 364 error = ofw_pcib_init(dev); 365 if (error) 366 return (error); 367 368 /* 369 * Configure decode windows for PCI(E) access. 370 */ 371 if (fsl_pcib_decode_win(node, sc) != 0) 372 goto err; 373 374 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 375 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 376 PCIM_CMD_PORTEN; 377 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 378 379 do_reset = 0; 380 resource_int_value("pcib", device_get_unit(dev), "reset", &do_reset); 381 if (do_reset) { 382 /* Reset the bus. Needed for Radeon video cards. */ 383 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0, 384 PCIR_BRIDGECTL_1, 1); 385 brctl |= PCIB_BCR_SECBUS_RESET; 386 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 387 PCIR_BRIDGECTL_1, brctl, 1); 388 DELAY(100000); 389 brctl &= ~PCIB_BCR_SECBUS_RESET; 390 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 391 PCIR_BRIDGECTL_1, brctl, 1); 392 DELAY(100000); 393 } 394 395 if (sc->sc_pcie) { 396 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 397 if (ltssm < LTSSM_STAT_L0) { 398 if (bootverbose) 399 printf("PCI %d: no PCIE link, skipping\n", 400 device_get_unit(dev)); 401 return (0); 402 } 403 } 404 405 /* Allocate irq */ 406 rid = 0; 407 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 408 RF_ACTIVE | RF_SHAREABLE); 409 if (sc->sc_irq_res == NULL) { 410 error = fsl_pcib_detach(dev); 411 if (error != 0) { 412 device_printf(dev, 413 "Detach of the driver failed with error %d\n", 414 error); 415 } 416 return (ENXIO); 417 } 418 419 /* Setup interrupt handler */ 420 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 421 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih); 422 if (error != 0) { 423 device_printf(dev, "Could not setup irq, %d\n", error); 424 sc->sc_ih = NULL; 425 error = fsl_pcib_detach(dev); 426 if (error != 0) { 427 device_printf(dev, 428 "Detach of the driver failed with error %d\n", 429 error); 430 } 431 return (ENXIO); 432 } 433 434 fsl_pcib_err_init(dev); 435 436 return (ofw_pcib_attach(dev)); 437 438 err: 439 return (ENXIO); 440 } 441 442 static uint32_t 443 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 444 u_int reg, int bytes) 445 { 446 uint32_t addr, data; 447 448 addr = CONFIG_ACCESS_ENABLE; 449 addr |= (bus & 0xff) << 16; 450 addr |= (slot & 0x1f) << 11; 451 addr |= (func & 0x7) << 8; 452 addr |= reg & 0xfc; 453 if (sc->sc_pcie) 454 addr |= (reg & 0xf00) << 16; 455 456 mtx_lock_spin(&sc->sc_cfg_mtx); 457 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 458 459 switch (bytes) { 460 case 1: 461 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 462 REG_CFG_DATA + (reg & 3)); 463 break; 464 case 2: 465 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 466 REG_CFG_DATA + (reg & 2))); 467 break; 468 case 4: 469 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 470 REG_CFG_DATA)); 471 break; 472 default: 473 data = ~0; 474 break; 475 } 476 mtx_unlock_spin(&sc->sc_cfg_mtx); 477 return (data); 478 } 479 480 static void 481 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 482 u_int reg, uint32_t data, int bytes) 483 { 484 uint32_t addr; 485 486 addr = CONFIG_ACCESS_ENABLE; 487 addr |= (bus & 0xff) << 16; 488 addr |= (slot & 0x1f) << 11; 489 addr |= (func & 0x7) << 8; 490 addr |= reg & 0xfc; 491 if (sc->sc_pcie) 492 addr |= (reg & 0xf00) << 16; 493 494 mtx_lock_spin(&sc->sc_cfg_mtx); 495 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 496 497 switch (bytes) { 498 case 1: 499 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 500 REG_CFG_DATA + (reg & 3), data); 501 break; 502 case 2: 503 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 504 REG_CFG_DATA + (reg & 2), htole16(data)); 505 break; 506 case 4: 507 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 508 REG_CFG_DATA, htole32(data)); 509 break; 510 } 511 mtx_unlock_spin(&sc->sc_cfg_mtx); 512 } 513 514 #if 0 515 static void 516 dump(struct fsl_pcib_softc *sc) 517 { 518 unsigned int i; 519 520 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 521 for (i = 0; i < 5; i++) { 522 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 523 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 524 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 525 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 526 } 527 printf("\n"); 528 for (i = 1; i < 4; i++) { 529 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 530 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 531 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 532 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 533 } 534 printf("\n"); 535 #undef RD 536 537 for (i = 0; i < 0x48; i += 4) { 538 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 539 i, 4)); 540 } 541 } 542 #endif 543 544 static int 545 fsl_pcib_maxslots(device_t dev) 546 { 547 struct fsl_pcib_softc *sc = device_get_softc(dev); 548 549 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 550 } 551 552 static uint32_t 553 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 554 u_int reg, int bytes) 555 { 556 struct fsl_pcib_softc *sc = device_get_softc(dev); 557 558 if (bus == sc->sc_busnr && !sc->sc_pcie && 559 slot < PCI_SLOT_FIRST) 560 return (~0); 561 562 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 563 } 564 565 static void 566 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 567 u_int reg, uint32_t val, int bytes) 568 { 569 struct fsl_pcib_softc *sc = device_get_softc(dev); 570 571 if (bus == sc->sc_busnr && !sc->sc_pcie && 572 slot < PCI_SLOT_FIRST) 573 return; 574 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 575 } 576 577 static void 578 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 579 uint64_t size, uint64_t pci_start) 580 { 581 uint32_t attr, bar, tar; 582 583 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 584 585 attr = PIWAR_EN; 586 587 switch (tgt) { 588 case -1: 589 attr &= ~PIWAR_EN; 590 break; 591 case PIWAR_TRGT_LOCAL: 592 attr |= (ffsl(size) - 2); 593 default: 594 attr |= (tgt << PIWAR_TRGT_S); 595 break; 596 } 597 tar = start >> 12; 598 bar = pci_start >> 12; 599 600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 601 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 602 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 603 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 604 } 605 606 static void 607 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 608 uint64_t size, uint64_t pci_start) 609 { 610 uint32_t attr, bar, tar; 611 612 switch (res) { 613 case SYS_RES_MEMORY: 614 attr = 0x80044000 | (ffsll(size) - 2); 615 break; 616 case SYS_RES_IOPORT: 617 attr = 0x80088000 | (ffsll(size) - 2); 618 break; 619 default: 620 attr = 0x0004401f; 621 break; 622 } 623 bar = start >> 12; 624 tar = pci_start >> 12; 625 626 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 627 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 628 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 629 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 630 } 631 632 static void 633 fsl_pcib_err_init(device_t dev) 634 { 635 struct fsl_pcib_softc *sc; 636 uint16_t sec_stat, dsr; 637 uint32_t dcr, err_en; 638 639 sc = device_get_softc(dev); 640 641 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 642 if (sec_stat) 643 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 644 if (sc->sc_pcie) { 645 /* Clear error bits */ 646 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 647 0xffffffff); 648 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 649 0xffffffff); 650 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 651 0xffffffff); 652 653 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 654 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 655 if (dsr) 656 fsl_pcib_cfgwrite(sc, 0, 0, 0, 657 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 658 0xffff, 2); 659 660 /* Enable all errors reporting */ 661 err_en = 0x00bfff00; 662 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 663 err_en); 664 665 /* Enable error reporting: URR, FER, NFER */ 666 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 667 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 668 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 669 PCIEM_CTL_NFER_ENABLE; 670 fsl_pcib_cfgwrite(sc, 0, 0, 0, 671 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 672 } 673 } 674 675 static int 676 fsl_pcib_detach(device_t dev) 677 { 678 struct fsl_pcib_softc *sc; 679 680 sc = device_get_softc(dev); 681 682 mtx_destroy(&sc->sc_cfg_mtx); 683 684 return (bus_generic_detach(dev)); 685 } 686 687 static int 688 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 689 { 690 device_t dev; 691 int error, i, trgt; 692 693 dev = sc->sc_dev; 694 695 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 696 697 /* 698 * Configure LAW decode windows. 699 */ 700 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 701 &sc->sc_ioport_target); 702 if (error != 0) { 703 device_printf(dev, "could not retrieve PCI LAW target info\n"); 704 return (error); 705 } 706 707 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 708 switch (sc->pci_sc.sc_range[i].pci_hi & 709 OFW_PCI_PHYS_HI_SPACEMASK) { 710 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 711 continue; 712 case OFW_PCI_PHYS_HI_SPACE_IO: 713 trgt = sc->sc_ioport_target; 714 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 715 sc->pci_sc.sc_range[i].host, 716 sc->pci_sc.sc_range[i].size, 717 sc->pci_sc.sc_range[i].pci); 718 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 719 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 720 sc->pci_sc.sc_range[i].size - 1; 721 break; 722 case OFW_PCI_PHYS_HI_SPACE_MEM32: 723 case OFW_PCI_PHYS_HI_SPACE_MEM64: 724 trgt = sc->sc_iomem_target; 725 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 726 sc->pci_sc.sc_range[i].host, 727 sc->pci_sc.sc_range[i].size, 728 sc->pci_sc.sc_range[i].pci); 729 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 730 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 731 sc->pci_sc.sc_range[i].size - 1; 732 break; 733 default: 734 panic("Unknown range type %#x\n", 735 sc->pci_sc.sc_range[i].pci_hi & 736 OFW_PCI_PHYS_HI_SPACEMASK); 737 } 738 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 739 sc->pci_sc.sc_range[i].size); 740 if (error != 0) { 741 device_printf(dev, "could not program LAW for range " 742 "%d\n", i); 743 return (error); 744 } 745 } 746 747 /* 748 * Set outbout and inbound windows. 749 */ 750 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 751 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 752 753 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 754 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 755 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0, 756 ptoa(Maxmem), 0); 757 758 /* Direct-map the CCSR for MSIs. */ 759 /* Freescale PCIe 2.x has a dedicated MSI window. */ 760 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */ 761 if (sc->sc_ip_maj >= 2) 762 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa, 763 ccsrbar_size, ccsrbar_pa); 764 else 765 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa, 766 ccsrbar_size, ccsrbar_pa); 767 768 return (0); 769 } 770 771 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 772 int count, int maxcount, int *irqs) 773 { 774 vmem_addr_t start; 775 int err, i; 776 777 if (msi_vmem == NULL) 778 return (ENODEV); 779 780 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0, 781 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 782 783 if (err) 784 return (err); 785 786 for (i = 0; i < count; i++) 787 irqs[i] = start + i; 788 789 return (0); 790 } 791 792 static int fsl_pcib_release_msi(device_t dev, device_t child, 793 int count, int *irqs) 794 { 795 if (msi_vmem == NULL) 796 return (ENODEV); 797 798 vmem_xfree(msi_vmem, irqs[0], count); 799 return (0); 800 } 801 802 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq) 803 { 804 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq)); 805 } 806 807 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq) 808 { 809 return (fsl_pcib_release_msi(dev, child, 1, &irq)); 810 } 811 812 static int fsl_pcib_map_msi(device_t dev, device_t child, 813 int irq, uint64_t *addr, uint32_t *data) 814 { 815 struct fsl_msi_map *mp; 816 817 SLIST_FOREACH(mp, &fsl_msis, slist) { 818 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS) 819 break; 820 } 821 822 if (mp == NULL) 823 return (ENODEV); 824 825 *data = (irq & 255); 826 *addr = ccsrbar_pa + mp->target; 827 828 return (0); 829 } 830 831 /* 832 * Linux device trees put the msi@<x> as children of the SoC, with ranges based 833 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between 834 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC 835 * driver just to allocate a subregion for a sibling driver). This driver will 836 * use ccsr_write() and ccsr_read() instead. 837 */ 838 839 #define FSL_NUM_IRQS 8 840 #define FSL_NUM_MSI_PER_IRQ 32 841 #define FSL_MSI_TARGET 0x140 842 843 struct fsl_msi_softc { 844 vm_offset_t sc_base; 845 vm_offset_t sc_target; 846 int sc_msi_base_irq; 847 struct fsl_msi_map sc_map; 848 struct fsl_msi_irq { 849 /* This struct gets passed as the filter private data. */ 850 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */ 851 struct resource *res; 852 int irq; 853 void *cookie; 854 int vectors[FSL_NUM_MSI_PER_IRQ]; 855 vm_offset_t reg; 856 } sc_msi_irq[FSL_NUM_IRQS]; 857 }; 858 859 static int 860 fsl_msi_intr_filter(void *priv) 861 { 862 struct fsl_msi_irq *data = priv; 863 uint32_t reg; 864 int i; 865 866 reg = ccsr_read4(ccsrbar_va + data->reg); 867 i = 0; 868 while (reg != 0) { 869 if (reg & 1) 870 powerpc_dispatch_intr(data->vectors[i], NULL); 871 reg >>= 1; 872 i++; 873 } 874 875 return (FILTER_HANDLED); 876 } 877 878 static int 879 fsl_msi_probe(device_t dev) 880 { 881 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi")) 882 return (ENXIO); 883 884 device_set_desc(dev, "Freescale MSI"); 885 886 return (BUS_PROBE_DEFAULT); 887 } 888 889 static int 890 fsl_msi_attach(device_t dev) 891 { 892 struct fsl_msi_softc *sc; 893 struct fsl_msi_irq *irq; 894 int i; 895 896 sc = device_get_softc(dev); 897 898 if (msi_vmem == NULL) 899 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK); 900 901 /* Manually play with resource entries. */ 902 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); 903 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1); 904 905 if (sc->sc_map.target == 0) 906 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET; 907 908 for (i = 0; i < FSL_NUM_IRQS; i++) { 909 irq = &sc->sc_msi_irq[i]; 910 irq->irq = i; 911 irq->reg = sc->sc_base + 16 * i; 912 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 913 &irq->irq, RF_ACTIVE); 914 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE, 915 fsl_msi_intr_filter, NULL, irq, &irq->cookie); 916 } 917 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev), 918 FSL_NUM_MSIS, 0, 0); 919 920 /* Let vmem and the IRQ subsystem work their magic for allocations. */ 921 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK); 922 923 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist); 924 925 return (0); 926 } 927 928 static void 929 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv) 930 { 931 struct fsl_msi_softc *sc; 932 struct fsl_msi_irq *irqd; 933 934 sc = device_get_softc(dev); 935 936 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ]; 937 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector; 938 } 939 940 static device_method_t fsl_msi_methods[] = { 941 DEVMETHOD(device_probe, fsl_msi_probe), 942 DEVMETHOD(device_attach, fsl_msi_attach), 943 944 DEVMETHOD(pic_enable, fsl_msi_enable), 945 DEVMETHOD_END 946 }; 947 948 static driver_t fsl_msi_driver = { 949 "fsl_msi", 950 fsl_msi_methods, 951 sizeof(struct fsl_msi_softc) 952 }; 953 954 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0, 955 BUS_PASS_INTERRUPT + 1); 956