1 /*- 2 * Copyright 2006-2007 by Juniper Networks. 3 * Copyright 2008 Semihalf. 4 * Copyright 2010 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Semihalf 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ktr.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/socket.h> 48 #include <sys/queue.h> 49 #include <sys/bus.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcib_private.h> 64 65 #include <powerpc/ofw/ofw_pci.h> 66 67 #include "ofw_bus_if.h" 68 #include "pcib_if.h" 69 70 #include <machine/resource.h> 71 #include <machine/bus.h> 72 #include <machine/intr_machdep.h> 73 74 #include <powerpc/mpc85xx/mpc85xx.h> 75 76 #define REG_CFG_ADDR 0x0000 77 #define CONFIG_ACCESS_ENABLE 0x80000000 78 79 #define REG_CFG_DATA 0x0004 80 #define REG_INT_ACK 0x0008 81 82 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 83 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 84 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 85 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 86 87 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 88 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 89 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 90 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 91 92 #define REG_PEX_MES_DR 0x0020 93 #define REG_PEX_MES_IER 0x0028 94 #define REG_PEX_ERR_DR 0x0e00 95 #define REG_PEX_ERR_EN 0x0e08 96 97 #define PCIR_LTSSM 0x404 98 #define LTSSM_STAT_L0 0x16 99 100 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 101 102 struct fsl_pcib_softc { 103 struct ofw_pci_softc pci_sc; 104 device_t sc_dev; 105 106 int sc_iomem_target; 107 bus_addr_t sc_iomem_alloc, sc_iomem_start, sc_iomem_end; 108 int sc_ioport_target; 109 bus_addr_t sc_ioport_alloc, sc_ioport_start, sc_ioport_end; 110 111 struct resource *sc_res; 112 bus_space_handle_t sc_bsh; 113 bus_space_tag_t sc_bst; 114 int sc_rid; 115 116 int sc_busnr; 117 int sc_pcie; 118 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 119 120 /* Devices that need special attention. */ 121 int sc_devfn_tundra; 122 int sc_devfn_via_ide; 123 }; 124 125 /* Local forward declerations. */ 126 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 127 u_int, int); 128 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 129 u_int, uint32_t, int); 130 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 131 static void fsl_pcib_err_init(device_t); 132 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long, 133 u_long, u_long); 134 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 135 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long, 136 u_long, u_long); 137 138 /* Forward declerations. */ 139 static int fsl_pcib_attach(device_t); 140 static int fsl_pcib_detach(device_t); 141 static int fsl_pcib_probe(device_t); 142 143 static int fsl_pcib_maxslots(device_t); 144 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 145 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 146 uint32_t, int); 147 148 /* Configuration r/w mutex. */ 149 struct mtx pcicfg_mtx; 150 static int mtx_initialized = 0; 151 152 /* 153 * Bus interface definitions. 154 */ 155 static device_method_t fsl_pcib_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, fsl_pcib_probe), 158 DEVMETHOD(device_attach, fsl_pcib_attach), 159 DEVMETHOD(device_detach, fsl_pcib_detach), 160 161 /* pcib interface */ 162 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 163 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 164 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 165 166 DEVMETHOD_END 167 }; 168 169 static devclass_t fsl_pcib_devclass; 170 171 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 172 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 173 DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0); 174 175 static int 176 fsl_pcib_probe(device_t dev) 177 { 178 179 if (ofw_bus_get_type(dev) == NULL || 180 strcmp(ofw_bus_get_type(dev), "pci") != 0) 181 return (ENXIO); 182 183 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 184 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 185 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 186 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 187 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 188 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 189 return (ENXIO); 190 191 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 192 return (BUS_PROBE_DEFAULT); 193 } 194 195 static int 196 fsl_pcib_attach(device_t dev) 197 { 198 struct fsl_pcib_softc *sc; 199 phandle_t node; 200 uint32_t cfgreg; 201 int maxslot, error; 202 uint8_t ltssm, capptr; 203 204 sc = device_get_softc(dev); 205 sc->sc_dev = dev; 206 207 sc->sc_rid = 0; 208 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 209 RF_ACTIVE); 210 if (sc->sc_res == NULL) { 211 device_printf(dev, "could not map I/O memory\n"); 212 return (ENXIO); 213 } 214 sc->sc_bst = rman_get_bustag(sc->sc_res); 215 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 216 sc->sc_busnr = 0; 217 218 if (!mtx_initialized) { 219 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 220 mtx_initialized = 1; 221 } 222 223 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 224 if (cfgreg != 0x1057 && cfgreg != 0x1957) 225 goto err; 226 227 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 228 while (capptr != 0) { 229 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 230 switch (cfgreg & 0xff) { 231 case PCIY_PCIX: 232 break; 233 case PCIY_EXPRESS: 234 sc->sc_pcie = 1; 235 sc->sc_pcie_capreg = capptr; 236 break; 237 } 238 capptr = (cfgreg >> 8) & 0xff; 239 } 240 241 node = ofw_bus_get_node(dev); 242 243 /* 244 * Initialize generic OF PCI interface (ranges, etc.) 245 */ 246 247 error = ofw_pci_init(dev); 248 if (error) 249 return (error); 250 251 /* 252 * Configure decode windows for PCI(E) access. 253 */ 254 if (fsl_pcib_decode_win(node, sc) != 0) 255 goto err; 256 257 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 258 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 259 PCIM_CMD_PORTEN; 260 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 261 262 sc->sc_devfn_tundra = -1; 263 sc->sc_devfn_via_ide = -1; 264 265 266 /* 267 * Scan bus using firmware configured, 0 based bus numbering. 268 */ 269 sc->sc_busnr = 0; 270 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 271 sc->sc_busnr = fsl_pcib_init(sc, sc->sc_busnr, maxslot); 272 273 if (sc->sc_pcie) { 274 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 275 if (ltssm < LTSSM_STAT_L0) { 276 if (bootverbose) 277 printf("PCI %d: no PCIE link, skipping\n", 278 device_get_unit(dev)); 279 return (0); 280 } 281 } 282 283 fsl_pcib_err_init(dev); 284 285 return (ofw_pci_attach(dev)); 286 287 err: 288 return (ENXIO); 289 } 290 291 static uint32_t 292 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 293 u_int reg, int bytes) 294 { 295 uint32_t addr, data; 296 297 if (bus == sc->sc_busnr - 1) 298 bus = 0; 299 300 addr = CONFIG_ACCESS_ENABLE; 301 addr |= (bus & 0xff) << 16; 302 addr |= (slot & 0x1f) << 11; 303 addr |= (func & 0x7) << 8; 304 addr |= reg & 0xfc; 305 if (sc->sc_pcie) 306 addr |= (reg & 0xf00) << 16; 307 308 mtx_lock_spin(&pcicfg_mtx); 309 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 310 311 switch (bytes) { 312 case 1: 313 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 314 REG_CFG_DATA + (reg & 3)); 315 break; 316 case 2: 317 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 318 REG_CFG_DATA + (reg & 2))); 319 break; 320 case 4: 321 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 322 REG_CFG_DATA)); 323 break; 324 default: 325 data = ~0; 326 break; 327 } 328 mtx_unlock_spin(&pcicfg_mtx); 329 return (data); 330 } 331 332 static void 333 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 334 u_int reg, uint32_t data, int bytes) 335 { 336 uint32_t addr; 337 338 if (bus == sc->sc_busnr - 1) 339 bus = 0; 340 341 addr = CONFIG_ACCESS_ENABLE; 342 addr |= (bus & 0xff) << 16; 343 addr |= (slot & 0x1f) << 11; 344 addr |= (func & 0x7) << 8; 345 addr |= reg & 0xfc; 346 if (sc->sc_pcie) 347 addr |= (reg & 0xf00) << 16; 348 349 mtx_lock_spin(&pcicfg_mtx); 350 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 351 352 switch (bytes) { 353 case 1: 354 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 355 REG_CFG_DATA + (reg & 3), data); 356 break; 357 case 2: 358 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 359 REG_CFG_DATA + (reg & 2), htole16(data)); 360 break; 361 case 4: 362 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 363 REG_CFG_DATA, htole32(data)); 364 break; 365 } 366 mtx_unlock_spin(&pcicfg_mtx); 367 } 368 369 #if 0 370 static void 371 dump(struct fsl_pcib_softc *sc) 372 { 373 unsigned int i; 374 375 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 376 for (i = 0; i < 5; i++) { 377 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 378 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 379 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 380 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 381 } 382 printf("\n"); 383 for (i = 1; i < 4; i++) { 384 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 385 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 386 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 387 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 388 } 389 printf("\n"); 390 #undef RD 391 392 for (i = 0; i < 0x48; i += 4) { 393 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 394 i, 4)); 395 } 396 } 397 #endif 398 399 static int 400 fsl_pcib_maxslots(device_t dev) 401 { 402 struct fsl_pcib_softc *sc = device_get_softc(dev); 403 404 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 405 } 406 407 static uint32_t 408 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 409 u_int reg, int bytes) 410 { 411 struct fsl_pcib_softc *sc = device_get_softc(dev); 412 u_int devfn; 413 414 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 415 return (~0); 416 devfn = DEVFN(bus, slot, func); 417 if (devfn == sc->sc_devfn_tundra) 418 return (~0); 419 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 420 return (1); 421 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 422 } 423 424 static void 425 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 426 u_int reg, uint32_t val, int bytes) 427 { 428 struct fsl_pcib_softc *sc = device_get_softc(dev); 429 430 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 431 return; 432 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 433 } 434 435 static void 436 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 437 int slot, int fn) 438 { 439 440 if (device == 0x0686) { 441 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 442 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 443 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 444 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 445 } else if (device == 0x0571) { 446 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 447 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 448 } 449 } 450 451 static int 452 fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func, 453 int barno) 454 { 455 bus_addr_t *allocp; 456 uint32_t addr, mask, size; 457 int reg, width; 458 459 reg = PCIR_BAR(barno); 460 461 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) { 462 switch (barno) { 463 case 0: addr = 0x1f0; break; 464 case 1: addr = 0x3f4; break; 465 case 2: addr = 0x170; break; 466 case 3: addr = 0x374; break; 467 case 4: addr = 0xcc0; break; 468 default: return (1); 469 } 470 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 471 return (1); 472 } 473 474 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 475 size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 476 if (size == 0) 477 return (1); 478 width = ((size & 7) == 4) ? 2 : 1; 479 480 if (size & 1) { /* I/O port */ 481 allocp = &sc->sc_ioport_alloc; 482 size &= ~3; 483 if ((size & 0xffff0000) == 0) 484 size |= 0xffff0000; 485 } else { /* memory */ 486 allocp = &sc->sc_iomem_alloc; 487 size &= ~15; 488 } 489 mask = ~size; 490 size = mask + 1; 491 /* Sanity check (must be a power of 2). */ 492 if (size & mask) 493 return (width); 494 495 addr = (*allocp + mask) & ~mask; 496 *allocp = addr + size; 497 498 if (bootverbose) 499 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n", 500 device_get_unit(sc->sc_dev), bus, slot, func, reg, 501 size, addr); 502 503 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 504 if (width == 2) 505 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 506 0, 4); 507 return (width); 508 } 509 510 static int 511 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 512 { 513 int secbus; 514 int old_pribus, old_secbus, old_subbus; 515 int new_pribus, new_secbus, new_subbus; 516 int slot, func, maxfunc; 517 int bar, maxbar; 518 uint16_t vendor, device; 519 uint8_t command, hdrtype, class, subclass; 520 521 secbus = bus; 522 for (slot = 0; slot <= maxslot; slot++) { 523 maxfunc = 0; 524 for (func = 0; func <= maxfunc; func++) { 525 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 526 func, PCIR_HDRTYPE, 1); 527 528 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 529 continue; 530 531 if (func == 0 && (hdrtype & PCIM_MFDEV)) 532 maxfunc = PCI_FUNCMAX; 533 534 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 535 func, PCIR_VENDOR, 2); 536 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 537 func, PCIR_DEVICE, 2); 538 539 if (vendor == 0x1957 && device == 0x3fff) { 540 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 541 continue; 542 } 543 544 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 545 func, PCIR_COMMAND, 1); 546 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 547 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 548 PCIR_COMMAND, command, 1); 549 550 if (vendor == 0x1106) 551 fsl_pcib_init_via(sc, device, bus, slot, func); 552 553 /* Program the base address registers. */ 554 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6; 555 bar = 0; 556 while (bar < maxbar) 557 bar += fsl_pcib_init_bar(sc, bus, slot, func, 558 bar); 559 560 /* Put a placeholder interrupt value */ 561 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 562 PCIR_INTLINE, PCI_INVALID_IRQ, 1); 563 564 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 565 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 566 PCIR_COMMAND, command, 1); 567 568 /* 569 * Handle PCI-PCI bridges 570 */ 571 class = fsl_pcib_read_config(sc->sc_dev, bus, slot, 572 func, PCIR_CLASS, 1); 573 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 574 func, PCIR_SUBCLASS, 1); 575 576 /* Allow all DEVTYPE 1 devices */ 577 if (hdrtype != PCIM_HDRTYPE_BRIDGE) 578 continue; 579 580 secbus++; 581 582 /* Program I/O decoder. */ 583 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 584 PCIR_IOBASEL_1, sc->sc_ioport_start >> 8, 1); 585 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 586 PCIR_IOLIMITL_1, sc->sc_ioport_end >> 8, 1); 587 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 588 PCIR_IOBASEH_1, sc->sc_ioport_start >> 16, 2); 589 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 590 PCIR_IOLIMITH_1, sc->sc_ioport_end >> 16, 2); 591 592 /* Program (non-prefetchable) memory decoder. */ 593 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 594 PCIR_MEMBASE_1, sc->sc_iomem_start >> 16, 2); 595 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 596 PCIR_MEMLIMIT_1, sc->sc_iomem_end >> 16, 2); 597 598 /* Program prefetchable memory decoder. */ 599 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 600 PCIR_PMBASEL_1, 0x0010, 2); 601 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 602 PCIR_PMLIMITL_1, 0x000f, 2); 603 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 604 PCIR_PMBASEH_1, 0x00000000, 4); 605 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 606 PCIR_PMLIMITH_1, 0x00000000, 4); 607 608 /* Read currect bus register configuration */ 609 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 610 slot, func, PCIR_PRIBUS_1, 1); 611 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 612 slot, func, PCIR_SECBUS_1, 1); 613 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 614 slot, func, PCIR_SUBBUS_1, 1); 615 616 if (bootverbose) 617 printf("PCI: reading firmware bus numbers for " 618 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 619 secbus, old_pribus, old_secbus, old_subbus); 620 621 new_pribus = bus; 622 new_secbus = secbus; 623 624 secbus = fsl_pcib_init(sc, secbus, 625 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 626 627 new_subbus = secbus; 628 629 if (bootverbose) 630 printf("PCI: translate firmware bus numbers " 631 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 632 secbus, old_pribus, old_secbus, old_subbus, 633 new_pribus, new_secbus, new_subbus); 634 635 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 636 PCIR_PRIBUS_1, new_pribus, 1); 637 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 638 PCIR_SECBUS_1, new_secbus, 1); 639 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 640 PCIR_SUBBUS_1, new_subbus, 1); 641 } 642 } 643 644 return (secbus); 645 } 646 647 static void 648 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start, 649 u_long size, u_long pci_start) 650 { 651 uint32_t attr, bar, tar; 652 653 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 654 655 switch (tgt) { 656 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 657 case OCP85XX_TGTIF_RAM1: 658 attr = 0xa0f55000 | (ffsl(size) - 2); 659 break; 660 default: 661 attr = 0; 662 break; 663 } 664 tar = start >> 12; 665 bar = pci_start >> 12; 666 667 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 668 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 669 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 670 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 671 } 672 673 static void 674 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start, 675 u_long size, u_long pci_start) 676 { 677 uint32_t attr, bar, tar; 678 679 switch (res) { 680 case SYS_RES_MEMORY: 681 attr = 0x80044000 | (ffsl(size) - 2); 682 break; 683 case SYS_RES_IOPORT: 684 attr = 0x80088000 | (ffsl(size) - 2); 685 break; 686 default: 687 attr = 0x0004401f; 688 break; 689 } 690 bar = start >> 12; 691 tar = pci_start >> 12; 692 693 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 694 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 695 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 696 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 697 } 698 699 700 static void 701 fsl_pcib_err_init(device_t dev) 702 { 703 struct fsl_pcib_softc *sc; 704 uint16_t sec_stat, dsr; 705 uint32_t dcr, err_en; 706 707 sc = device_get_softc(dev); 708 709 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 710 if (sec_stat) 711 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 712 if (sc->sc_pcie) { 713 /* Clear error bits */ 714 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 715 0xffffffff); 716 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 717 0xffffffff); 718 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 719 0xffffffff); 720 721 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 722 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 723 if (dsr) 724 fsl_pcib_cfgwrite(sc, 0, 0, 0, 725 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 726 0xffff, 2); 727 728 /* Enable all errors reporting */ 729 err_en = 0x00bfff00; 730 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 731 err_en); 732 733 /* Enable error reporting: URR, FER, NFER */ 734 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 735 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 736 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 737 PCIEM_CTL_NFER_ENABLE; 738 fsl_pcib_cfgwrite(sc, 0, 0, 0, 739 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 740 } 741 } 742 743 static int 744 fsl_pcib_detach(device_t dev) 745 { 746 747 if (mtx_initialized) { 748 mtx_destroy(&pcicfg_mtx); 749 mtx_initialized = 0; 750 } 751 return (bus_generic_detach(dev)); 752 } 753 754 static int 755 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 756 { 757 device_t dev; 758 int error, i, trgt; 759 760 dev = sc->sc_dev; 761 762 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 763 764 /* 765 * Configure LAW decode windows. 766 */ 767 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 768 &sc->sc_ioport_target); 769 if (error != 0) { 770 device_printf(dev, "could not retrieve PCI LAW target info\n"); 771 return (error); 772 } 773 774 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 775 switch (sc->pci_sc.sc_range[i].pci_hi & 776 OFW_PCI_PHYS_HI_SPACEMASK) { 777 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 778 continue; 779 case OFW_PCI_PHYS_HI_SPACE_IO: 780 trgt = sc->sc_ioport_target; 781 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 782 sc->pci_sc.sc_range[i].host, 783 sc->pci_sc.sc_range[i].size, 784 sc->pci_sc.sc_range[i].pci); 785 sc->sc_ioport_start = sc->pci_sc.sc_range[i].host; 786 sc->sc_ioport_end = sc->pci_sc.sc_range[i].host + 787 sc->pci_sc.sc_range[i].size; 788 sc->sc_ioport_alloc = 0x1000 + sc->pci_sc.sc_range[i].pci; 789 break; 790 case OFW_PCI_PHYS_HI_SPACE_MEM32: 791 case OFW_PCI_PHYS_HI_SPACE_MEM64: 792 trgt = sc->sc_iomem_target; 793 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 794 sc->pci_sc.sc_range[i].host, 795 sc->pci_sc.sc_range[i].size, 796 sc->pci_sc.sc_range[i].pci); 797 sc->sc_iomem_start = sc->pci_sc.sc_range[i].host; 798 sc->sc_iomem_end = sc->pci_sc.sc_range[i].host + 799 sc->pci_sc.sc_range[i].size; 800 sc->sc_iomem_alloc = sc->pci_sc.sc_range[i].pci; 801 break; 802 default: 803 panic("Unknown range type %#x\n", 804 sc->pci_sc.sc_range[i].pci_hi & 805 OFW_PCI_PHYS_HI_SPACEMASK); 806 } 807 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 808 sc->pci_sc.sc_range[i].size); 809 if (error != 0) { 810 device_printf(dev, "could not program LAW for range " 811 "%d\n", i); 812 return (error); 813 } 814 } 815 816 /* 817 * Set outbout and inbound windows. 818 */ 819 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 820 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 821 822 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 823 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 824 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 825 2U * 1024U * 1024U * 1024U, 0); 826 827 return (0); 828 } 829