1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ktr.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/socket.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/queue.h> 55 #include <sys/rman.h> 56 #include <sys/endian.h> 57 #include <sys/vmem.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/ofw/ofw_pci.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofwpci.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 74 #include <machine/resource.h> 75 #include <machine/bus.h> 76 #include <machine/intr_machdep.h> 77 78 #include <powerpc/mpc85xx/mpc85xx.h> 79 80 #define REG_CFG_ADDR 0x0000 81 #define CONFIG_ACCESS_ENABLE 0x80000000 82 83 #define REG_CFG_DATA 0x0004 84 #define REG_INT_ACK 0x0008 85 86 #define REG_PEX_IP_BLK_REV1 0x0bf8 87 #define IP_MJ_M 0x0000ff00 88 #define IP_MJ_S 8 89 #define IP_MN_M 0x000000ff 90 #define IP_MN_S 0 91 92 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 93 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 94 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 95 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 96 97 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 98 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 99 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 100 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 101 #define PIWAR_EN 0x80000000 102 #define PIWAR_PF 0x40000000 103 #define PIWAR_TRGT_M 0x00f00000 104 #define PIWAR_TRGT_S 20 105 #define PIWAR_TRGT_CCSR 0xe 106 #define PIWAR_TRGT_LOCAL 0xf 107 108 #define REG_PEX_MES_DR 0x0020 109 #define REG_PEX_MES_IER 0x0028 110 #define REG_PEX_ERR_DR 0x0e00 111 #define REG_PEX_ERR_EN 0x0e08 112 113 #define REG_PEX_ERR_DR 0x0e00 114 #define REG_PEX_ERR_DR_ME 0x80000000 115 #define REG_PEX_ERR_DR_PCT 0x800000 116 #define REG_PEX_ERR_DR_PAT 0x400000 117 #define REG_PEX_ERR_DR_PCAC 0x200000 118 #define REG_PEX_ERR_DR_PNM 0x100000 119 #define REG_PEX_ERR_DR_CDNSC 0x80000 120 #define REG_PEX_ERR_DR_CRSNC 0x40000 121 #define REG_PEX_ERR_DR_ICCA 0x20000 122 #define REG_PEX_ERR_DR_IACA 0x10000 123 #define REG_PEX_ERR_DR_CRST 0x8000 124 #define REG_PEX_ERR_DR_MIS 0x4000 125 #define REG_PEX_ERR_DR_IOIS 0x2000 126 #define REG_PEX_ERR_DR_CIS 0x1000 127 #define REG_PEX_ERR_DR_CIEP 0x800 128 #define REG_PEX_ERR_DR_IOIEP 0x400 129 #define REG_PEX_ERR_DR_OAC 0x200 130 #define REG_PEX_ERR_DR_IOIA 0x100 131 #define REG_PEX_ERR_DR_IMBA 0x80 132 #define REG_PEX_ERR_DR_IIOBA 0x40 133 #define REG_PEX_ERR_DR_LDDE 0x20 134 #define REG_PEX_ERR_EN 0x0e08 135 136 #define PCIR_LTSSM 0x404 137 #define LTSSM_STAT_L0 0x16 138 139 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 140 141 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */ 142 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */ 143 144 struct fsl_pcib_softc { 145 struct ofw_pci_softc pci_sc; 146 device_t sc_dev; 147 struct mtx sc_cfg_mtx; 148 int sc_ip_maj; 149 int sc_ip_min; 150 151 int sc_iomem_target; 152 bus_addr_t sc_iomem_start, sc_iomem_end; 153 int sc_ioport_target; 154 bus_addr_t sc_ioport_start, sc_ioport_end; 155 156 struct resource *sc_res; 157 bus_space_handle_t sc_bsh; 158 bus_space_tag_t sc_bst; 159 int sc_rid; 160 161 struct resource *sc_irq_res; 162 void *sc_ih; 163 164 int sc_busnr; 165 int sc_pcie; 166 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 167 }; 168 169 struct fsl_pcib_err_dr { 170 const char *msg; 171 uint32_t err_dr_mask; 172 }; 173 174 struct fsl_msi_map { 175 SLIST_ENTRY(fsl_msi_map) slist; 176 uint32_t irq_base; 177 bus_addr_t target; 178 }; 179 180 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head); 181 182 static const struct fsl_pcib_err_dr pci_err[] = { 183 {"ME", REG_PEX_ERR_DR_ME}, 184 {"PCT", REG_PEX_ERR_DR_PCT}, 185 {"PAT", REG_PEX_ERR_DR_PAT}, 186 {"PCAC", REG_PEX_ERR_DR_PCAC}, 187 {"PNM", REG_PEX_ERR_DR_PNM}, 188 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 189 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 190 {"ICCA", REG_PEX_ERR_DR_ICCA}, 191 {"IACA", REG_PEX_ERR_DR_IACA}, 192 {"CRST", REG_PEX_ERR_DR_CRST}, 193 {"MIS", REG_PEX_ERR_DR_MIS}, 194 {"IOIS", REG_PEX_ERR_DR_IOIS}, 195 {"CIS", REG_PEX_ERR_DR_CIS}, 196 {"CIEP", REG_PEX_ERR_DR_CIEP}, 197 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 198 {"OAC", REG_PEX_ERR_DR_OAC}, 199 {"IOIA", REG_PEX_ERR_DR_IOIA}, 200 {"IMBA", REG_PEX_ERR_DR_IMBA}, 201 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 202 {"LDDE", REG_PEX_ERR_DR_LDDE} 203 }; 204 205 /* Local forward declerations. */ 206 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 207 u_int, int); 208 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 209 u_int, uint32_t, int); 210 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 211 static void fsl_pcib_err_init(device_t); 212 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 213 uint64_t, uint64_t); 214 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 215 uint64_t, uint64_t); 216 217 /* Forward declerations. */ 218 static int fsl_pcib_attach(device_t); 219 static int fsl_pcib_detach(device_t); 220 static int fsl_pcib_probe(device_t); 221 222 static int fsl_pcib_maxslots(device_t); 223 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 224 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 225 uint32_t, int); 226 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 227 int count, int maxcount, int *irqs); 228 static int fsl_pcib_release_msi(device_t dev, device_t child, 229 int count, int *irqs); 230 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq); 231 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq); 232 static int fsl_pcib_map_msi(device_t dev, device_t child, 233 int irq, uint64_t *addr, uint32_t *data); 234 235 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */ 236 237 /* 238 * Bus interface definitions. 239 */ 240 static device_method_t fsl_pcib_methods[] = { 241 /* Device interface */ 242 DEVMETHOD(device_probe, fsl_pcib_probe), 243 DEVMETHOD(device_attach, fsl_pcib_attach), 244 DEVMETHOD(device_detach, fsl_pcib_detach), 245 246 /* pcib interface */ 247 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 248 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 249 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 250 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi), 251 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi), 252 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix), 253 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix), 254 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi), 255 256 DEVMETHOD_END 257 }; 258 259 static devclass_t fsl_pcib_devclass; 260 261 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 262 sizeof(struct fsl_pcib_softc), ofw_pcib_driver); 263 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0, 264 BUS_PASS_BUS); 265 266 static void 267 fsl_pcib_err_intr(void *v) 268 { 269 struct fsl_pcib_softc *sc; 270 device_t dev; 271 uint32_t err_reg, clear_reg; 272 uint8_t i; 273 274 dev = (device_t)v; 275 sc = device_get_softc(dev); 276 277 clear_reg = 0; 278 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 279 280 /* Check which one error occurred */ 281 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 282 if (err_reg & pci_err[i].err_dr_mask) { 283 device_printf(dev, "PCI %d: report %s error\n", 284 device_get_unit(dev), pci_err[i].msg); 285 clear_reg |= pci_err[i].err_dr_mask; 286 } 287 } 288 289 /* Clear pending errors */ 290 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 291 } 292 293 static int 294 fsl_pcib_probe(device_t dev) 295 { 296 297 if (ofw_bus_get_type(dev) == NULL || 298 strcmp(ofw_bus_get_type(dev), "pci") != 0) 299 return (ENXIO); 300 301 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 302 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 303 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 304 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 305 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 306 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 307 return (ENXIO); 308 309 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 310 return (BUS_PROBE_DEFAULT); 311 } 312 313 static int 314 fsl_pcib_attach(device_t dev) 315 { 316 struct fsl_pcib_softc *sc; 317 phandle_t node; 318 uint32_t cfgreg, brctl, ipreg; 319 int error, rid; 320 uint8_t ltssm, capptr; 321 322 sc = device_get_softc(dev); 323 sc->sc_dev = dev; 324 325 sc->sc_rid = 0; 326 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 327 RF_ACTIVE); 328 if (sc->sc_res == NULL) { 329 device_printf(dev, "could not map I/O memory\n"); 330 return (ENXIO); 331 } 332 sc->sc_bst = rman_get_bustag(sc->sc_res); 333 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 334 sc->sc_busnr = 0; 335 336 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1); 337 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S; 338 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S; 339 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN); 340 341 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 342 if (cfgreg != 0x1057 && cfgreg != 0x1957) 343 goto err; 344 345 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 346 while (capptr != 0) { 347 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 348 switch (cfgreg & 0xff) { 349 case PCIY_PCIX: 350 break; 351 case PCIY_EXPRESS: 352 sc->sc_pcie = 1; 353 sc->sc_pcie_capreg = capptr; 354 break; 355 } 356 capptr = (cfgreg >> 8) & 0xff; 357 } 358 359 node = ofw_bus_get_node(dev); 360 361 /* 362 * Initialize generic OF PCI interface (ranges, etc.) 363 */ 364 365 error = ofw_pcib_init(dev); 366 if (error) 367 return (error); 368 369 /* 370 * Configure decode windows for PCI(E) access. 371 */ 372 if (fsl_pcib_decode_win(node, sc) != 0) 373 goto err; 374 375 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 376 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 377 PCIM_CMD_PORTEN; 378 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 379 380 /* Reset the bus. Needed for Radeon video cards. */ 381 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0, 382 PCIR_BRIDGECTL_1, 1); 383 brctl |= PCIB_BCR_SECBUS_RESET; 384 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 385 PCIR_BRIDGECTL_1, brctl, 1); 386 DELAY(100000); 387 brctl &= ~PCIB_BCR_SECBUS_RESET; 388 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 389 PCIR_BRIDGECTL_1, brctl, 1); 390 DELAY(100000); 391 392 if (sc->sc_pcie) { 393 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 394 if (ltssm < LTSSM_STAT_L0) { 395 if (bootverbose) 396 printf("PCI %d: no PCIE link, skipping\n", 397 device_get_unit(dev)); 398 return (0); 399 } 400 } 401 402 /* Allocate irq */ 403 rid = 0; 404 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 405 RF_ACTIVE | RF_SHAREABLE); 406 if (sc->sc_irq_res == NULL) { 407 error = fsl_pcib_detach(dev); 408 if (error != 0) { 409 device_printf(dev, 410 "Detach of the driver failed with error %d\n", 411 error); 412 } 413 return (ENXIO); 414 } 415 416 /* Setup interrupt handler */ 417 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 418 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih); 419 if (error != 0) { 420 device_printf(dev, "Could not setup irq, %d\n", error); 421 sc->sc_ih = NULL; 422 error = fsl_pcib_detach(dev); 423 if (error != 0) { 424 device_printf(dev, 425 "Detach of the driver failed with error %d\n", 426 error); 427 } 428 return (ENXIO); 429 } 430 431 fsl_pcib_err_init(dev); 432 433 return (ofw_pcib_attach(dev)); 434 435 err: 436 return (ENXIO); 437 } 438 439 static uint32_t 440 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 441 u_int reg, int bytes) 442 { 443 uint32_t addr, data; 444 445 addr = CONFIG_ACCESS_ENABLE; 446 addr |= (bus & 0xff) << 16; 447 addr |= (slot & 0x1f) << 11; 448 addr |= (func & 0x7) << 8; 449 addr |= reg & 0xfc; 450 if (sc->sc_pcie) 451 addr |= (reg & 0xf00) << 16; 452 453 mtx_lock_spin(&sc->sc_cfg_mtx); 454 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 455 456 switch (bytes) { 457 case 1: 458 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 459 REG_CFG_DATA + (reg & 3)); 460 break; 461 case 2: 462 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 463 REG_CFG_DATA + (reg & 2))); 464 break; 465 case 4: 466 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 467 REG_CFG_DATA)); 468 break; 469 default: 470 data = ~0; 471 break; 472 } 473 mtx_unlock_spin(&sc->sc_cfg_mtx); 474 return (data); 475 } 476 477 static void 478 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 479 u_int reg, uint32_t data, int bytes) 480 { 481 uint32_t addr; 482 483 addr = CONFIG_ACCESS_ENABLE; 484 addr |= (bus & 0xff) << 16; 485 addr |= (slot & 0x1f) << 11; 486 addr |= (func & 0x7) << 8; 487 addr |= reg & 0xfc; 488 if (sc->sc_pcie) 489 addr |= (reg & 0xf00) << 16; 490 491 mtx_lock_spin(&sc->sc_cfg_mtx); 492 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 493 494 switch (bytes) { 495 case 1: 496 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 497 REG_CFG_DATA + (reg & 3), data); 498 break; 499 case 2: 500 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 501 REG_CFG_DATA + (reg & 2), htole16(data)); 502 break; 503 case 4: 504 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 505 REG_CFG_DATA, htole32(data)); 506 break; 507 } 508 mtx_unlock_spin(&sc->sc_cfg_mtx); 509 } 510 511 #if 0 512 static void 513 dump(struct fsl_pcib_softc *sc) 514 { 515 unsigned int i; 516 517 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 518 for (i = 0; i < 5; i++) { 519 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 520 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 521 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 522 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 523 } 524 printf("\n"); 525 for (i = 1; i < 4; i++) { 526 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 527 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 528 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 529 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 530 } 531 printf("\n"); 532 #undef RD 533 534 for (i = 0; i < 0x48; i += 4) { 535 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 536 i, 4)); 537 } 538 } 539 #endif 540 541 static int 542 fsl_pcib_maxslots(device_t dev) 543 { 544 struct fsl_pcib_softc *sc = device_get_softc(dev); 545 546 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 547 } 548 549 static uint32_t 550 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 551 u_int reg, int bytes) 552 { 553 struct fsl_pcib_softc *sc = device_get_softc(dev); 554 u_int devfn; 555 556 if (bus == sc->sc_busnr && !sc->sc_pcie && 557 slot < PCI_SLOT_FIRST) 558 return (~0); 559 devfn = DEVFN(bus, slot, func); 560 561 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 562 } 563 564 static void 565 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 566 u_int reg, uint32_t val, int bytes) 567 { 568 struct fsl_pcib_softc *sc = device_get_softc(dev); 569 570 if (bus == sc->sc_busnr && !sc->sc_pcie && 571 slot < PCI_SLOT_FIRST) 572 return; 573 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 574 } 575 576 static void 577 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 578 uint64_t size, uint64_t pci_start) 579 { 580 uint32_t attr, bar, tar; 581 582 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 583 584 attr = PIWAR_EN; 585 586 switch (tgt) { 587 case -1: 588 attr &= ~PIWAR_EN; 589 break; 590 case PIWAR_TRGT_LOCAL: 591 attr |= (ffsl(size) - 2); 592 default: 593 attr |= (tgt << PIWAR_TRGT_S); 594 break; 595 } 596 tar = start >> 12; 597 bar = pci_start >> 12; 598 599 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 601 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 602 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 603 } 604 605 static void 606 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 607 uint64_t size, uint64_t pci_start) 608 { 609 uint32_t attr, bar, tar; 610 611 switch (res) { 612 case SYS_RES_MEMORY: 613 attr = 0x80044000 | (ffsll(size) - 2); 614 break; 615 case SYS_RES_IOPORT: 616 attr = 0x80088000 | (ffsll(size) - 2); 617 break; 618 default: 619 attr = 0x0004401f; 620 break; 621 } 622 bar = start >> 12; 623 tar = pci_start >> 12; 624 625 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 626 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 627 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 628 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 629 } 630 631 static void 632 fsl_pcib_err_init(device_t dev) 633 { 634 struct fsl_pcib_softc *sc; 635 uint16_t sec_stat, dsr; 636 uint32_t dcr, err_en; 637 638 sc = device_get_softc(dev); 639 640 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 641 if (sec_stat) 642 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 643 if (sc->sc_pcie) { 644 /* Clear error bits */ 645 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 646 0xffffffff); 647 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 648 0xffffffff); 649 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 650 0xffffffff); 651 652 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 653 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 654 if (dsr) 655 fsl_pcib_cfgwrite(sc, 0, 0, 0, 656 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 657 0xffff, 2); 658 659 /* Enable all errors reporting */ 660 err_en = 0x00bfff00; 661 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 662 err_en); 663 664 /* Enable error reporting: URR, FER, NFER */ 665 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 666 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 667 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 668 PCIEM_CTL_NFER_ENABLE; 669 fsl_pcib_cfgwrite(sc, 0, 0, 0, 670 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 671 } 672 } 673 674 static int 675 fsl_pcib_detach(device_t dev) 676 { 677 struct fsl_pcib_softc *sc; 678 679 sc = device_get_softc(dev); 680 681 mtx_destroy(&sc->sc_cfg_mtx); 682 683 return (bus_generic_detach(dev)); 684 } 685 686 static int 687 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 688 { 689 device_t dev; 690 int error, i, trgt; 691 692 dev = sc->sc_dev; 693 694 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 695 696 /* 697 * Configure LAW decode windows. 698 */ 699 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 700 &sc->sc_ioport_target); 701 if (error != 0) { 702 device_printf(dev, "could not retrieve PCI LAW target info\n"); 703 return (error); 704 } 705 706 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 707 switch (sc->pci_sc.sc_range[i].pci_hi & 708 OFW_PCI_PHYS_HI_SPACEMASK) { 709 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 710 continue; 711 case OFW_PCI_PHYS_HI_SPACE_IO: 712 trgt = sc->sc_ioport_target; 713 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 714 sc->pci_sc.sc_range[i].host, 715 sc->pci_sc.sc_range[i].size, 716 sc->pci_sc.sc_range[i].pci); 717 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 718 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 719 sc->pci_sc.sc_range[i].size - 1; 720 break; 721 case OFW_PCI_PHYS_HI_SPACE_MEM32: 722 case OFW_PCI_PHYS_HI_SPACE_MEM64: 723 trgt = sc->sc_iomem_target; 724 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 725 sc->pci_sc.sc_range[i].host, 726 sc->pci_sc.sc_range[i].size, 727 sc->pci_sc.sc_range[i].pci); 728 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 729 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 730 sc->pci_sc.sc_range[i].size - 1; 731 break; 732 default: 733 panic("Unknown range type %#x\n", 734 sc->pci_sc.sc_range[i].pci_hi & 735 OFW_PCI_PHYS_HI_SPACEMASK); 736 } 737 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 738 sc->pci_sc.sc_range[i].size); 739 if (error != 0) { 740 device_printf(dev, "could not program LAW for range " 741 "%d\n", i); 742 return (error); 743 } 744 } 745 746 /* 747 * Set outbout and inbound windows. 748 */ 749 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 750 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 751 752 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 753 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 754 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0, 755 ptoa(Maxmem), 0); 756 757 /* Direct-map the CCSR for MSIs. */ 758 /* Freescale PCIe 2.x has a dedicated MSI window. */ 759 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */ 760 if (sc->sc_ip_maj >= 2) 761 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa, 762 ccsrbar_size, ccsrbar_pa); 763 else 764 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa, 765 ccsrbar_size, ccsrbar_pa); 766 767 return (0); 768 } 769 770 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 771 int count, int maxcount, int *irqs) 772 { 773 struct fsl_pcib_softc *sc; 774 vmem_addr_t start; 775 int err, i; 776 777 sc = device_get_softc(dev); 778 if (msi_vmem == NULL) 779 return (ENODEV); 780 781 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0, 782 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 783 784 if (err) 785 return (err); 786 787 for (i = 0; i < count; i++) 788 irqs[i] = start + i; 789 790 return (0); 791 } 792 793 static int fsl_pcib_release_msi(device_t dev, device_t child, 794 int count, int *irqs) 795 { 796 if (msi_vmem == NULL) 797 return (ENODEV); 798 799 vmem_xfree(msi_vmem, irqs[0], count); 800 return (0); 801 } 802 803 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq) 804 { 805 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq)); 806 } 807 808 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq) 809 { 810 return (fsl_pcib_release_msi(dev, child, 1, &irq)); 811 } 812 813 static int fsl_pcib_map_msi(device_t dev, device_t child, 814 int irq, uint64_t *addr, uint32_t *data) 815 { 816 struct fsl_msi_map *mp; 817 818 SLIST_FOREACH(mp, &fsl_msis, slist) { 819 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS) 820 break; 821 } 822 823 if (mp == NULL) 824 return (ENODEV); 825 826 *data = (irq & 255); 827 *addr = ccsrbar_pa + mp->target; 828 829 return (0); 830 } 831 832 /* 833 * Linux device trees put the msi@<x> as children of the SoC, with ranges based 834 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between 835 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC 836 * driver just to allocate a subregion for a sibling driver). This driver will 837 * use ccsr_write() and ccsr_read() instead. 838 */ 839 840 #define FSL_NUM_IRQS 8 841 #define FSL_NUM_MSI_PER_IRQ 32 842 #define FSL_MSI_TARGET 0x140 843 844 struct fsl_msi_softc { 845 vm_offset_t sc_base; 846 vm_offset_t sc_target; 847 int sc_msi_base_irq; 848 struct fsl_msi_map sc_map; 849 struct fsl_msi_irq { 850 /* This struct gets passed as the filter private data. */ 851 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */ 852 struct resource *res; 853 int irq; 854 void *cookie; 855 int vectors[FSL_NUM_MSI_PER_IRQ]; 856 vm_offset_t reg; 857 } sc_msi_irq[FSL_NUM_IRQS]; 858 }; 859 860 static int 861 fsl_msi_intr_filter(void *priv) 862 { 863 struct fsl_msi_irq *data = priv; 864 uint32_t reg; 865 int i; 866 867 reg = ccsr_read4(ccsrbar_va + data->reg); 868 i = 0; 869 while (reg != 0) { 870 if (reg & 1) 871 powerpc_dispatch_intr(data->vectors[i], NULL); 872 reg >>= 1; 873 i++; 874 } 875 876 return (FILTER_HANDLED); 877 } 878 879 static int 880 fsl_msi_probe(device_t dev) 881 { 882 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi")) 883 return (ENXIO); 884 885 device_set_desc(dev, "Freescale MSI"); 886 887 return (BUS_PROBE_DEFAULT); 888 } 889 890 static int 891 fsl_msi_attach(device_t dev) 892 { 893 struct fsl_msi_softc *sc; 894 struct fsl_msi_irq *irq; 895 int i; 896 897 sc = device_get_softc(dev); 898 899 if (msi_vmem == NULL) 900 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK); 901 902 /* Manually play with resource entries. */ 903 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); 904 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1); 905 906 if (sc->sc_map.target == 0) 907 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET; 908 909 for (i = 0; i < FSL_NUM_IRQS; i++) { 910 irq = &sc->sc_msi_irq[i]; 911 irq->irq = i; 912 irq->reg = sc->sc_base + 16 * i; 913 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 914 &irq->irq, RF_ACTIVE); 915 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE, 916 fsl_msi_intr_filter, NULL, irq, &irq->cookie); 917 } 918 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev), 919 FSL_NUM_MSIS, 0, 0); 920 921 /* Let vmem and the IRQ subsystem work their magic for allocations. */ 922 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK); 923 924 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist); 925 926 return (0); 927 } 928 929 static void 930 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv) 931 { 932 struct fsl_msi_softc *sc; 933 struct fsl_msi_irq *irqd; 934 935 sc = device_get_softc(dev); 936 937 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ]; 938 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector; 939 } 940 941 static device_method_t fsl_msi_methods[] = { 942 DEVMETHOD(device_probe, fsl_msi_probe), 943 DEVMETHOD(device_attach, fsl_msi_attach), 944 945 DEVMETHOD(pic_enable, fsl_msi_enable), 946 DEVMETHOD_END 947 }; 948 949 static devclass_t fsl_msi_devclass; 950 951 static driver_t fsl_msi_driver = { 952 "fsl_msi", 953 fsl_msi_methods, 954 sizeof(struct fsl_msi_softc) 955 }; 956 957 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, fsl_msi_devclass, 0, 0, 958 BUS_PASS_INTERRUPT + 1); 959