1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ktr.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/socket.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/rman.h> 55 #include <sys/endian.h> 56 57 #include <vm/vm.h> 58 #include <vm/pmap.h> 59 60 #include <dev/ofw/ofw_pci.h> 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 #include <dev/ofw/ofwpci.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcib_private.h> 67 68 #include "ofw_bus_if.h" 69 #include "pcib_if.h" 70 71 #include <machine/resource.h> 72 #include <machine/bus.h> 73 #include <machine/intr_machdep.h> 74 75 #include <powerpc/mpc85xx/mpc85xx.h> 76 77 #define REG_CFG_ADDR 0x0000 78 #define CONFIG_ACCESS_ENABLE 0x80000000 79 80 #define REG_CFG_DATA 0x0004 81 #define REG_INT_ACK 0x0008 82 83 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 84 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 85 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 86 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 87 88 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 89 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 90 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 91 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 92 93 #define REG_PEX_MES_DR 0x0020 94 #define REG_PEX_MES_IER 0x0028 95 #define REG_PEX_ERR_DR 0x0e00 96 #define REG_PEX_ERR_EN 0x0e08 97 98 #define REG_PEX_ERR_DR 0x0e00 99 #define REG_PEX_ERR_DR_ME 0x80000000 100 #define REG_PEX_ERR_DR_PCT 0x800000 101 #define REG_PEX_ERR_DR_PAT 0x400000 102 #define REG_PEX_ERR_DR_PCAC 0x200000 103 #define REG_PEX_ERR_DR_PNM 0x100000 104 #define REG_PEX_ERR_DR_CDNSC 0x80000 105 #define REG_PEX_ERR_DR_CRSNC 0x40000 106 #define REG_PEX_ERR_DR_ICCA 0x20000 107 #define REG_PEX_ERR_DR_IACA 0x10000 108 #define REG_PEX_ERR_DR_CRST 0x8000 109 #define REG_PEX_ERR_DR_MIS 0x4000 110 #define REG_PEX_ERR_DR_IOIS 0x2000 111 #define REG_PEX_ERR_DR_CIS 0x1000 112 #define REG_PEX_ERR_DR_CIEP 0x800 113 #define REG_PEX_ERR_DR_IOIEP 0x400 114 #define REG_PEX_ERR_DR_OAC 0x200 115 #define REG_PEX_ERR_DR_IOIA 0x100 116 #define REG_PEX_ERR_DR_IMBA 0x80 117 #define REG_PEX_ERR_DR_IIOBA 0x40 118 #define REG_PEX_ERR_DR_LDDE 0x20 119 #define REG_PEX_ERR_EN 0x0e08 120 121 #define PCIR_LTSSM 0x404 122 #define LTSSM_STAT_L0 0x16 123 124 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 125 126 struct fsl_pcib_softc { 127 struct ofw_pci_softc pci_sc; 128 device_t sc_dev; 129 struct mtx sc_cfg_mtx; 130 131 int sc_iomem_target; 132 bus_addr_t sc_iomem_start, sc_iomem_end; 133 int sc_ioport_target; 134 bus_addr_t sc_ioport_start, sc_ioport_end; 135 136 struct resource *sc_res; 137 bus_space_handle_t sc_bsh; 138 bus_space_tag_t sc_bst; 139 int sc_rid; 140 141 struct resource *sc_irq_res; 142 void *sc_ih; 143 144 int sc_busnr; 145 int sc_pcie; 146 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 147 148 /* Devices that need special attention. */ 149 int sc_devfn_tundra; 150 int sc_devfn_via_ide; 151 }; 152 153 struct fsl_pcib_err_dr { 154 const char *msg; 155 uint32_t err_dr_mask; 156 }; 157 158 static const struct fsl_pcib_err_dr pci_err[] = { 159 {"ME", REG_PEX_ERR_DR_ME}, 160 {"PCT", REG_PEX_ERR_DR_PCT}, 161 {"PAT", REG_PEX_ERR_DR_PAT}, 162 {"PCAC", REG_PEX_ERR_DR_PCAC}, 163 {"PNM", REG_PEX_ERR_DR_PNM}, 164 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 165 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 166 {"ICCA", REG_PEX_ERR_DR_ICCA}, 167 {"IACA", REG_PEX_ERR_DR_IACA}, 168 {"CRST", REG_PEX_ERR_DR_CRST}, 169 {"MIS", REG_PEX_ERR_DR_MIS}, 170 {"IOIS", REG_PEX_ERR_DR_IOIS}, 171 {"CIS", REG_PEX_ERR_DR_CIS}, 172 {"CIEP", REG_PEX_ERR_DR_CIEP}, 173 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 174 {"OAC", REG_PEX_ERR_DR_OAC}, 175 {"IOIA", REG_PEX_ERR_DR_IOIA}, 176 {"IMBA", REG_PEX_ERR_DR_IMBA}, 177 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 178 {"LDDE", REG_PEX_ERR_DR_LDDE} 179 }; 180 181 /* Local forward declerations. */ 182 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 183 u_int, int); 184 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 185 u_int, uint32_t, int); 186 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 187 static void fsl_pcib_err_init(device_t); 188 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 189 uint64_t, uint64_t); 190 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 191 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 192 uint64_t, uint64_t); 193 194 /* Forward declerations. */ 195 static int fsl_pcib_attach(device_t); 196 static int fsl_pcib_detach(device_t); 197 static int fsl_pcib_probe(device_t); 198 199 static int fsl_pcib_maxslots(device_t); 200 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 201 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 202 uint32_t, int); 203 204 /* 205 * Bus interface definitions. 206 */ 207 static device_method_t fsl_pcib_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, fsl_pcib_probe), 210 DEVMETHOD(device_attach, fsl_pcib_attach), 211 DEVMETHOD(device_detach, fsl_pcib_detach), 212 213 /* pcib interface */ 214 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 215 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 216 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 217 218 DEVMETHOD_END 219 }; 220 221 static devclass_t fsl_pcib_devclass; 222 223 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 224 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 225 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0, 226 BUS_PASS_BUS); 227 228 static void 229 fsl_pcib_err_intr(void *v) 230 { 231 struct fsl_pcib_softc *sc; 232 device_t dev; 233 uint32_t err_reg, clear_reg; 234 uint8_t i; 235 236 dev = (device_t)v; 237 sc = device_get_softc(dev); 238 239 clear_reg = 0; 240 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 241 242 /* Check which one error occurred */ 243 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 244 if (err_reg & pci_err[i].err_dr_mask) { 245 device_printf(dev, "PCI %d: report %s error\n", 246 device_get_unit(dev), pci_err[i].msg); 247 clear_reg |= pci_err[i].err_dr_mask; 248 } 249 } 250 251 /* Clear pending errors */ 252 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 253 } 254 255 static int 256 fsl_pcib_probe(device_t dev) 257 { 258 259 if (ofw_bus_get_type(dev) == NULL || 260 strcmp(ofw_bus_get_type(dev), "pci") != 0) 261 return (ENXIO); 262 263 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 264 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 265 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 266 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 267 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 268 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 269 return (ENXIO); 270 271 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 272 return (BUS_PROBE_DEFAULT); 273 } 274 275 static int 276 fsl_pcib_attach(device_t dev) 277 { 278 struct fsl_pcib_softc *sc; 279 phandle_t node; 280 uint32_t cfgreg; 281 int error, maxslot, rid; 282 uint8_t ltssm, capptr; 283 284 sc = device_get_softc(dev); 285 sc->sc_dev = dev; 286 287 sc->sc_rid = 0; 288 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 289 RF_ACTIVE); 290 if (sc->sc_res == NULL) { 291 device_printf(dev, "could not map I/O memory\n"); 292 return (ENXIO); 293 } 294 sc->sc_bst = rman_get_bustag(sc->sc_res); 295 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 296 sc->sc_busnr = 0; 297 298 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN); 299 300 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 301 if (cfgreg != 0x1057 && cfgreg != 0x1957) 302 goto err; 303 304 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 305 while (capptr != 0) { 306 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 307 switch (cfgreg & 0xff) { 308 case PCIY_PCIX: 309 break; 310 case PCIY_EXPRESS: 311 sc->sc_pcie = 1; 312 sc->sc_pcie_capreg = capptr; 313 break; 314 } 315 capptr = (cfgreg >> 8) & 0xff; 316 } 317 318 node = ofw_bus_get_node(dev); 319 320 /* 321 * Initialize generic OF PCI interface (ranges, etc.) 322 */ 323 324 error = ofw_pci_init(dev); 325 if (error) 326 return (error); 327 328 /* 329 * Configure decode windows for PCI(E) access. 330 */ 331 if (fsl_pcib_decode_win(node, sc) != 0) 332 goto err; 333 334 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 335 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 336 PCIM_CMD_PORTEN; 337 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 338 339 sc->sc_devfn_tundra = -1; 340 sc->sc_devfn_via_ide = -1; 341 342 343 /* 344 * Scan bus using firmware configured, 0 based bus numbering. 345 */ 346 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 347 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 348 349 if (sc->sc_pcie) { 350 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 351 if (ltssm < LTSSM_STAT_L0) { 352 if (bootverbose) 353 printf("PCI %d: no PCIE link, skipping\n", 354 device_get_unit(dev)); 355 return (0); 356 } 357 } 358 359 /* Allocate irq */ 360 rid = 0; 361 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 362 RF_ACTIVE | RF_SHAREABLE); 363 if (sc->sc_irq_res == NULL) { 364 error = fsl_pcib_detach(dev); 365 if (error != 0) { 366 device_printf(dev, 367 "Detach of the driver failed with error %d\n", 368 error); 369 } 370 return (ENXIO); 371 } 372 373 /* Setup interrupt handler */ 374 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 375 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih); 376 if (error != 0) { 377 device_printf(dev, "Could not setup irq, %d\n", error); 378 sc->sc_ih = NULL; 379 error = fsl_pcib_detach(dev); 380 if (error != 0) { 381 device_printf(dev, 382 "Detach of the driver failed with error %d\n", 383 error); 384 } 385 return (ENXIO); 386 } 387 388 fsl_pcib_err_init(dev); 389 390 return (ofw_pci_attach(dev)); 391 392 err: 393 return (ENXIO); 394 } 395 396 static uint32_t 397 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 398 u_int reg, int bytes) 399 { 400 uint32_t addr, data; 401 402 addr = CONFIG_ACCESS_ENABLE; 403 addr |= (bus & 0xff) << 16; 404 addr |= (slot & 0x1f) << 11; 405 addr |= (func & 0x7) << 8; 406 addr |= reg & 0xfc; 407 if (sc->sc_pcie) 408 addr |= (reg & 0xf00) << 16; 409 410 mtx_lock_spin(&sc->sc_cfg_mtx); 411 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 412 413 switch (bytes) { 414 case 1: 415 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 416 REG_CFG_DATA + (reg & 3)); 417 break; 418 case 2: 419 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 420 REG_CFG_DATA + (reg & 2))); 421 break; 422 case 4: 423 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 424 REG_CFG_DATA)); 425 break; 426 default: 427 data = ~0; 428 break; 429 } 430 mtx_unlock_spin(&sc->sc_cfg_mtx); 431 return (data); 432 } 433 434 static void 435 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 436 u_int reg, uint32_t data, int bytes) 437 { 438 uint32_t addr; 439 440 addr = CONFIG_ACCESS_ENABLE; 441 addr |= (bus & 0xff) << 16; 442 addr |= (slot & 0x1f) << 11; 443 addr |= (func & 0x7) << 8; 444 addr |= reg & 0xfc; 445 if (sc->sc_pcie) 446 addr |= (reg & 0xf00) << 16; 447 448 mtx_lock_spin(&sc->sc_cfg_mtx); 449 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 450 451 switch (bytes) { 452 case 1: 453 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 454 REG_CFG_DATA + (reg & 3), data); 455 break; 456 case 2: 457 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 458 REG_CFG_DATA + (reg & 2), htole16(data)); 459 break; 460 case 4: 461 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 462 REG_CFG_DATA, htole32(data)); 463 break; 464 } 465 mtx_unlock_spin(&sc->sc_cfg_mtx); 466 } 467 468 #if 0 469 static void 470 dump(struct fsl_pcib_softc *sc) 471 { 472 unsigned int i; 473 474 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 475 for (i = 0; i < 5; i++) { 476 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 477 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 478 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 479 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 480 } 481 printf("\n"); 482 for (i = 1; i < 4; i++) { 483 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 484 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 485 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 486 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 487 } 488 printf("\n"); 489 #undef RD 490 491 for (i = 0; i < 0x48; i += 4) { 492 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 493 i, 4)); 494 } 495 } 496 #endif 497 498 static int 499 fsl_pcib_maxslots(device_t dev) 500 { 501 struct fsl_pcib_softc *sc = device_get_softc(dev); 502 503 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 504 } 505 506 static uint32_t 507 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 508 u_int reg, int bytes) 509 { 510 struct fsl_pcib_softc *sc = device_get_softc(dev); 511 u_int devfn; 512 513 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 514 return (~0); 515 devfn = DEVFN(bus, slot, func); 516 if (devfn == sc->sc_devfn_tundra) 517 return (~0); 518 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 519 return (1); 520 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 521 } 522 523 static void 524 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 525 u_int reg, uint32_t val, int bytes) 526 { 527 struct fsl_pcib_softc *sc = device_get_softc(dev); 528 529 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 530 return; 531 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 532 } 533 534 static void 535 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 536 int slot, int fn) 537 { 538 539 if (device == 0x0686) { 540 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 541 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 542 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 543 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 544 } else if (device == 0x0571) { 545 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 546 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 547 } 548 } 549 550 static int 551 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 552 { 553 int secbus; 554 int old_pribus, old_secbus, old_subbus; 555 int new_pribus, new_secbus, new_subbus; 556 int slot, func, maxfunc; 557 uint16_t vendor, device; 558 uint8_t brctl, command, hdrtype, subclass; 559 560 secbus = bus; 561 for (slot = 0; slot <= maxslot; slot++) { 562 maxfunc = 0; 563 for (func = 0; func <= maxfunc; func++) { 564 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 565 func, PCIR_HDRTYPE, 1); 566 567 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 568 continue; 569 570 if (func == 0 && (hdrtype & PCIM_MFDEV)) 571 maxfunc = PCI_FUNCMAX; 572 573 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 574 func, PCIR_VENDOR, 2); 575 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 576 func, PCIR_DEVICE, 2); 577 578 if (vendor == 0x1957 && device == 0x3fff) { 579 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 580 continue; 581 } 582 583 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 584 func, PCIR_COMMAND, 1); 585 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 586 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 587 PCIR_COMMAND, command, 1); 588 589 if (vendor == 0x1106) 590 fsl_pcib_init_via(sc, device, bus, slot, func); 591 592 /* 593 * Handle PCI-PCI bridges 594 */ 595 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 596 func, PCIR_SUBCLASS, 1); 597 598 /* Allow all DEVTYPE 1 devices */ 599 if (hdrtype != PCIM_HDRTYPE_BRIDGE) 600 continue; 601 602 brctl = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, 603 PCIR_BRIDGECTL_1, 1); 604 brctl |= PCIB_BCR_SECBUS_RESET; 605 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 606 PCIR_BRIDGECTL_1, brctl, 1); 607 DELAY(100000); 608 brctl &= ~PCIB_BCR_SECBUS_RESET; 609 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 610 PCIR_BRIDGECTL_1, brctl, 1); 611 DELAY(100000); 612 613 secbus++; 614 615 /* Read currect bus register configuration */ 616 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 617 slot, func, PCIR_PRIBUS_1, 1); 618 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 619 slot, func, PCIR_SECBUS_1, 1); 620 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 621 slot, func, PCIR_SUBBUS_1, 1); 622 623 if (bootverbose) 624 printf("PCI: reading firmware bus numbers for " 625 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 626 secbus, old_pribus, old_secbus, old_subbus); 627 628 new_pribus = bus; 629 new_secbus = secbus; 630 631 secbus = fsl_pcib_init(sc, secbus, 632 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 633 634 new_subbus = secbus; 635 636 if (bootverbose) 637 printf("PCI: translate firmware bus numbers " 638 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 639 secbus, old_pribus, old_secbus, old_subbus, 640 new_pribus, new_secbus, new_subbus); 641 642 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 643 PCIR_PRIBUS_1, new_pribus, 1); 644 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 645 PCIR_SECBUS_1, new_secbus, 1); 646 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 647 PCIR_SUBBUS_1, new_subbus, 1); 648 } 649 } 650 651 return (secbus); 652 } 653 654 static void 655 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 656 uint64_t size, uint64_t pci_start) 657 { 658 uint32_t attr, bar, tar; 659 660 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 661 662 switch (tgt) { 663 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 664 case OCP85XX_TGTIF_RAM1_85XX: 665 case OCP85XX_TGTIF_RAM1_QORIQ: 666 attr = 0xa0f55000 | (ffsl(size) - 2); 667 break; 668 default: 669 attr = 0; 670 break; 671 } 672 tar = start >> 12; 673 bar = pci_start >> 12; 674 675 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 676 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 677 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 678 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 679 } 680 681 static void 682 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 683 uint64_t size, uint64_t pci_start) 684 { 685 uint32_t attr, bar, tar; 686 687 switch (res) { 688 case SYS_RES_MEMORY: 689 attr = 0x80044000 | (ffsll(size) - 2); 690 break; 691 case SYS_RES_IOPORT: 692 attr = 0x80088000 | (ffsll(size) - 2); 693 break; 694 default: 695 attr = 0x0004401f; 696 break; 697 } 698 bar = start >> 12; 699 tar = pci_start >> 12; 700 701 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 702 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 703 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 704 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 705 } 706 707 708 static void 709 fsl_pcib_err_init(device_t dev) 710 { 711 struct fsl_pcib_softc *sc; 712 uint16_t sec_stat, dsr; 713 uint32_t dcr, err_en; 714 715 sc = device_get_softc(dev); 716 717 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 718 if (sec_stat) 719 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 720 if (sc->sc_pcie) { 721 /* Clear error bits */ 722 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 723 0xffffffff); 724 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 725 0xffffffff); 726 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 727 0xffffffff); 728 729 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 730 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 731 if (dsr) 732 fsl_pcib_cfgwrite(sc, 0, 0, 0, 733 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 734 0xffff, 2); 735 736 /* Enable all errors reporting */ 737 err_en = 0x00bfff00; 738 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 739 err_en); 740 741 /* Enable error reporting: URR, FER, NFER */ 742 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 743 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 744 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 745 PCIEM_CTL_NFER_ENABLE; 746 fsl_pcib_cfgwrite(sc, 0, 0, 0, 747 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 748 } 749 } 750 751 static int 752 fsl_pcib_detach(device_t dev) 753 { 754 struct fsl_pcib_softc *sc; 755 756 sc = device_get_softc(dev); 757 758 mtx_destroy(&sc->sc_cfg_mtx); 759 760 return (bus_generic_detach(dev)); 761 } 762 763 static int 764 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 765 { 766 device_t dev; 767 int error, i, trgt; 768 769 dev = sc->sc_dev; 770 771 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 772 773 /* 774 * Configure LAW decode windows. 775 */ 776 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 777 &sc->sc_ioport_target); 778 if (error != 0) { 779 device_printf(dev, "could not retrieve PCI LAW target info\n"); 780 return (error); 781 } 782 783 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 784 switch (sc->pci_sc.sc_range[i].pci_hi & 785 OFW_PCI_PHYS_HI_SPACEMASK) { 786 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 787 continue; 788 case OFW_PCI_PHYS_HI_SPACE_IO: 789 trgt = sc->sc_ioport_target; 790 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 791 sc->pci_sc.sc_range[i].host, 792 sc->pci_sc.sc_range[i].size, 793 sc->pci_sc.sc_range[i].pci); 794 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 795 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 796 sc->pci_sc.sc_range[i].size - 1; 797 break; 798 case OFW_PCI_PHYS_HI_SPACE_MEM32: 799 case OFW_PCI_PHYS_HI_SPACE_MEM64: 800 trgt = sc->sc_iomem_target; 801 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 802 sc->pci_sc.sc_range[i].host, 803 sc->pci_sc.sc_range[i].size, 804 sc->pci_sc.sc_range[i].pci); 805 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 806 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 807 sc->pci_sc.sc_range[i].size - 1; 808 break; 809 default: 810 panic("Unknown range type %#x\n", 811 sc->pci_sc.sc_range[i].pci_hi & 812 OFW_PCI_PHYS_HI_SPACEMASK); 813 } 814 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 815 sc->pci_sc.sc_range[i].size); 816 if (error != 0) { 817 device_printf(dev, "could not program LAW for range " 818 "%d\n", i); 819 return (error); 820 } 821 } 822 823 /* 824 * Set outbout and inbound windows. 825 */ 826 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 827 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 828 829 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 830 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 831 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 832 2U * 1024U * 1024U * 1024U, 0); 833 834 return (0); 835 } 836