1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ktr.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/socket.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/queue.h> 55 #include <sys/rman.h> 56 #include <sys/endian.h> 57 #include <sys/vmem.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/ofw/ofw_pci.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofwpci.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 74 #include <machine/resource.h> 75 #include <machine/bus.h> 76 #include <machine/intr_machdep.h> 77 78 #include <powerpc/mpc85xx/mpc85xx.h> 79 80 #define REG_CFG_ADDR 0x0000 81 #define CONFIG_ACCESS_ENABLE 0x80000000 82 83 #define REG_CFG_DATA 0x0004 84 #define REG_INT_ACK 0x0008 85 86 #define REG_PEX_IP_BLK_REV1 0x0bf8 87 #define IP_MJ_M 0x0000ff00 88 #define IP_MJ_S 8 89 #define IP_MN_M 0x000000ff 90 #define IP_MN_S 0 91 92 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 93 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 94 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 95 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 96 97 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 98 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 99 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 100 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 101 #define PIWAR_EN 0x80000000 102 #define PIWAR_PF 0x40000000 103 #define PIWAR_TRGT_M 0x00f00000 104 #define PIWAR_TRGT_S 20 105 #define PIWAR_TRGT_CCSR 0xe 106 #define PIWAR_TRGT_LOCAL 0xf 107 108 #define REG_PEX_MES_DR 0x0020 109 #define REG_PEX_MES_IER 0x0028 110 #define REG_PEX_ERR_DR 0x0e00 111 #define REG_PEX_ERR_EN 0x0e08 112 113 #define REG_PEX_ERR_DR 0x0e00 114 #define REG_PEX_ERR_DR_ME 0x80000000 115 #define REG_PEX_ERR_DR_PCT 0x800000 116 #define REG_PEX_ERR_DR_PAT 0x400000 117 #define REG_PEX_ERR_DR_PCAC 0x200000 118 #define REG_PEX_ERR_DR_PNM 0x100000 119 #define REG_PEX_ERR_DR_CDNSC 0x80000 120 #define REG_PEX_ERR_DR_CRSNC 0x40000 121 #define REG_PEX_ERR_DR_ICCA 0x20000 122 #define REG_PEX_ERR_DR_IACA 0x10000 123 #define REG_PEX_ERR_DR_CRST 0x8000 124 #define REG_PEX_ERR_DR_MIS 0x4000 125 #define REG_PEX_ERR_DR_IOIS 0x2000 126 #define REG_PEX_ERR_DR_CIS 0x1000 127 #define REG_PEX_ERR_DR_CIEP 0x800 128 #define REG_PEX_ERR_DR_IOIEP 0x400 129 #define REG_PEX_ERR_DR_OAC 0x200 130 #define REG_PEX_ERR_DR_IOIA 0x100 131 #define REG_PEX_ERR_DR_IMBA 0x80 132 #define REG_PEX_ERR_DR_IIOBA 0x40 133 #define REG_PEX_ERR_DR_LDDE 0x20 134 #define REG_PEX_ERR_EN 0x0e08 135 136 #define PCIR_LTSSM 0x404 137 #define LTSSM_STAT_L0 0x16 138 139 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 140 141 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */ 142 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */ 143 144 struct fsl_pcib_softc { 145 struct ofw_pci_softc pci_sc; 146 device_t sc_dev; 147 struct mtx sc_cfg_mtx; 148 int sc_ip_maj; 149 int sc_ip_min; 150 151 int sc_iomem_target; 152 bus_addr_t sc_iomem_start, sc_iomem_end; 153 int sc_ioport_target; 154 bus_addr_t sc_ioport_start, sc_ioport_end; 155 156 struct resource *sc_res; 157 bus_space_handle_t sc_bsh; 158 bus_space_tag_t sc_bst; 159 int sc_rid; 160 161 struct resource *sc_irq_res; 162 void *sc_ih; 163 164 int sc_busnr; 165 int sc_pcie; 166 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 167 }; 168 169 struct fsl_pcib_err_dr { 170 const char *msg; 171 uint32_t err_dr_mask; 172 }; 173 174 struct fsl_msi_map { 175 SLIST_ENTRY(fsl_msi_map) slist; 176 uint32_t irq_base; 177 bus_addr_t target; 178 }; 179 180 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head); 181 182 static const struct fsl_pcib_err_dr pci_err[] = { 183 {"ME", REG_PEX_ERR_DR_ME}, 184 {"PCT", REG_PEX_ERR_DR_PCT}, 185 {"PAT", REG_PEX_ERR_DR_PAT}, 186 {"PCAC", REG_PEX_ERR_DR_PCAC}, 187 {"PNM", REG_PEX_ERR_DR_PNM}, 188 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 189 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 190 {"ICCA", REG_PEX_ERR_DR_ICCA}, 191 {"IACA", REG_PEX_ERR_DR_IACA}, 192 {"CRST", REG_PEX_ERR_DR_CRST}, 193 {"MIS", REG_PEX_ERR_DR_MIS}, 194 {"IOIS", REG_PEX_ERR_DR_IOIS}, 195 {"CIS", REG_PEX_ERR_DR_CIS}, 196 {"CIEP", REG_PEX_ERR_DR_CIEP}, 197 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 198 {"OAC", REG_PEX_ERR_DR_OAC}, 199 {"IOIA", REG_PEX_ERR_DR_IOIA}, 200 {"IMBA", REG_PEX_ERR_DR_IMBA}, 201 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 202 {"LDDE", REG_PEX_ERR_DR_LDDE} 203 }; 204 205 /* Local forward declerations. */ 206 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 207 u_int, int); 208 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 209 u_int, uint32_t, int); 210 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 211 static void fsl_pcib_err_init(device_t); 212 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 213 uint64_t, uint64_t); 214 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 215 uint64_t, uint64_t); 216 217 /* Forward declerations. */ 218 static int fsl_pcib_attach(device_t); 219 static int fsl_pcib_detach(device_t); 220 static int fsl_pcib_probe(device_t); 221 222 static int fsl_pcib_maxslots(device_t); 223 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 224 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 225 uint32_t, int); 226 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 227 int count, int maxcount, int *irqs); 228 static int fsl_pcib_release_msi(device_t dev, device_t child, 229 int count, int *irqs); 230 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq); 231 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq); 232 static int fsl_pcib_map_msi(device_t dev, device_t child, 233 int irq, uint64_t *addr, uint32_t *data); 234 235 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */ 236 237 /* 238 * Bus interface definitions. 239 */ 240 static device_method_t fsl_pcib_methods[] = { 241 /* Device interface */ 242 DEVMETHOD(device_probe, fsl_pcib_probe), 243 DEVMETHOD(device_attach, fsl_pcib_attach), 244 DEVMETHOD(device_detach, fsl_pcib_detach), 245 246 /* pcib interface */ 247 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 248 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 249 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 250 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi), 251 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi), 252 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix), 253 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix), 254 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi), 255 256 DEVMETHOD_END 257 }; 258 259 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 260 sizeof(struct fsl_pcib_softc), ofw_pcib_driver); 261 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS); 262 263 static void 264 fsl_pcib_err_intr(void *v) 265 { 266 struct fsl_pcib_softc *sc; 267 device_t dev; 268 uint32_t err_reg, clear_reg; 269 uint8_t i; 270 271 dev = (device_t)v; 272 sc = device_get_softc(dev); 273 274 clear_reg = 0; 275 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 276 277 /* Check which one error occurred */ 278 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 279 if (err_reg & pci_err[i].err_dr_mask) { 280 device_printf(dev, "PCI %d: report %s error\n", 281 device_get_unit(dev), pci_err[i].msg); 282 clear_reg |= pci_err[i].err_dr_mask; 283 } 284 } 285 286 /* Clear pending errors */ 287 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 288 } 289 290 static int 291 fsl_pcib_probe(device_t dev) 292 { 293 294 if (ofw_bus_get_type(dev) == NULL || 295 strcmp(ofw_bus_get_type(dev), "pci") != 0) 296 return (ENXIO); 297 298 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 299 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 300 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 301 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 302 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 303 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 304 return (ENXIO); 305 306 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 307 return (BUS_PROBE_DEFAULT); 308 } 309 310 static int 311 fsl_pcib_attach(device_t dev) 312 { 313 struct fsl_pcib_softc *sc; 314 phandle_t node; 315 uint32_t cfgreg, brctl, ipreg; 316 int error, rid; 317 uint8_t ltssm, capptr; 318 319 sc = device_get_softc(dev); 320 sc->sc_dev = dev; 321 322 sc->sc_rid = 0; 323 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 324 RF_ACTIVE); 325 if (sc->sc_res == NULL) { 326 device_printf(dev, "could not map I/O memory\n"); 327 return (ENXIO); 328 } 329 sc->sc_bst = rman_get_bustag(sc->sc_res); 330 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 331 sc->sc_busnr = 0; 332 333 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1); 334 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S; 335 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S; 336 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN); 337 338 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 339 if (cfgreg != 0x1057 && cfgreg != 0x1957) 340 goto err; 341 342 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 343 while (capptr != 0) { 344 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 345 switch (cfgreg & 0xff) { 346 case PCIY_PCIX: 347 break; 348 case PCIY_EXPRESS: 349 sc->sc_pcie = 1; 350 sc->sc_pcie_capreg = capptr; 351 break; 352 } 353 capptr = (cfgreg >> 8) & 0xff; 354 } 355 356 node = ofw_bus_get_node(dev); 357 358 /* 359 * Initialize generic OF PCI interface (ranges, etc.) 360 */ 361 362 error = ofw_pcib_init(dev); 363 if (error) 364 return (error); 365 366 /* 367 * Configure decode windows for PCI(E) access. 368 */ 369 if (fsl_pcib_decode_win(node, sc) != 0) 370 goto err; 371 372 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 373 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 374 PCIM_CMD_PORTEN; 375 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 376 377 /* Reset the bus. Needed for Radeon video cards. */ 378 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0, 379 PCIR_BRIDGECTL_1, 1); 380 brctl |= PCIB_BCR_SECBUS_RESET; 381 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 382 PCIR_BRIDGECTL_1, brctl, 1); 383 DELAY(100000); 384 brctl &= ~PCIB_BCR_SECBUS_RESET; 385 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 386 PCIR_BRIDGECTL_1, brctl, 1); 387 DELAY(100000); 388 389 if (sc->sc_pcie) { 390 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 391 if (ltssm < LTSSM_STAT_L0) { 392 if (bootverbose) 393 printf("PCI %d: no PCIE link, skipping\n", 394 device_get_unit(dev)); 395 return (0); 396 } 397 } 398 399 /* Allocate irq */ 400 rid = 0; 401 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 402 RF_ACTIVE | RF_SHAREABLE); 403 if (sc->sc_irq_res == NULL) { 404 error = fsl_pcib_detach(dev); 405 if (error != 0) { 406 device_printf(dev, 407 "Detach of the driver failed with error %d\n", 408 error); 409 } 410 return (ENXIO); 411 } 412 413 /* Setup interrupt handler */ 414 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 415 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih); 416 if (error != 0) { 417 device_printf(dev, "Could not setup irq, %d\n", error); 418 sc->sc_ih = NULL; 419 error = fsl_pcib_detach(dev); 420 if (error != 0) { 421 device_printf(dev, 422 "Detach of the driver failed with error %d\n", 423 error); 424 } 425 return (ENXIO); 426 } 427 428 fsl_pcib_err_init(dev); 429 430 return (ofw_pcib_attach(dev)); 431 432 err: 433 return (ENXIO); 434 } 435 436 static uint32_t 437 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 438 u_int reg, int bytes) 439 { 440 uint32_t addr, data; 441 442 addr = CONFIG_ACCESS_ENABLE; 443 addr |= (bus & 0xff) << 16; 444 addr |= (slot & 0x1f) << 11; 445 addr |= (func & 0x7) << 8; 446 addr |= reg & 0xfc; 447 if (sc->sc_pcie) 448 addr |= (reg & 0xf00) << 16; 449 450 mtx_lock_spin(&sc->sc_cfg_mtx); 451 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 452 453 switch (bytes) { 454 case 1: 455 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 456 REG_CFG_DATA + (reg & 3)); 457 break; 458 case 2: 459 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 460 REG_CFG_DATA + (reg & 2))); 461 break; 462 case 4: 463 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 464 REG_CFG_DATA)); 465 break; 466 default: 467 data = ~0; 468 break; 469 } 470 mtx_unlock_spin(&sc->sc_cfg_mtx); 471 return (data); 472 } 473 474 static void 475 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 476 u_int reg, uint32_t data, int bytes) 477 { 478 uint32_t addr; 479 480 addr = CONFIG_ACCESS_ENABLE; 481 addr |= (bus & 0xff) << 16; 482 addr |= (slot & 0x1f) << 11; 483 addr |= (func & 0x7) << 8; 484 addr |= reg & 0xfc; 485 if (sc->sc_pcie) 486 addr |= (reg & 0xf00) << 16; 487 488 mtx_lock_spin(&sc->sc_cfg_mtx); 489 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 490 491 switch (bytes) { 492 case 1: 493 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 494 REG_CFG_DATA + (reg & 3), data); 495 break; 496 case 2: 497 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 498 REG_CFG_DATA + (reg & 2), htole16(data)); 499 break; 500 case 4: 501 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 502 REG_CFG_DATA, htole32(data)); 503 break; 504 } 505 mtx_unlock_spin(&sc->sc_cfg_mtx); 506 } 507 508 #if 0 509 static void 510 dump(struct fsl_pcib_softc *sc) 511 { 512 unsigned int i; 513 514 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 515 for (i = 0; i < 5; i++) { 516 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 517 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 518 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 519 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 520 } 521 printf("\n"); 522 for (i = 1; i < 4; i++) { 523 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 524 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 525 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 526 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 527 } 528 printf("\n"); 529 #undef RD 530 531 for (i = 0; i < 0x48; i += 4) { 532 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 533 i, 4)); 534 } 535 } 536 #endif 537 538 static int 539 fsl_pcib_maxslots(device_t dev) 540 { 541 struct fsl_pcib_softc *sc = device_get_softc(dev); 542 543 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 544 } 545 546 static uint32_t 547 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 548 u_int reg, int bytes) 549 { 550 struct fsl_pcib_softc *sc = device_get_softc(dev); 551 552 if (bus == sc->sc_busnr && !sc->sc_pcie && 553 slot < PCI_SLOT_FIRST) 554 return (~0); 555 556 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 557 } 558 559 static void 560 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 561 u_int reg, uint32_t val, int bytes) 562 { 563 struct fsl_pcib_softc *sc = device_get_softc(dev); 564 565 if (bus == sc->sc_busnr && !sc->sc_pcie && 566 slot < PCI_SLOT_FIRST) 567 return; 568 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 569 } 570 571 static void 572 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 573 uint64_t size, uint64_t pci_start) 574 { 575 uint32_t attr, bar, tar; 576 577 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 578 579 attr = PIWAR_EN; 580 581 switch (tgt) { 582 case -1: 583 attr &= ~PIWAR_EN; 584 break; 585 case PIWAR_TRGT_LOCAL: 586 attr |= (ffsl(size) - 2); 587 default: 588 attr |= (tgt << PIWAR_TRGT_S); 589 break; 590 } 591 tar = start >> 12; 592 bar = pci_start >> 12; 593 594 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 595 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 596 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 597 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 598 } 599 600 static void 601 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 602 uint64_t size, uint64_t pci_start) 603 { 604 uint32_t attr, bar, tar; 605 606 switch (res) { 607 case SYS_RES_MEMORY: 608 attr = 0x80044000 | (ffsll(size) - 2); 609 break; 610 case SYS_RES_IOPORT: 611 attr = 0x80088000 | (ffsll(size) - 2); 612 break; 613 default: 614 attr = 0x0004401f; 615 break; 616 } 617 bar = start >> 12; 618 tar = pci_start >> 12; 619 620 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 621 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 622 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 623 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 624 } 625 626 static void 627 fsl_pcib_err_init(device_t dev) 628 { 629 struct fsl_pcib_softc *sc; 630 uint16_t sec_stat, dsr; 631 uint32_t dcr, err_en; 632 633 sc = device_get_softc(dev); 634 635 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 636 if (sec_stat) 637 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 638 if (sc->sc_pcie) { 639 /* Clear error bits */ 640 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 641 0xffffffff); 642 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 643 0xffffffff); 644 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 645 0xffffffff); 646 647 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 648 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 649 if (dsr) 650 fsl_pcib_cfgwrite(sc, 0, 0, 0, 651 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 652 0xffff, 2); 653 654 /* Enable all errors reporting */ 655 err_en = 0x00bfff00; 656 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 657 err_en); 658 659 /* Enable error reporting: URR, FER, NFER */ 660 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 661 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 662 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 663 PCIEM_CTL_NFER_ENABLE; 664 fsl_pcib_cfgwrite(sc, 0, 0, 0, 665 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 666 } 667 } 668 669 static int 670 fsl_pcib_detach(device_t dev) 671 { 672 struct fsl_pcib_softc *sc; 673 674 sc = device_get_softc(dev); 675 676 mtx_destroy(&sc->sc_cfg_mtx); 677 678 return (bus_generic_detach(dev)); 679 } 680 681 static int 682 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 683 { 684 device_t dev; 685 int error, i, trgt; 686 687 dev = sc->sc_dev; 688 689 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 690 691 /* 692 * Configure LAW decode windows. 693 */ 694 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 695 &sc->sc_ioport_target); 696 if (error != 0) { 697 device_printf(dev, "could not retrieve PCI LAW target info\n"); 698 return (error); 699 } 700 701 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 702 switch (sc->pci_sc.sc_range[i].pci_hi & 703 OFW_PCI_PHYS_HI_SPACEMASK) { 704 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 705 continue; 706 case OFW_PCI_PHYS_HI_SPACE_IO: 707 trgt = sc->sc_ioport_target; 708 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 709 sc->pci_sc.sc_range[i].host, 710 sc->pci_sc.sc_range[i].size, 711 sc->pci_sc.sc_range[i].pci); 712 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 713 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 714 sc->pci_sc.sc_range[i].size - 1; 715 break; 716 case OFW_PCI_PHYS_HI_SPACE_MEM32: 717 case OFW_PCI_PHYS_HI_SPACE_MEM64: 718 trgt = sc->sc_iomem_target; 719 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 720 sc->pci_sc.sc_range[i].host, 721 sc->pci_sc.sc_range[i].size, 722 sc->pci_sc.sc_range[i].pci); 723 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 724 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 725 sc->pci_sc.sc_range[i].size - 1; 726 break; 727 default: 728 panic("Unknown range type %#x\n", 729 sc->pci_sc.sc_range[i].pci_hi & 730 OFW_PCI_PHYS_HI_SPACEMASK); 731 } 732 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 733 sc->pci_sc.sc_range[i].size); 734 if (error != 0) { 735 device_printf(dev, "could not program LAW for range " 736 "%d\n", i); 737 return (error); 738 } 739 } 740 741 /* 742 * Set outbout and inbound windows. 743 */ 744 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 745 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 746 747 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 748 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 749 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0, 750 ptoa(Maxmem), 0); 751 752 /* Direct-map the CCSR for MSIs. */ 753 /* Freescale PCIe 2.x has a dedicated MSI window. */ 754 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */ 755 if (sc->sc_ip_maj >= 2) 756 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa, 757 ccsrbar_size, ccsrbar_pa); 758 else 759 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa, 760 ccsrbar_size, ccsrbar_pa); 761 762 return (0); 763 } 764 765 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 766 int count, int maxcount, int *irqs) 767 { 768 vmem_addr_t start; 769 int err, i; 770 771 if (msi_vmem == NULL) 772 return (ENODEV); 773 774 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0, 775 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 776 777 if (err) 778 return (err); 779 780 for (i = 0; i < count; i++) 781 irqs[i] = start + i; 782 783 return (0); 784 } 785 786 static int fsl_pcib_release_msi(device_t dev, device_t child, 787 int count, int *irqs) 788 { 789 if (msi_vmem == NULL) 790 return (ENODEV); 791 792 vmem_xfree(msi_vmem, irqs[0], count); 793 return (0); 794 } 795 796 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq) 797 { 798 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq)); 799 } 800 801 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq) 802 { 803 return (fsl_pcib_release_msi(dev, child, 1, &irq)); 804 } 805 806 static int fsl_pcib_map_msi(device_t dev, device_t child, 807 int irq, uint64_t *addr, uint32_t *data) 808 { 809 struct fsl_msi_map *mp; 810 811 SLIST_FOREACH(mp, &fsl_msis, slist) { 812 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS) 813 break; 814 } 815 816 if (mp == NULL) 817 return (ENODEV); 818 819 *data = (irq & 255); 820 *addr = ccsrbar_pa + mp->target; 821 822 return (0); 823 } 824 825 /* 826 * Linux device trees put the msi@<x> as children of the SoC, with ranges based 827 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between 828 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC 829 * driver just to allocate a subregion for a sibling driver). This driver will 830 * use ccsr_write() and ccsr_read() instead. 831 */ 832 833 #define FSL_NUM_IRQS 8 834 #define FSL_NUM_MSI_PER_IRQ 32 835 #define FSL_MSI_TARGET 0x140 836 837 struct fsl_msi_softc { 838 vm_offset_t sc_base; 839 vm_offset_t sc_target; 840 int sc_msi_base_irq; 841 struct fsl_msi_map sc_map; 842 struct fsl_msi_irq { 843 /* This struct gets passed as the filter private data. */ 844 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */ 845 struct resource *res; 846 int irq; 847 void *cookie; 848 int vectors[FSL_NUM_MSI_PER_IRQ]; 849 vm_offset_t reg; 850 } sc_msi_irq[FSL_NUM_IRQS]; 851 }; 852 853 static int 854 fsl_msi_intr_filter(void *priv) 855 { 856 struct fsl_msi_irq *data = priv; 857 uint32_t reg; 858 int i; 859 860 reg = ccsr_read4(ccsrbar_va + data->reg); 861 i = 0; 862 while (reg != 0) { 863 if (reg & 1) 864 powerpc_dispatch_intr(data->vectors[i], NULL); 865 reg >>= 1; 866 i++; 867 } 868 869 return (FILTER_HANDLED); 870 } 871 872 static int 873 fsl_msi_probe(device_t dev) 874 { 875 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi")) 876 return (ENXIO); 877 878 device_set_desc(dev, "Freescale MSI"); 879 880 return (BUS_PROBE_DEFAULT); 881 } 882 883 static int 884 fsl_msi_attach(device_t dev) 885 { 886 struct fsl_msi_softc *sc; 887 struct fsl_msi_irq *irq; 888 int i; 889 890 sc = device_get_softc(dev); 891 892 if (msi_vmem == NULL) 893 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK); 894 895 /* Manually play with resource entries. */ 896 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); 897 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1); 898 899 if (sc->sc_map.target == 0) 900 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET; 901 902 for (i = 0; i < FSL_NUM_IRQS; i++) { 903 irq = &sc->sc_msi_irq[i]; 904 irq->irq = i; 905 irq->reg = sc->sc_base + 16 * i; 906 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 907 &irq->irq, RF_ACTIVE); 908 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE, 909 fsl_msi_intr_filter, NULL, irq, &irq->cookie); 910 } 911 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev), 912 FSL_NUM_MSIS, 0, 0); 913 914 /* Let vmem and the IRQ subsystem work their magic for allocations. */ 915 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK); 916 917 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist); 918 919 return (0); 920 } 921 922 static void 923 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv) 924 { 925 struct fsl_msi_softc *sc; 926 struct fsl_msi_irq *irqd; 927 928 sc = device_get_softc(dev); 929 930 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ]; 931 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector; 932 } 933 934 static device_method_t fsl_msi_methods[] = { 935 DEVMETHOD(device_probe, fsl_msi_probe), 936 DEVMETHOD(device_attach, fsl_msi_attach), 937 938 DEVMETHOD(pic_enable, fsl_msi_enable), 939 DEVMETHOD_END 940 }; 941 942 static driver_t fsl_msi_driver = { 943 "fsl_msi", 944 fsl_msi_methods, 945 sizeof(struct fsl_msi_softc) 946 }; 947 948 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0, 949 BUS_PASS_INTERRUPT + 1); 950