1 /*- 2 * Copyright 2006-2007 by Juniper Networks. 3 * Copyright 2008 Semihalf. 4 * Copyright 2010 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Semihalf 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ktr.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/socket.h> 48 #include <sys/queue.h> 49 #include <sys/bus.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcib_private.h> 64 65 #include <powerpc/ofw/ofw_pci.h> 66 67 #include "ofw_bus_if.h" 68 #include "pcib_if.h" 69 70 #include <machine/resource.h> 71 #include <machine/bus.h> 72 #include <machine/intr_machdep.h> 73 74 #include <powerpc/mpc85xx/mpc85xx.h> 75 76 #define REG_CFG_ADDR 0x0000 77 #define CONFIG_ACCESS_ENABLE 0x80000000 78 79 #define REG_CFG_DATA 0x0004 80 #define REG_INT_ACK 0x0008 81 82 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 83 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 84 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 85 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 86 87 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 88 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 89 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 90 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 91 92 #define REG_PEX_MES_DR 0x0020 93 #define REG_PEX_MES_IER 0x0028 94 #define REG_PEX_ERR_DR 0x0e00 95 #define REG_PEX_ERR_EN 0x0e08 96 97 #define PCIR_LTSSM 0x404 98 #define LTSSM_STAT_L0 0x16 99 100 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 101 102 struct fsl_pcib_softc { 103 struct ofw_pci_softc pci_sc; 104 device_t sc_dev; 105 106 int sc_iomem_target; 107 bus_addr_t sc_iomem_start, sc_iomem_end; 108 int sc_ioport_target; 109 bus_addr_t sc_ioport_start, sc_ioport_end; 110 111 struct resource *sc_res; 112 bus_space_handle_t sc_bsh; 113 bus_space_tag_t sc_bst; 114 int sc_rid; 115 116 int sc_busnr; 117 int sc_pcie; 118 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 119 120 /* Devices that need special attention. */ 121 int sc_devfn_tundra; 122 int sc_devfn_via_ide; 123 }; 124 125 /* Local forward declerations. */ 126 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 127 u_int, int); 128 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 129 u_int, uint32_t, int); 130 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 131 static void fsl_pcib_err_init(device_t); 132 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 133 uint64_t, uint64_t); 134 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 135 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 136 uint64_t, uint64_t); 137 138 /* Forward declerations. */ 139 static int fsl_pcib_attach(device_t); 140 static int fsl_pcib_detach(device_t); 141 static int fsl_pcib_probe(device_t); 142 143 static int fsl_pcib_maxslots(device_t); 144 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 145 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 146 uint32_t, int); 147 148 /* Configuration r/w mutex. */ 149 struct mtx pcicfg_mtx; 150 static int mtx_initialized = 0; 151 152 /* 153 * Bus interface definitions. 154 */ 155 static device_method_t fsl_pcib_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, fsl_pcib_probe), 158 DEVMETHOD(device_attach, fsl_pcib_attach), 159 DEVMETHOD(device_detach, fsl_pcib_detach), 160 161 /* pcib interface */ 162 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 163 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 164 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 165 166 DEVMETHOD_END 167 }; 168 169 static devclass_t fsl_pcib_devclass; 170 171 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 172 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 173 DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0); 174 175 static int 176 fsl_pcib_probe(device_t dev) 177 { 178 179 if (ofw_bus_get_type(dev) == NULL || 180 strcmp(ofw_bus_get_type(dev), "pci") != 0) 181 return (ENXIO); 182 183 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 184 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 185 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 186 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 187 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 188 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 189 return (ENXIO); 190 191 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 192 return (BUS_PROBE_DEFAULT); 193 } 194 195 static int 196 fsl_pcib_attach(device_t dev) 197 { 198 struct fsl_pcib_softc *sc; 199 phandle_t node; 200 uint32_t cfgreg; 201 int maxslot, error; 202 uint8_t ltssm, capptr; 203 204 sc = device_get_softc(dev); 205 sc->sc_dev = dev; 206 207 sc->sc_rid = 0; 208 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 209 RF_ACTIVE); 210 if (sc->sc_res == NULL) { 211 device_printf(dev, "could not map I/O memory\n"); 212 return (ENXIO); 213 } 214 sc->sc_bst = rman_get_bustag(sc->sc_res); 215 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 216 sc->sc_busnr = 0; 217 218 if (!mtx_initialized) { 219 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 220 mtx_initialized = 1; 221 } 222 223 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 224 if (cfgreg != 0x1057 && cfgreg != 0x1957) 225 goto err; 226 227 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 228 while (capptr != 0) { 229 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 230 switch (cfgreg & 0xff) { 231 case PCIY_PCIX: 232 break; 233 case PCIY_EXPRESS: 234 sc->sc_pcie = 1; 235 sc->sc_pcie_capreg = capptr; 236 break; 237 } 238 capptr = (cfgreg >> 8) & 0xff; 239 } 240 241 node = ofw_bus_get_node(dev); 242 243 /* 244 * Initialize generic OF PCI interface (ranges, etc.) 245 */ 246 247 error = ofw_pci_init(dev); 248 if (error) 249 return (error); 250 251 /* 252 * Configure decode windows for PCI(E) access. 253 */ 254 if (fsl_pcib_decode_win(node, sc) != 0) 255 goto err; 256 257 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 258 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 259 PCIM_CMD_PORTEN; 260 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 261 262 sc->sc_devfn_tundra = -1; 263 sc->sc_devfn_via_ide = -1; 264 265 266 /* 267 * Scan bus using firmware configured, 0 based bus numbering. 268 */ 269 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 270 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 271 272 if (sc->sc_pcie) { 273 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 274 if (ltssm < LTSSM_STAT_L0) { 275 if (bootverbose) 276 printf("PCI %d: no PCIE link, skipping\n", 277 device_get_unit(dev)); 278 return (0); 279 } 280 } 281 282 fsl_pcib_err_init(dev); 283 284 return (ofw_pci_attach(dev)); 285 286 err: 287 return (ENXIO); 288 } 289 290 static uint32_t 291 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 292 u_int reg, int bytes) 293 { 294 uint32_t addr, data; 295 296 addr = CONFIG_ACCESS_ENABLE; 297 addr |= (bus & 0xff) << 16; 298 addr |= (slot & 0x1f) << 11; 299 addr |= (func & 0x7) << 8; 300 addr |= reg & 0xfc; 301 if (sc->sc_pcie) 302 addr |= (reg & 0xf00) << 16; 303 304 mtx_lock_spin(&pcicfg_mtx); 305 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 306 307 switch (bytes) { 308 case 1: 309 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 310 REG_CFG_DATA + (reg & 3)); 311 break; 312 case 2: 313 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 314 REG_CFG_DATA + (reg & 2))); 315 break; 316 case 4: 317 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 318 REG_CFG_DATA)); 319 break; 320 default: 321 data = ~0; 322 break; 323 } 324 mtx_unlock_spin(&pcicfg_mtx); 325 return (data); 326 } 327 328 static void 329 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 330 u_int reg, uint32_t data, int bytes) 331 { 332 uint32_t addr; 333 334 addr = CONFIG_ACCESS_ENABLE; 335 addr |= (bus & 0xff) << 16; 336 addr |= (slot & 0x1f) << 11; 337 addr |= (func & 0x7) << 8; 338 addr |= reg & 0xfc; 339 if (sc->sc_pcie) 340 addr |= (reg & 0xf00) << 16; 341 342 mtx_lock_spin(&pcicfg_mtx); 343 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 344 345 switch (bytes) { 346 case 1: 347 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 348 REG_CFG_DATA + (reg & 3), data); 349 break; 350 case 2: 351 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 352 REG_CFG_DATA + (reg & 2), htole16(data)); 353 break; 354 case 4: 355 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 356 REG_CFG_DATA, htole32(data)); 357 break; 358 } 359 mtx_unlock_spin(&pcicfg_mtx); 360 } 361 362 #if 0 363 static void 364 dump(struct fsl_pcib_softc *sc) 365 { 366 unsigned int i; 367 368 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 369 for (i = 0; i < 5; i++) { 370 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 371 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 372 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 373 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 374 } 375 printf("\n"); 376 for (i = 1; i < 4; i++) { 377 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 378 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 379 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 380 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 381 } 382 printf("\n"); 383 #undef RD 384 385 for (i = 0; i < 0x48; i += 4) { 386 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 387 i, 4)); 388 } 389 } 390 #endif 391 392 static int 393 fsl_pcib_maxslots(device_t dev) 394 { 395 struct fsl_pcib_softc *sc = device_get_softc(dev); 396 397 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 398 } 399 400 static uint32_t 401 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 402 u_int reg, int bytes) 403 { 404 struct fsl_pcib_softc *sc = device_get_softc(dev); 405 u_int devfn; 406 407 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 408 return (~0); 409 devfn = DEVFN(bus, slot, func); 410 if (devfn == sc->sc_devfn_tundra) 411 return (~0); 412 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 413 return (1); 414 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 415 } 416 417 static void 418 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 419 u_int reg, uint32_t val, int bytes) 420 { 421 struct fsl_pcib_softc *sc = device_get_softc(dev); 422 423 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 424 return; 425 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 426 } 427 428 static void 429 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 430 int slot, int fn) 431 { 432 433 if (device == 0x0686) { 434 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 435 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 436 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 437 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 438 } else if (device == 0x0571) { 439 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 440 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 441 } 442 } 443 444 static int 445 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 446 { 447 int secbus; 448 int old_pribus, old_secbus, old_subbus; 449 int new_pribus, new_secbus, new_subbus; 450 int slot, func, maxfunc; 451 uint16_t vendor, device; 452 uint8_t command, hdrtype, subclass; 453 454 secbus = bus; 455 for (slot = 0; slot <= maxslot; slot++) { 456 maxfunc = 0; 457 for (func = 0; func <= maxfunc; func++) { 458 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 459 func, PCIR_HDRTYPE, 1); 460 461 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 462 continue; 463 464 if (func == 0 && (hdrtype & PCIM_MFDEV)) 465 maxfunc = PCI_FUNCMAX; 466 467 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 468 func, PCIR_VENDOR, 2); 469 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 470 func, PCIR_DEVICE, 2); 471 472 if (vendor == 0x1957 && device == 0x3fff) { 473 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 474 continue; 475 } 476 477 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 478 func, PCIR_COMMAND, 1); 479 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 480 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 481 PCIR_COMMAND, command, 1); 482 483 if (vendor == 0x1106) 484 fsl_pcib_init_via(sc, device, bus, slot, func); 485 486 /* 487 * Handle PCI-PCI bridges 488 */ 489 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 490 func, PCIR_SUBCLASS, 1); 491 492 /* Allow all DEVTYPE 1 devices */ 493 if (hdrtype != PCIM_HDRTYPE_BRIDGE) 494 continue; 495 496 secbus++; 497 498 /* Read currect bus register configuration */ 499 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 500 slot, func, PCIR_PRIBUS_1, 1); 501 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 502 slot, func, PCIR_SECBUS_1, 1); 503 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 504 slot, func, PCIR_SUBBUS_1, 1); 505 506 if (bootverbose) 507 printf("PCI: reading firmware bus numbers for " 508 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 509 secbus, old_pribus, old_secbus, old_subbus); 510 511 new_pribus = bus; 512 new_secbus = secbus; 513 514 secbus = fsl_pcib_init(sc, secbus, 515 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 516 517 new_subbus = secbus; 518 519 if (bootverbose) 520 printf("PCI: translate firmware bus numbers " 521 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 522 secbus, old_pribus, old_secbus, old_subbus, 523 new_pribus, new_secbus, new_subbus); 524 525 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 526 PCIR_PRIBUS_1, new_pribus, 1); 527 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 528 PCIR_SECBUS_1, new_secbus, 1); 529 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 530 PCIR_SUBBUS_1, new_subbus, 1); 531 } 532 } 533 534 return (secbus); 535 } 536 537 static void 538 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 539 uint64_t size, uint64_t pci_start) 540 { 541 uint32_t attr, bar, tar; 542 543 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 544 545 switch (tgt) { 546 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 547 case OCP85XX_TGTIF_RAM1: 548 attr = 0xa0f55000 | (ffsl(size) - 2); 549 break; 550 default: 551 attr = 0; 552 break; 553 } 554 tar = start >> 12; 555 bar = pci_start >> 12; 556 557 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 558 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 559 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 560 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 561 } 562 563 static void 564 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 565 uint64_t size, uint64_t pci_start) 566 { 567 uint32_t attr, bar, tar; 568 569 switch (res) { 570 case SYS_RES_MEMORY: 571 attr = 0x80044000 | (ffsll(size) - 2); 572 break; 573 case SYS_RES_IOPORT: 574 attr = 0x80088000 | (ffsll(size) - 2); 575 break; 576 default: 577 attr = 0x0004401f; 578 break; 579 } 580 bar = start >> 12; 581 tar = pci_start >> 12; 582 583 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 584 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 585 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 586 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 587 } 588 589 590 static void 591 fsl_pcib_err_init(device_t dev) 592 { 593 struct fsl_pcib_softc *sc; 594 uint16_t sec_stat, dsr; 595 uint32_t dcr, err_en; 596 597 sc = device_get_softc(dev); 598 599 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 600 if (sec_stat) 601 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 602 if (sc->sc_pcie) { 603 /* Clear error bits */ 604 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 605 0xffffffff); 606 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 607 0xffffffff); 608 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 609 0xffffffff); 610 611 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 612 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 613 if (dsr) 614 fsl_pcib_cfgwrite(sc, 0, 0, 0, 615 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 616 0xffff, 2); 617 618 /* Enable all errors reporting */ 619 err_en = 0x00bfff00; 620 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 621 err_en); 622 623 /* Enable error reporting: URR, FER, NFER */ 624 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 625 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 626 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 627 PCIEM_CTL_NFER_ENABLE; 628 fsl_pcib_cfgwrite(sc, 0, 0, 0, 629 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 630 } 631 } 632 633 static int 634 fsl_pcib_detach(device_t dev) 635 { 636 637 if (mtx_initialized) { 638 mtx_destroy(&pcicfg_mtx); 639 mtx_initialized = 0; 640 } 641 return (bus_generic_detach(dev)); 642 } 643 644 static int 645 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 646 { 647 device_t dev; 648 int error, i, trgt; 649 650 dev = sc->sc_dev; 651 652 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 653 654 /* 655 * Configure LAW decode windows. 656 */ 657 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 658 &sc->sc_ioport_target); 659 if (error != 0) { 660 device_printf(dev, "could not retrieve PCI LAW target info\n"); 661 return (error); 662 } 663 664 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 665 switch (sc->pci_sc.sc_range[i].pci_hi & 666 OFW_PCI_PHYS_HI_SPACEMASK) { 667 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 668 continue; 669 case OFW_PCI_PHYS_HI_SPACE_IO: 670 trgt = sc->sc_ioport_target; 671 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 672 sc->pci_sc.sc_range[i].host, 673 sc->pci_sc.sc_range[i].size, 674 sc->pci_sc.sc_range[i].pci); 675 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 676 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 677 sc->pci_sc.sc_range[i].size - 1; 678 break; 679 case OFW_PCI_PHYS_HI_SPACE_MEM32: 680 case OFW_PCI_PHYS_HI_SPACE_MEM64: 681 trgt = sc->sc_iomem_target; 682 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 683 sc->pci_sc.sc_range[i].host, 684 sc->pci_sc.sc_range[i].size, 685 sc->pci_sc.sc_range[i].pci); 686 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 687 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 688 sc->pci_sc.sc_range[i].size - 1; 689 break; 690 default: 691 panic("Unknown range type %#x\n", 692 sc->pci_sc.sc_range[i].pci_hi & 693 OFW_PCI_PHYS_HI_SPACEMASK); 694 } 695 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 696 sc->pci_sc.sc_range[i].size); 697 if (error != 0) { 698 device_printf(dev, "could not program LAW for range " 699 "%d\n", i); 700 return (error); 701 } 702 } 703 704 /* 705 * Set outbout and inbound windows. 706 */ 707 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 708 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 709 710 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 711 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 712 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 713 2U * 1024U * 1024U * 1024U, 0); 714 715 return (0); 716 } 717