xref: /freebsd/sys/powerpc/mpc85xx/pci_mpc85xx.c (revision 6087140822b82f3a20ab763fd8050809efc272c3)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright 2006-2007 by Juniper Networks.
5  * Copyright 2008 Semihalf.
6  * Copyright 2010 The FreeBSD Foundation
7  * All rights reserved.
8  *
9  * Portions of this software were developed by Semihalf
10  * under sponsorship from the FreeBSD Foundation.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
36  */
37 
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/ktr.h>
44 #include <sys/sockio.h>
45 #include <sys/mbuf.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/queue.h>
51 #include <sys/bus.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/rman.h>
55 #include <sys/endian.h>
56 
57 #include <vm/vm.h>
58 #include <vm/pmap.h>
59 
60 #include <dev/ofw/ofw_pci.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/ofw/ofwpci.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcib_private.h>
67 
68 #include "ofw_bus_if.h"
69 #include "pcib_if.h"
70 
71 #include <machine/resource.h>
72 #include <machine/bus.h>
73 #include <machine/intr_machdep.h>
74 
75 #include <powerpc/mpc85xx/mpc85xx.h>
76 
77 #define	REG_CFG_ADDR	0x0000
78 #define	CONFIG_ACCESS_ENABLE	0x80000000
79 
80 #define	REG_CFG_DATA	0x0004
81 #define	REG_INT_ACK	0x0008
82 
83 #define	REG_POTAR(n)	(0x0c00 + 0x20 * (n))
84 #define	REG_POTEAR(n)	(0x0c04 + 0x20 * (n))
85 #define	REG_POWBAR(n)	(0x0c08 + 0x20 * (n))
86 #define	REG_POWAR(n)	(0x0c10 + 0x20 * (n))
87 
88 #define	REG_PITAR(n)	(0x0e00 - 0x20 * (n))
89 #define	REG_PIWBAR(n)	(0x0e08 - 0x20 * (n))
90 #define	REG_PIWBEAR(n)	(0x0e0c - 0x20 * (n))
91 #define	REG_PIWAR(n)	(0x0e10 - 0x20 * (n))
92 
93 #define	REG_PEX_MES_DR	0x0020
94 #define	REG_PEX_MES_IER	0x0028
95 #define	REG_PEX_ERR_DR	0x0e00
96 #define	REG_PEX_ERR_EN	0x0e08
97 
98 #define	REG_PEX_ERR_DR		0x0e00
99 #define	REG_PEX_ERR_DR_ME	0x80000000
100 #define	REG_PEX_ERR_DR_PCT	0x800000
101 #define	REG_PEX_ERR_DR_PAT	0x400000
102 #define	REG_PEX_ERR_DR_PCAC	0x200000
103 #define	REG_PEX_ERR_DR_PNM	0x100000
104 #define	REG_PEX_ERR_DR_CDNSC	0x80000
105 #define	REG_PEX_ERR_DR_CRSNC	0x40000
106 #define	REG_PEX_ERR_DR_ICCA	0x20000
107 #define	REG_PEX_ERR_DR_IACA	0x10000
108 #define	REG_PEX_ERR_DR_CRST	0x8000
109 #define	REG_PEX_ERR_DR_MIS	0x4000
110 #define	REG_PEX_ERR_DR_IOIS	0x2000
111 #define	REG_PEX_ERR_DR_CIS	0x1000
112 #define	REG_PEX_ERR_DR_CIEP	0x800
113 #define	REG_PEX_ERR_DR_IOIEP	0x400
114 #define	REG_PEX_ERR_DR_OAC	0x200
115 #define	REG_PEX_ERR_DR_IOIA	0x100
116 #define	REG_PEX_ERR_DR_IMBA	0x80
117 #define	REG_PEX_ERR_DR_IIOBA	0x40
118 #define	REG_PEX_ERR_DR_LDDE	0x20
119 #define	REG_PEX_ERR_EN		0x0e08
120 
121 #define PCIR_LTSSM	0x404
122 #define LTSSM_STAT_L0	0x16
123 
124 #define	DEVFN(b, s, f)	((b << 16) | (s << 8) | f)
125 
126 struct fsl_pcib_softc {
127 	struct ofw_pci_softc pci_sc;
128 	device_t	sc_dev;
129 	struct mtx	sc_cfg_mtx;
130 
131 	int		sc_iomem_target;
132 	bus_addr_t	sc_iomem_start, sc_iomem_end;
133 	int		sc_ioport_target;
134 	bus_addr_t	sc_ioport_start, sc_ioport_end;
135 
136 	struct resource *sc_res;
137 	bus_space_handle_t sc_bsh;
138 	bus_space_tag_t	sc_bst;
139 	int		sc_rid;
140 
141 	struct resource	*sc_irq_res;
142 	void		*sc_ih;
143 
144 	int		sc_busnr;
145 	int		sc_pcie;
146 	uint8_t		sc_pcie_capreg;		/* PCI-E Capability Reg Set */
147 };
148 
149 struct fsl_pcib_err_dr {
150 	const char	*msg;
151 	uint32_t	err_dr_mask;
152 };
153 
154 static const struct fsl_pcib_err_dr pci_err[] = {
155 	{"ME",		REG_PEX_ERR_DR_ME},
156 	{"PCT",		REG_PEX_ERR_DR_PCT},
157 	{"PAT",		REG_PEX_ERR_DR_PAT},
158 	{"PCAC",	REG_PEX_ERR_DR_PCAC},
159 	{"PNM",		REG_PEX_ERR_DR_PNM},
160 	{"CDNSC",	REG_PEX_ERR_DR_CDNSC},
161 	{"CRSNC",	REG_PEX_ERR_DR_CRSNC},
162 	{"ICCA",	REG_PEX_ERR_DR_ICCA},
163 	{"IACA",	REG_PEX_ERR_DR_IACA},
164 	{"CRST",	REG_PEX_ERR_DR_CRST},
165 	{"MIS",		REG_PEX_ERR_DR_MIS},
166 	{"IOIS",	REG_PEX_ERR_DR_IOIS},
167 	{"CIS",		REG_PEX_ERR_DR_CIS},
168 	{"CIEP",	REG_PEX_ERR_DR_CIEP},
169 	{"IOIEP",	REG_PEX_ERR_DR_IOIEP},
170 	{"OAC",		REG_PEX_ERR_DR_OAC},
171 	{"IOIA",	REG_PEX_ERR_DR_IOIA},
172 	{"IMBA",	REG_PEX_ERR_DR_IMBA},
173 	{"IIOBA",	REG_PEX_ERR_DR_IIOBA},
174 	{"LDDE",	REG_PEX_ERR_DR_LDDE}
175 };
176 
177 /* Local forward declerations. */
178 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
179     u_int, int);
180 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
181     u_int, uint32_t, int);
182 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
183 static void fsl_pcib_err_init(device_t);
184 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
185     uint64_t, uint64_t);
186 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
187     uint64_t, uint64_t);
188 
189 /* Forward declerations. */
190 static int fsl_pcib_attach(device_t);
191 static int fsl_pcib_detach(device_t);
192 static int fsl_pcib_probe(device_t);
193 
194 static int fsl_pcib_maxslots(device_t);
195 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
196 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
197     uint32_t, int);
198 
199 /*
200  * Bus interface definitions.
201  */
202 static device_method_t fsl_pcib_methods[] = {
203 	/* Device interface */
204 	DEVMETHOD(device_probe,		fsl_pcib_probe),
205 	DEVMETHOD(device_attach,	fsl_pcib_attach),
206 	DEVMETHOD(device_detach,	fsl_pcib_detach),
207 
208 	/* pcib interface */
209 	DEVMETHOD(pcib_maxslots,	fsl_pcib_maxslots),
210 	DEVMETHOD(pcib_read_config,	fsl_pcib_read_config),
211 	DEVMETHOD(pcib_write_config,	fsl_pcib_write_config),
212 
213 	DEVMETHOD_END
214 };
215 
216 static devclass_t fsl_pcib_devclass;
217 
218 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
219     sizeof(struct fsl_pcib_softc), ofw_pci_driver);
220 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0,
221     BUS_PASS_BUS);
222 
223 static void
224 fsl_pcib_err_intr(void *v)
225 {
226 	struct fsl_pcib_softc *sc;
227 	device_t dev;
228 	uint32_t err_reg, clear_reg;
229 	uint8_t i;
230 
231 	dev = (device_t)v;
232 	sc = device_get_softc(dev);
233 
234 	clear_reg = 0;
235 	err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);
236 
237 	/* Check which one error occurred */
238 	for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) {
239 		if (err_reg & pci_err[i].err_dr_mask) {
240 			device_printf(dev, "PCI %d: report %s error\n",
241 			    device_get_unit(dev), pci_err[i].msg);
242 			clear_reg |= pci_err[i].err_dr_mask;
243 		}
244 	}
245 
246 	/* Clear pending errors */
247 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);
248 }
249 
250 static int
251 fsl_pcib_probe(device_t dev)
252 {
253 
254 	if (ofw_bus_get_type(dev) == NULL ||
255 	    strcmp(ofw_bus_get_type(dev), "pci") != 0)
256 		return (ENXIO);
257 
258 	if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
259 	    ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
260 	    ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||
261 	    ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||
262 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||
263 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))
264 		return (ENXIO);
265 
266 	device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
267 	return (BUS_PROBE_DEFAULT);
268 }
269 
270 static int
271 fsl_pcib_attach(device_t dev)
272 {
273 	struct fsl_pcib_softc *sc;
274 	phandle_t node;
275 	uint32_t cfgreg, brctl;
276 	int error, rid;
277 	uint8_t ltssm, capptr;
278 
279 	sc = device_get_softc(dev);
280 	sc->sc_dev = dev;
281 
282 	sc->sc_rid = 0;
283 	sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
284 	    RF_ACTIVE);
285 	if (sc->sc_res == NULL) {
286 		device_printf(dev, "could not map I/O memory\n");
287 		return (ENXIO);
288 	}
289 	sc->sc_bst = rman_get_bustag(sc->sc_res);
290 	sc->sc_bsh = rman_get_bushandle(sc->sc_res);
291 	sc->sc_busnr = 0;
292 
293 	mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);
294 
295 	cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
296 	if (cfgreg != 0x1057 && cfgreg != 0x1957)
297 		goto err;
298 
299 	capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
300 	while (capptr != 0) {
301 		cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
302 		switch (cfgreg & 0xff) {
303 		case PCIY_PCIX:
304 			break;
305 		case PCIY_EXPRESS:
306 			sc->sc_pcie = 1;
307 			sc->sc_pcie_capreg = capptr;
308 			break;
309 		}
310 		capptr = (cfgreg >> 8) & 0xff;
311 	}
312 
313 	node = ofw_bus_get_node(dev);
314 
315 	/*
316 	 * Initialize generic OF PCI interface (ranges, etc.)
317 	 */
318 
319 	error = ofw_pci_init(dev);
320 	if (error)
321 		return (error);
322 
323 	/*
324 	 * Configure decode windows for PCI(E) access.
325 	 */
326 	if (fsl_pcib_decode_win(node, sc) != 0)
327 		goto err;
328 
329 	cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
330 	cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
331 	    PCIM_CMD_PORTEN;
332 	fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
333 
334 	/* Reset the bus.  Needed for Radeon video cards. */
335 	brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
336 	    PCIR_BRIDGECTL_1, 1);
337 	brctl |= PCIB_BCR_SECBUS_RESET;
338 	fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
339 	    PCIR_BRIDGECTL_1, brctl, 1);
340 	DELAY(100000);
341 	brctl &= ~PCIB_BCR_SECBUS_RESET;
342 	fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
343 	    PCIR_BRIDGECTL_1, brctl, 1);
344 	DELAY(100000);
345 
346 	if (sc->sc_pcie) {
347 		ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
348 		if (ltssm < LTSSM_STAT_L0) {
349 			if (bootverbose)
350 				printf("PCI %d: no PCIE link, skipping\n",
351 				    device_get_unit(dev));
352 			return (0);
353 		}
354 	}
355 
356 	/* Allocate irq */
357 	rid = 0;
358 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
359 	    RF_ACTIVE | RF_SHAREABLE);
360 	if (sc->sc_irq_res == NULL) {
361 		error = fsl_pcib_detach(dev);
362 		if (error != 0) {
363 			device_printf(dev,
364 			    "Detach of the driver failed with error %d\n",
365 			    error);
366 		}
367 		return (ENXIO);
368 	}
369 
370 	/* Setup interrupt handler */
371 	error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
372 	    NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);
373 	if (error != 0) {
374 		device_printf(dev, "Could not setup irq, %d\n", error);
375 		sc->sc_ih = NULL;
376 		error = fsl_pcib_detach(dev);
377 		if (error != 0) {
378 			device_printf(dev,
379 			    "Detach of the driver failed with error %d\n",
380 			    error);
381 		}
382 		return (ENXIO);
383 	}
384 
385 	fsl_pcib_err_init(dev);
386 
387 	return (ofw_pci_attach(dev));
388 
389 err:
390 	return (ENXIO);
391 }
392 
393 static uint32_t
394 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
395     u_int reg, int bytes)
396 {
397 	uint32_t addr, data;
398 
399 	addr = CONFIG_ACCESS_ENABLE;
400 	addr |= (bus & 0xff) << 16;
401 	addr |= (slot & 0x1f) << 11;
402 	addr |= (func & 0x7) << 8;
403 	addr |= reg & 0xfc;
404 	if (sc->sc_pcie)
405 		addr |= (reg & 0xf00) << 16;
406 
407 	mtx_lock_spin(&sc->sc_cfg_mtx);
408 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
409 
410 	switch (bytes) {
411 	case 1:
412 		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
413 		    REG_CFG_DATA + (reg & 3));
414 		break;
415 	case 2:
416 		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
417 		    REG_CFG_DATA + (reg & 2)));
418 		break;
419 	case 4:
420 		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
421 		    REG_CFG_DATA));
422 		break;
423 	default:
424 		data = ~0;
425 		break;
426 	}
427 	mtx_unlock_spin(&sc->sc_cfg_mtx);
428 	return (data);
429 }
430 
431 static void
432 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
433     u_int reg, uint32_t data, int bytes)
434 {
435 	uint32_t addr;
436 
437 	addr = CONFIG_ACCESS_ENABLE;
438 	addr |= (bus & 0xff) << 16;
439 	addr |= (slot & 0x1f) << 11;
440 	addr |= (func & 0x7) << 8;
441 	addr |= reg & 0xfc;
442 	if (sc->sc_pcie)
443 		addr |= (reg & 0xf00) << 16;
444 
445 	mtx_lock_spin(&sc->sc_cfg_mtx);
446 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
447 
448 	switch (bytes) {
449 	case 1:
450 		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
451 		    REG_CFG_DATA + (reg & 3), data);
452 		break;
453 	case 2:
454 		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
455 		    REG_CFG_DATA + (reg & 2), htole16(data));
456 		break;
457 	case 4:
458 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
459 		    REG_CFG_DATA, htole32(data));
460 		break;
461 	}
462 	mtx_unlock_spin(&sc->sc_cfg_mtx);
463 }
464 
465 #if 0
466 static void
467 dump(struct fsl_pcib_softc *sc)
468 {
469 	unsigned int i;
470 
471 #define RD(o)	bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
472 	for (i = 0; i < 5; i++) {
473 		printf("POTAR%u  =0x%08x\n", i, RD(REG_POTAR(i)));
474 		printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
475 		printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
476 		printf("POWAR%u  =0x%08x\n", i, RD(REG_POWAR(i)));
477 	}
478 	printf("\n");
479 	for (i = 1; i < 4; i++) {
480 		printf("PITAR%u  =0x%08x\n", i, RD(REG_PITAR(i)));
481 		printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
482 		printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
483 		printf("PIWAR%u  =0x%08x\n", i, RD(REG_PIWAR(i)));
484 	}
485 	printf("\n");
486 #undef RD
487 
488 	for (i = 0; i < 0x48; i += 4) {
489 		printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
490 		    i, 4));
491 	}
492 }
493 #endif
494 
495 static int
496 fsl_pcib_maxslots(device_t dev)
497 {
498 	struct fsl_pcib_softc *sc = device_get_softc(dev);
499 
500 	return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
501 }
502 
503 static uint32_t
504 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
505     u_int reg, int bytes)
506 {
507 	struct fsl_pcib_softc *sc = device_get_softc(dev);
508 	u_int devfn;
509 
510 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
511 		return (~0);
512 	devfn = DEVFN(bus, slot, func);
513 
514 	return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
515 }
516 
517 static void
518 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
519     u_int reg, uint32_t val, int bytes)
520 {
521 	struct fsl_pcib_softc *sc = device_get_softc(dev);
522 
523 	if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
524 		return;
525 	fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
526 }
527 
528 static void
529 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
530     uint64_t size, uint64_t pci_start)
531 {
532 	uint32_t attr, bar, tar;
533 
534 	KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
535 
536 	switch (tgt) {
537 	/* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
538 	case OCP85XX_TGTIF_RAM1_85XX:
539 	case OCP85XX_TGTIF_RAM1_QORIQ:
540 		attr = 0xa0f55000 | (ffsl(size) - 2);
541 		break;
542 	default:
543 		attr = 0;
544 		break;
545 	}
546 	tar = start >> 12;
547 	bar = pci_start >> 12;
548 
549 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
550 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
551 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
552 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
553 }
554 
555 static void
556 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
557     uint64_t size, uint64_t pci_start)
558 {
559 	uint32_t attr, bar, tar;
560 
561 	switch (res) {
562 	case SYS_RES_MEMORY:
563 		attr = 0x80044000 | (ffsll(size) - 2);
564 		break;
565 	case SYS_RES_IOPORT:
566 		attr = 0x80088000 | (ffsll(size) - 2);
567 		break;
568 	default:
569 		attr = 0x0004401f;
570 		break;
571 	}
572 	bar = start >> 12;
573 	tar = pci_start >> 12;
574 
575 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
576 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
577 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
578 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
579 }
580 
581 
582 static void
583 fsl_pcib_err_init(device_t dev)
584 {
585 	struct fsl_pcib_softc *sc;
586 	uint16_t sec_stat, dsr;
587 	uint32_t dcr, err_en;
588 
589 	sc = device_get_softc(dev);
590 
591 	sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
592 	if (sec_stat)
593 		fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
594 	if (sc->sc_pcie) {
595 		/* Clear error bits */
596 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
597 		    0xffffffff);
598 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
599 		    0xffffffff);
600 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
601 		    0xffffffff);
602 
603 		dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
604 		    sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
605 		if (dsr)
606 			fsl_pcib_cfgwrite(sc, 0, 0, 0,
607 			    sc->sc_pcie_capreg + PCIER_DEVICE_STA,
608 			    0xffff, 2);
609 
610 		/* Enable all errors reporting */
611 		err_en = 0x00bfff00;
612 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
613 		    err_en);
614 
615 		/* Enable error reporting: URR, FER, NFER */
616 		dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
617 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
618 		dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
619 		    PCIEM_CTL_NFER_ENABLE;
620 		fsl_pcib_cfgwrite(sc, 0, 0, 0,
621 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
622 	}
623 }
624 
625 static int
626 fsl_pcib_detach(device_t dev)
627 {
628 	struct fsl_pcib_softc *sc;
629 
630 	sc = device_get_softc(dev);
631 
632 	mtx_destroy(&sc->sc_cfg_mtx);
633 
634 	return (bus_generic_detach(dev));
635 }
636 
637 static int
638 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
639 {
640 	device_t dev;
641 	int error, i, trgt;
642 
643 	dev = sc->sc_dev;
644 
645 	fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
646 
647 	/*
648 	 * Configure LAW decode windows.
649 	 */
650 	error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
651 	    &sc->sc_ioport_target);
652 	if (error != 0) {
653 		device_printf(dev, "could not retrieve PCI LAW target info\n");
654 		return (error);
655 	}
656 
657 	for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
658 		switch (sc->pci_sc.sc_range[i].pci_hi &
659 		    OFW_PCI_PHYS_HI_SPACEMASK) {
660 		case OFW_PCI_PHYS_HI_SPACE_CONFIG:
661 			continue;
662 		case OFW_PCI_PHYS_HI_SPACE_IO:
663 			trgt = sc->sc_ioport_target;
664 			fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
665 			    sc->pci_sc.sc_range[i].host,
666 			    sc->pci_sc.sc_range[i].size,
667 			    sc->pci_sc.sc_range[i].pci);
668 			sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
669 			sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
670 			    sc->pci_sc.sc_range[i].size - 1;
671 			break;
672 		case OFW_PCI_PHYS_HI_SPACE_MEM32:
673 		case OFW_PCI_PHYS_HI_SPACE_MEM64:
674 			trgt = sc->sc_iomem_target;
675 			fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
676 			    sc->pci_sc.sc_range[i].host,
677 			    sc->pci_sc.sc_range[i].size,
678 			    sc->pci_sc.sc_range[i].pci);
679 			sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
680 			sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
681 			    sc->pci_sc.sc_range[i].size - 1;
682 			break;
683 		default:
684 			panic("Unknown range type %#x\n",
685 			    sc->pci_sc.sc_range[i].pci_hi &
686 			    OFW_PCI_PHYS_HI_SPACEMASK);
687 		}
688 		error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
689 		    sc->pci_sc.sc_range[i].size);
690 		if (error != 0) {
691 			device_printf(dev, "could not program LAW for range "
692 			    "%d\n", i);
693 			return (error);
694 		}
695 	}
696 
697 	/*
698 	 * Set outbout and inbound windows.
699 	 */
700 	fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
701 	fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
702 
703 	fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
704 	fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
705 	fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
706 	    2U * 1024U * 1024U * 1024U, 0);
707 
708 	return (0);
709 }
710