1 /*- 2 * Copyright 2006-2007 by Juniper Networks. 3 * Copyright 2008 Semihalf. 4 * Copyright 2010 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Semihalf 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ktr.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/socket.h> 48 #include <sys/queue.h> 49 #include <sys/bus.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcib_private.h> 64 65 #include <powerpc/ofw/ofw_pci.h> 66 67 #include "ofw_bus_if.h" 68 #include "pcib_if.h" 69 70 #include <machine/resource.h> 71 #include <machine/bus.h> 72 #include <machine/intr_machdep.h> 73 74 #include <powerpc/mpc85xx/mpc85xx.h> 75 76 #define REG_CFG_ADDR 0x0000 77 #define CONFIG_ACCESS_ENABLE 0x80000000 78 79 #define REG_CFG_DATA 0x0004 80 #define REG_INT_ACK 0x0008 81 82 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 83 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 84 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 85 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 86 87 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 88 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 89 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 90 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 91 92 #define REG_PEX_MES_DR 0x0020 93 #define REG_PEX_MES_IER 0x0028 94 #define REG_PEX_ERR_DR 0x0e00 95 #define REG_PEX_ERR_EN 0x0e08 96 97 #define REG_PEX_ERR_DR 0x0e00 98 #define REG_PEX_ERR_DR_ME 0x80000000 99 #define REG_PEX_ERR_DR_PCT 0x800000 100 #define REG_PEX_ERR_DR_PAT 0x400000 101 #define REG_PEX_ERR_DR_PCAC 0x200000 102 #define REG_PEX_ERR_DR_PNM 0x100000 103 #define REG_PEX_ERR_DR_CDNSC 0x80000 104 #define REG_PEX_ERR_DR_CRSNC 0x40000 105 #define REG_PEX_ERR_DR_ICCA 0x20000 106 #define REG_PEX_ERR_DR_IACA 0x10000 107 #define REG_PEX_ERR_DR_CRST 0x8000 108 #define REG_PEX_ERR_DR_MIS 0x4000 109 #define REG_PEX_ERR_DR_IOIS 0x2000 110 #define REG_PEX_ERR_DR_CIS 0x1000 111 #define REG_PEX_ERR_DR_CIEP 0x800 112 #define REG_PEX_ERR_DR_IOIEP 0x400 113 #define REG_PEX_ERR_DR_OAC 0x200 114 #define REG_PEX_ERR_DR_IOIA 0x100 115 #define REG_PEX_ERR_DR_IMBA 0x80 116 #define REG_PEX_ERR_DR_IIOBA 0x40 117 #define REG_PEX_ERR_DR_LDDE 0x20 118 #define REG_PEX_ERR_EN 0x0e08 119 120 #define PCIR_LTSSM 0x404 121 #define LTSSM_STAT_L0 0x16 122 123 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 124 125 struct fsl_pcib_softc { 126 struct ofw_pci_softc pci_sc; 127 device_t sc_dev; 128 129 int sc_iomem_target; 130 bus_addr_t sc_iomem_start, sc_iomem_end; 131 int sc_ioport_target; 132 bus_addr_t sc_ioport_start, sc_ioport_end; 133 134 struct resource *sc_res; 135 bus_space_handle_t sc_bsh; 136 bus_space_tag_t sc_bst; 137 int sc_rid; 138 139 struct resource *sc_irq_res; 140 void *sc_ih; 141 142 int sc_busnr; 143 int sc_pcie; 144 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 145 146 /* Devices that need special attention. */ 147 int sc_devfn_tundra; 148 int sc_devfn_via_ide; 149 }; 150 151 struct fsl_pcib_err_dr { 152 const char *msg; 153 uint32_t err_dr_mask; 154 }; 155 156 static const struct fsl_pcib_err_dr pci_err[] = { 157 {"ME", REG_PEX_ERR_DR_ME}, 158 {"PCT", REG_PEX_ERR_DR_PCT}, 159 {"PAT", REG_PEX_ERR_DR_PAT}, 160 {"PCAC", REG_PEX_ERR_DR_PCAC}, 161 {"PNM", REG_PEX_ERR_DR_PNM}, 162 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 163 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 164 {"ICCA", REG_PEX_ERR_DR_ICCA}, 165 {"IACA", REG_PEX_ERR_DR_IACA}, 166 {"CRST", REG_PEX_ERR_DR_CRST}, 167 {"MIS", REG_PEX_ERR_DR_MIS}, 168 {"IOIS", REG_PEX_ERR_DR_IOIS}, 169 {"CIS", REG_PEX_ERR_DR_CIS}, 170 {"CIEP", REG_PEX_ERR_DR_CIEP}, 171 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 172 {"OAC", REG_PEX_ERR_DR_OAC}, 173 {"IOIA", REG_PEX_ERR_DR_IOIA}, 174 {"IMBA", REG_PEX_ERR_DR_IMBA}, 175 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 176 {"LDDE", REG_PEX_ERR_DR_LDDE} 177 }; 178 179 /* Local forward declerations. */ 180 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 181 u_int, int); 182 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 183 u_int, uint32_t, int); 184 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 185 static void fsl_pcib_err_init(device_t); 186 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 187 uint64_t, uint64_t); 188 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 189 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 190 uint64_t, uint64_t); 191 192 /* Forward declerations. */ 193 static int fsl_pcib_attach(device_t); 194 static int fsl_pcib_detach(device_t); 195 static int fsl_pcib_probe(device_t); 196 197 static int fsl_pcib_maxslots(device_t); 198 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 199 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 200 uint32_t, int); 201 202 /* Configuration r/w mutex. */ 203 struct mtx pcicfg_mtx; 204 static int mtx_initialized = 0; 205 206 /* 207 * Bus interface definitions. 208 */ 209 static device_method_t fsl_pcib_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, fsl_pcib_probe), 212 DEVMETHOD(device_attach, fsl_pcib_attach), 213 DEVMETHOD(device_detach, fsl_pcib_detach), 214 215 /* pcib interface */ 216 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 217 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 218 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 219 220 DEVMETHOD_END 221 }; 222 223 static devclass_t fsl_pcib_devclass; 224 225 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 226 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 227 DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0); 228 229 static int 230 fsl_pcib_err_intr(void *v) 231 { 232 struct fsl_pcib_softc *sc; 233 device_t dev; 234 uint32_t err_reg, clear_reg; 235 uint8_t i; 236 237 dev = (device_t)v; 238 sc = device_get_softc(dev); 239 240 clear_reg = 0; 241 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 242 243 /* Check which one error occurred */ 244 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 245 if (err_reg & pci_err[i].err_dr_mask) { 246 device_printf(dev, "PCI %d: report %s error\n", 247 device_get_unit(dev), pci_err[i].msg); 248 clear_reg |= pci_err[i].err_dr_mask; 249 } 250 } 251 252 /* Clear pending errors */ 253 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 254 255 return (0); 256 } 257 258 static int 259 fsl_pcib_probe(device_t dev) 260 { 261 262 if (ofw_bus_get_type(dev) == NULL || 263 strcmp(ofw_bus_get_type(dev), "pci") != 0) 264 return (ENXIO); 265 266 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 267 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 268 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 269 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 270 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 271 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 272 return (ENXIO); 273 274 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 275 return (BUS_PROBE_DEFAULT); 276 } 277 278 static int 279 fsl_pcib_attach(device_t dev) 280 { 281 struct fsl_pcib_softc *sc; 282 phandle_t node; 283 uint32_t cfgreg; 284 int error, maxslot, rid; 285 uint8_t ltssm, capptr; 286 287 sc = device_get_softc(dev); 288 sc->sc_dev = dev; 289 290 sc->sc_rid = 0; 291 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 292 RF_ACTIVE); 293 if (sc->sc_res == NULL) { 294 device_printf(dev, "could not map I/O memory\n"); 295 return (ENXIO); 296 } 297 sc->sc_bst = rman_get_bustag(sc->sc_res); 298 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 299 sc->sc_busnr = 0; 300 301 if (!mtx_initialized) { 302 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 303 mtx_initialized = 1; 304 } 305 306 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 307 if (cfgreg != 0x1057 && cfgreg != 0x1957) 308 goto err; 309 310 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 311 while (capptr != 0) { 312 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 313 switch (cfgreg & 0xff) { 314 case PCIY_PCIX: 315 break; 316 case PCIY_EXPRESS: 317 sc->sc_pcie = 1; 318 sc->sc_pcie_capreg = capptr; 319 break; 320 } 321 capptr = (cfgreg >> 8) & 0xff; 322 } 323 324 node = ofw_bus_get_node(dev); 325 326 /* 327 * Initialize generic OF PCI interface (ranges, etc.) 328 */ 329 330 error = ofw_pci_init(dev); 331 if (error) 332 return (error); 333 334 /* 335 * Configure decode windows for PCI(E) access. 336 */ 337 if (fsl_pcib_decode_win(node, sc) != 0) 338 goto err; 339 340 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 341 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 342 PCIM_CMD_PORTEN; 343 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 344 345 sc->sc_devfn_tundra = -1; 346 sc->sc_devfn_via_ide = -1; 347 348 349 /* 350 * Scan bus using firmware configured, 0 based bus numbering. 351 */ 352 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 353 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 354 355 if (sc->sc_pcie) { 356 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 357 if (ltssm < LTSSM_STAT_L0) { 358 if (bootverbose) 359 printf("PCI %d: no PCIE link, skipping\n", 360 device_get_unit(dev)); 361 return (0); 362 } 363 } 364 365 /* Allocate irq */ 366 rid = 0; 367 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 368 RF_ACTIVE | RF_SHAREABLE); 369 if (sc->sc_irq_res == NULL) { 370 error = fsl_pcib_detach(dev); 371 if (error != 0) { 372 device_printf(dev, 373 "Detach of the driver failed with error %d\n", 374 error); 375 } 376 return (ENXIO); 377 } 378 379 /* Setup interrupt handler */ 380 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 381 NULL, (driver_intr_t *)fsl_pcib_err_intr, dev, &sc->sc_ih); 382 if (error != 0) { 383 device_printf(dev, "Could not setup irq, %d\n", error); 384 sc->sc_ih = NULL; 385 error = fsl_pcib_detach(dev); 386 if (error != 0) { 387 device_printf(dev, 388 "Detach of the driver failed with error %d\n", 389 error); 390 } 391 return (ENXIO); 392 } 393 394 fsl_pcib_err_init(dev); 395 396 return (ofw_pci_attach(dev)); 397 398 err: 399 return (ENXIO); 400 } 401 402 static uint32_t 403 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 404 u_int reg, int bytes) 405 { 406 uint32_t addr, data; 407 408 addr = CONFIG_ACCESS_ENABLE; 409 addr |= (bus & 0xff) << 16; 410 addr |= (slot & 0x1f) << 11; 411 addr |= (func & 0x7) << 8; 412 addr |= reg & 0xfc; 413 if (sc->sc_pcie) 414 addr |= (reg & 0xf00) << 16; 415 416 mtx_lock_spin(&pcicfg_mtx); 417 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 418 419 switch (bytes) { 420 case 1: 421 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 422 REG_CFG_DATA + (reg & 3)); 423 break; 424 case 2: 425 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 426 REG_CFG_DATA + (reg & 2))); 427 break; 428 case 4: 429 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 430 REG_CFG_DATA)); 431 break; 432 default: 433 data = ~0; 434 break; 435 } 436 mtx_unlock_spin(&pcicfg_mtx); 437 return (data); 438 } 439 440 static void 441 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 442 u_int reg, uint32_t data, int bytes) 443 { 444 uint32_t addr; 445 446 addr = CONFIG_ACCESS_ENABLE; 447 addr |= (bus & 0xff) << 16; 448 addr |= (slot & 0x1f) << 11; 449 addr |= (func & 0x7) << 8; 450 addr |= reg & 0xfc; 451 if (sc->sc_pcie) 452 addr |= (reg & 0xf00) << 16; 453 454 mtx_lock_spin(&pcicfg_mtx); 455 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 456 457 switch (bytes) { 458 case 1: 459 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 460 REG_CFG_DATA + (reg & 3), data); 461 break; 462 case 2: 463 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 464 REG_CFG_DATA + (reg & 2), htole16(data)); 465 break; 466 case 4: 467 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 468 REG_CFG_DATA, htole32(data)); 469 break; 470 } 471 mtx_unlock_spin(&pcicfg_mtx); 472 } 473 474 #if 0 475 static void 476 dump(struct fsl_pcib_softc *sc) 477 { 478 unsigned int i; 479 480 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 481 for (i = 0; i < 5; i++) { 482 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 483 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 484 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 485 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 486 } 487 printf("\n"); 488 for (i = 1; i < 4; i++) { 489 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 490 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 491 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 492 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 493 } 494 printf("\n"); 495 #undef RD 496 497 for (i = 0; i < 0x48; i += 4) { 498 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 499 i, 4)); 500 } 501 } 502 #endif 503 504 static int 505 fsl_pcib_maxslots(device_t dev) 506 { 507 struct fsl_pcib_softc *sc = device_get_softc(dev); 508 509 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 510 } 511 512 static uint32_t 513 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 514 u_int reg, int bytes) 515 { 516 struct fsl_pcib_softc *sc = device_get_softc(dev); 517 u_int devfn; 518 519 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 520 return (~0); 521 devfn = DEVFN(bus, slot, func); 522 if (devfn == sc->sc_devfn_tundra) 523 return (~0); 524 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 525 return (1); 526 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 527 } 528 529 static void 530 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 531 u_int reg, uint32_t val, int bytes) 532 { 533 struct fsl_pcib_softc *sc = device_get_softc(dev); 534 535 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 536 return; 537 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 538 } 539 540 static void 541 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 542 int slot, int fn) 543 { 544 545 if (device == 0x0686) { 546 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 547 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 548 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 549 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 550 } else if (device == 0x0571) { 551 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 552 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 553 } 554 } 555 556 static int 557 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 558 { 559 int secbus; 560 int old_pribus, old_secbus, old_subbus; 561 int new_pribus, new_secbus, new_subbus; 562 int slot, func, maxfunc; 563 uint16_t vendor, device; 564 uint8_t command, hdrtype, subclass; 565 566 secbus = bus; 567 for (slot = 0; slot <= maxslot; slot++) { 568 maxfunc = 0; 569 for (func = 0; func <= maxfunc; func++) { 570 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 571 func, PCIR_HDRTYPE, 1); 572 573 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 574 continue; 575 576 if (func == 0 && (hdrtype & PCIM_MFDEV)) 577 maxfunc = PCI_FUNCMAX; 578 579 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 580 func, PCIR_VENDOR, 2); 581 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 582 func, PCIR_DEVICE, 2); 583 584 if (vendor == 0x1957 && device == 0x3fff) { 585 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 586 continue; 587 } 588 589 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 590 func, PCIR_COMMAND, 1); 591 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 592 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 593 PCIR_COMMAND, command, 1); 594 595 if (vendor == 0x1106) 596 fsl_pcib_init_via(sc, device, bus, slot, func); 597 598 /* 599 * Handle PCI-PCI bridges 600 */ 601 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 602 func, PCIR_SUBCLASS, 1); 603 604 /* Allow all DEVTYPE 1 devices */ 605 if (hdrtype != PCIM_HDRTYPE_BRIDGE) 606 continue; 607 608 secbus++; 609 610 /* Read currect bus register configuration */ 611 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 612 slot, func, PCIR_PRIBUS_1, 1); 613 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 614 slot, func, PCIR_SECBUS_1, 1); 615 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 616 slot, func, PCIR_SUBBUS_1, 1); 617 618 if (bootverbose) 619 printf("PCI: reading firmware bus numbers for " 620 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 621 secbus, old_pribus, old_secbus, old_subbus); 622 623 new_pribus = bus; 624 new_secbus = secbus; 625 626 secbus = fsl_pcib_init(sc, secbus, 627 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 628 629 new_subbus = secbus; 630 631 if (bootverbose) 632 printf("PCI: translate firmware bus numbers " 633 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 634 secbus, old_pribus, old_secbus, old_subbus, 635 new_pribus, new_secbus, new_subbus); 636 637 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 638 PCIR_PRIBUS_1, new_pribus, 1); 639 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 640 PCIR_SECBUS_1, new_secbus, 1); 641 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 642 PCIR_SUBBUS_1, new_subbus, 1); 643 } 644 } 645 646 return (secbus); 647 } 648 649 static void 650 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 651 uint64_t size, uint64_t pci_start) 652 { 653 uint32_t attr, bar, tar; 654 655 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 656 657 switch (tgt) { 658 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 659 case OCP85XX_TGTIF_RAM1: 660 attr = 0xa0f55000 | (ffsl(size) - 2); 661 break; 662 default: 663 attr = 0; 664 break; 665 } 666 tar = start >> 12; 667 bar = pci_start >> 12; 668 669 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 670 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 671 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 672 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 673 } 674 675 static void 676 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 677 uint64_t size, uint64_t pci_start) 678 { 679 uint32_t attr, bar, tar; 680 681 switch (res) { 682 case SYS_RES_MEMORY: 683 attr = 0x80044000 | (ffsll(size) - 2); 684 break; 685 case SYS_RES_IOPORT: 686 attr = 0x80088000 | (ffsll(size) - 2); 687 break; 688 default: 689 attr = 0x0004401f; 690 break; 691 } 692 bar = start >> 12; 693 tar = pci_start >> 12; 694 695 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 696 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 697 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 698 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 699 } 700 701 702 static void 703 fsl_pcib_err_init(device_t dev) 704 { 705 struct fsl_pcib_softc *sc; 706 uint16_t sec_stat, dsr; 707 uint32_t dcr, err_en; 708 709 sc = device_get_softc(dev); 710 711 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 712 if (sec_stat) 713 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 714 if (sc->sc_pcie) { 715 /* Clear error bits */ 716 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 717 0xffffffff); 718 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 719 0xffffffff); 720 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 721 0xffffffff); 722 723 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 724 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 725 if (dsr) 726 fsl_pcib_cfgwrite(sc, 0, 0, 0, 727 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 728 0xffff, 2); 729 730 /* Enable all errors reporting */ 731 err_en = 0x00bfff00; 732 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 733 err_en); 734 735 /* Enable error reporting: URR, FER, NFER */ 736 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 737 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 738 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 739 PCIEM_CTL_NFER_ENABLE; 740 fsl_pcib_cfgwrite(sc, 0, 0, 0, 741 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 742 } 743 } 744 745 static int 746 fsl_pcib_detach(device_t dev) 747 { 748 749 if (mtx_initialized) { 750 mtx_destroy(&pcicfg_mtx); 751 mtx_initialized = 0; 752 } 753 return (bus_generic_detach(dev)); 754 } 755 756 static int 757 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 758 { 759 device_t dev; 760 int error, i, trgt; 761 762 dev = sc->sc_dev; 763 764 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 765 766 /* 767 * Configure LAW decode windows. 768 */ 769 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 770 &sc->sc_ioport_target); 771 if (error != 0) { 772 device_printf(dev, "could not retrieve PCI LAW target info\n"); 773 return (error); 774 } 775 776 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 777 switch (sc->pci_sc.sc_range[i].pci_hi & 778 OFW_PCI_PHYS_HI_SPACEMASK) { 779 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 780 continue; 781 case OFW_PCI_PHYS_HI_SPACE_IO: 782 trgt = sc->sc_ioport_target; 783 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 784 sc->pci_sc.sc_range[i].host, 785 sc->pci_sc.sc_range[i].size, 786 sc->pci_sc.sc_range[i].pci); 787 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 788 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 789 sc->pci_sc.sc_range[i].size - 1; 790 break; 791 case OFW_PCI_PHYS_HI_SPACE_MEM32: 792 case OFW_PCI_PHYS_HI_SPACE_MEM64: 793 trgt = sc->sc_iomem_target; 794 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 795 sc->pci_sc.sc_range[i].host, 796 sc->pci_sc.sc_range[i].size, 797 sc->pci_sc.sc_range[i].pci); 798 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 799 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 800 sc->pci_sc.sc_range[i].size - 1; 801 break; 802 default: 803 panic("Unknown range type %#x\n", 804 sc->pci_sc.sc_range[i].pci_hi & 805 OFW_PCI_PHYS_HI_SPACEMASK); 806 } 807 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 808 sc->pci_sc.sc_range[i].size); 809 if (error != 0) { 810 device_printf(dev, "could not program LAW for range " 811 "%d\n", i); 812 return (error); 813 } 814 } 815 816 /* 817 * Set outbout and inbound windows. 818 */ 819 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 820 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 821 822 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 823 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 824 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 825 2U * 1024U * 1024U * 1024U, 0); 826 827 return (0); 828 } 829