1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/ktr.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/queue.h> 48 #include <sys/bus.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <sys/queue.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 #include <sys/vmem.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include <dev/ofw/ofw_pci.h> 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 #include <dev/ofw/ofwpci.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcib_private.h> 66 67 #include "ofw_bus_if.h" 68 #include "pcib_if.h" 69 #include "pic_if.h" 70 71 #include <machine/resource.h> 72 #include <machine/bus.h> 73 #include <machine/intr_machdep.h> 74 75 #include <powerpc/mpc85xx/mpc85xx.h> 76 77 #define REG_CFG_ADDR 0x0000 78 #define CONFIG_ACCESS_ENABLE 0x80000000 79 80 #define REG_CFG_DATA 0x0004 81 #define REG_INT_ACK 0x0008 82 83 #define REG_PEX_IP_BLK_REV1 0x0bf8 84 #define IP_MJ_M 0x0000ff00 85 #define IP_MJ_S 8 86 #define IP_MN_M 0x000000ff 87 #define IP_MN_S 0 88 89 #define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 90 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 91 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 92 #define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 93 94 #define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 95 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 96 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 97 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 98 #define PIWAR_EN 0x80000000 99 #define PIWAR_PF 0x40000000 100 #define PIWAR_TRGT_M 0x00f00000 101 #define PIWAR_TRGT_S 20 102 #define PIWAR_TRGT_CCSR 0xe 103 #define PIWAR_TRGT_LOCAL 0xf 104 105 #define REG_PEX_MES_DR 0x0020 106 #define REG_PEX_MES_IER 0x0028 107 #define REG_PEX_ERR_DR 0x0e00 108 #define REG_PEX_ERR_EN 0x0e08 109 110 #define REG_PEX_ERR_DR 0x0e00 111 #define REG_PEX_ERR_DR_ME 0x80000000 112 #define REG_PEX_ERR_DR_PCT 0x800000 113 #define REG_PEX_ERR_DR_PAT 0x400000 114 #define REG_PEX_ERR_DR_PCAC 0x200000 115 #define REG_PEX_ERR_DR_PNM 0x100000 116 #define REG_PEX_ERR_DR_CDNSC 0x80000 117 #define REG_PEX_ERR_DR_CRSNC 0x40000 118 #define REG_PEX_ERR_DR_ICCA 0x20000 119 #define REG_PEX_ERR_DR_IACA 0x10000 120 #define REG_PEX_ERR_DR_CRST 0x8000 121 #define REG_PEX_ERR_DR_MIS 0x4000 122 #define REG_PEX_ERR_DR_IOIS 0x2000 123 #define REG_PEX_ERR_DR_CIS 0x1000 124 #define REG_PEX_ERR_DR_CIEP 0x800 125 #define REG_PEX_ERR_DR_IOIEP 0x400 126 #define REG_PEX_ERR_DR_OAC 0x200 127 #define REG_PEX_ERR_DR_IOIA 0x100 128 #define REG_PEX_ERR_DR_IMBA 0x80 129 #define REG_PEX_ERR_DR_IIOBA 0x40 130 #define REG_PEX_ERR_DR_LDDE 0x20 131 #define REG_PEX_ERR_EN 0x0e08 132 133 #define PCIR_LTSSM 0x404 134 #define LTSSM_STAT_L0 0x16 135 136 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 137 138 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */ 139 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */ 140 141 struct fsl_pcib_softc { 142 struct ofw_pci_softc pci_sc; 143 device_t sc_dev; 144 struct mtx sc_cfg_mtx; 145 int sc_ip_maj; 146 int sc_ip_min; 147 148 int sc_iomem_target; 149 bus_addr_t sc_iomem_start, sc_iomem_end; 150 int sc_ioport_target; 151 bus_addr_t sc_ioport_start, sc_ioport_end; 152 153 struct resource *sc_res; 154 bus_space_handle_t sc_bsh; 155 bus_space_tag_t sc_bst; 156 int sc_rid; 157 158 struct resource *sc_irq_res; 159 void *sc_ih; 160 161 int sc_busnr; 162 int sc_pcie; 163 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 164 }; 165 166 struct fsl_pcib_err_dr { 167 const char *msg; 168 uint32_t err_dr_mask; 169 }; 170 171 struct fsl_msi_map { 172 SLIST_ENTRY(fsl_msi_map) slist; 173 uint32_t irq_base; 174 bus_addr_t target; 175 }; 176 177 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head); 178 179 static const struct fsl_pcib_err_dr pci_err[] = { 180 {"ME", REG_PEX_ERR_DR_ME}, 181 {"PCT", REG_PEX_ERR_DR_PCT}, 182 {"PAT", REG_PEX_ERR_DR_PAT}, 183 {"PCAC", REG_PEX_ERR_DR_PCAC}, 184 {"PNM", REG_PEX_ERR_DR_PNM}, 185 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 186 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 187 {"ICCA", REG_PEX_ERR_DR_ICCA}, 188 {"IACA", REG_PEX_ERR_DR_IACA}, 189 {"CRST", REG_PEX_ERR_DR_CRST}, 190 {"MIS", REG_PEX_ERR_DR_MIS}, 191 {"IOIS", REG_PEX_ERR_DR_IOIS}, 192 {"CIS", REG_PEX_ERR_DR_CIS}, 193 {"CIEP", REG_PEX_ERR_DR_CIEP}, 194 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 195 {"OAC", REG_PEX_ERR_DR_OAC}, 196 {"IOIA", REG_PEX_ERR_DR_IOIA}, 197 {"IMBA", REG_PEX_ERR_DR_IMBA}, 198 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 199 {"LDDE", REG_PEX_ERR_DR_LDDE} 200 }; 201 202 /* Local forward declerations. */ 203 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 204 u_int, int); 205 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 206 u_int, uint32_t, int); 207 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 208 static void fsl_pcib_err_init(device_t); 209 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 210 uint64_t, uint64_t); 211 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 212 uint64_t, uint64_t); 213 214 /* Forward declerations. */ 215 static int fsl_pcib_attach(device_t); 216 static int fsl_pcib_detach(device_t); 217 static int fsl_pcib_probe(device_t); 218 219 static int fsl_pcib_maxslots(device_t); 220 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 221 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 222 uint32_t, int); 223 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 224 int count, int maxcount, int *irqs); 225 static int fsl_pcib_release_msi(device_t dev, device_t child, 226 int count, int *irqs); 227 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq); 228 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq); 229 static int fsl_pcib_map_msi(device_t dev, device_t child, 230 int irq, uint64_t *addr, uint32_t *data); 231 232 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */ 233 234 /* 235 * Bus interface definitions. 236 */ 237 static device_method_t fsl_pcib_methods[] = { 238 /* Device interface */ 239 DEVMETHOD(device_probe, fsl_pcib_probe), 240 DEVMETHOD(device_attach, fsl_pcib_attach), 241 DEVMETHOD(device_detach, fsl_pcib_detach), 242 243 /* pcib interface */ 244 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 245 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 246 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 247 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi), 248 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi), 249 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix), 250 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix), 251 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi), 252 253 DEVMETHOD_END 254 }; 255 256 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 257 sizeof(struct fsl_pcib_softc), ofw_pcib_driver); 258 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS); 259 260 static void 261 fsl_pcib_err_intr(void *v) 262 { 263 struct fsl_pcib_softc *sc; 264 device_t dev; 265 uint32_t err_reg, clear_reg; 266 uint8_t i; 267 268 dev = (device_t)v; 269 sc = device_get_softc(dev); 270 271 clear_reg = 0; 272 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 273 274 /* Check which one error occurred */ 275 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 276 if (err_reg & pci_err[i].err_dr_mask) { 277 device_printf(dev, "PCI %d: report %s error\n", 278 device_get_unit(dev), pci_err[i].msg); 279 clear_reg |= pci_err[i].err_dr_mask; 280 } 281 } 282 283 /* Clear pending errors */ 284 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 285 } 286 287 static int 288 fsl_pcib_probe(device_t dev) 289 { 290 291 if (ofw_bus_get_type(dev) == NULL || 292 strcmp(ofw_bus_get_type(dev), "pci") != 0) 293 return (ENXIO); 294 295 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 296 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 297 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 298 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 299 ofw_bus_is_compatible(dev, "fsl,p5040-pcie") || 300 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 301 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.4") || 302 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 303 return (ENXIO); 304 305 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 306 return (BUS_PROBE_DEFAULT); 307 } 308 309 static int 310 fsl_pcib_attach(device_t dev) 311 { 312 struct fsl_pcib_softc *sc; 313 phandle_t node; 314 uint32_t cfgreg, brctl, ipreg; 315 int do_reset, error, rid; 316 uint8_t ltssm, capptr; 317 318 sc = device_get_softc(dev); 319 sc->sc_dev = dev; 320 321 sc->sc_rid = 0; 322 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 323 RF_ACTIVE); 324 if (sc->sc_res == NULL) { 325 device_printf(dev, "could not map I/O memory\n"); 326 return (ENXIO); 327 } 328 sc->sc_bst = rman_get_bustag(sc->sc_res); 329 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 330 sc->sc_busnr = 0; 331 332 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1); 333 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S; 334 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S; 335 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN); 336 337 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 338 if (cfgreg != 0x1057 && cfgreg != 0x1957) 339 goto err; 340 341 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 342 while (capptr != 0) { 343 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 344 switch (cfgreg & 0xff) { 345 case PCIY_PCIX: 346 break; 347 case PCIY_EXPRESS: 348 sc->sc_pcie = 1; 349 sc->sc_pcie_capreg = capptr; 350 break; 351 } 352 capptr = (cfgreg >> 8) & 0xff; 353 } 354 355 node = ofw_bus_get_node(dev); 356 357 /* 358 * Initialize generic OF PCI interface (ranges, etc.) 359 */ 360 361 error = ofw_pcib_init(dev); 362 if (error) 363 return (error); 364 365 /* 366 * Configure decode windows for PCI(E) access. 367 */ 368 if (fsl_pcib_decode_win(node, sc) != 0) 369 goto err; 370 371 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 372 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 373 PCIM_CMD_PORTEN; 374 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 375 376 do_reset = 0; 377 resource_int_value("pcib", device_get_unit(dev), "reset", &do_reset); 378 if (do_reset) { 379 /* Reset the bus. Needed for Radeon video cards. */ 380 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0, 381 PCIR_BRIDGECTL_1, 1); 382 brctl |= PCIB_BCR_SECBUS_RESET; 383 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 384 PCIR_BRIDGECTL_1, brctl, 1); 385 DELAY(100000); 386 brctl &= ~PCIB_BCR_SECBUS_RESET; 387 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 388 PCIR_BRIDGECTL_1, brctl, 1); 389 DELAY(100000); 390 } 391 392 if (sc->sc_pcie) { 393 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 394 if (ltssm < LTSSM_STAT_L0) { 395 if (bootverbose) 396 printf("PCI %d: no PCIE link, skipping\n", 397 device_get_unit(dev)); 398 return (0); 399 } 400 } 401 402 /* Allocate irq */ 403 rid = 0; 404 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 405 RF_ACTIVE | RF_SHAREABLE); 406 if (sc->sc_irq_res == NULL) { 407 error = fsl_pcib_detach(dev); 408 if (error != 0) { 409 device_printf(dev, 410 "Detach of the driver failed with error %d\n", 411 error); 412 } 413 return (ENXIO); 414 } 415 416 /* Setup interrupt handler */ 417 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 418 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih); 419 if (error != 0) { 420 device_printf(dev, "Could not setup irq, %d\n", error); 421 sc->sc_ih = NULL; 422 error = fsl_pcib_detach(dev); 423 if (error != 0) { 424 device_printf(dev, 425 "Detach of the driver failed with error %d\n", 426 error); 427 } 428 return (ENXIO); 429 } 430 431 fsl_pcib_err_init(dev); 432 433 return (ofw_pcib_attach(dev)); 434 435 err: 436 return (ENXIO); 437 } 438 439 static uint32_t 440 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 441 u_int reg, int bytes) 442 { 443 uint32_t addr, data; 444 445 addr = CONFIG_ACCESS_ENABLE; 446 addr |= (bus & 0xff) << 16; 447 addr |= (slot & 0x1f) << 11; 448 addr |= (func & 0x7) << 8; 449 addr |= reg & 0xfc; 450 if (sc->sc_pcie) 451 addr |= (reg & 0xf00) << 16; 452 453 mtx_lock_spin(&sc->sc_cfg_mtx); 454 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 455 456 switch (bytes) { 457 case 1: 458 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 459 REG_CFG_DATA + (reg & 3)); 460 break; 461 case 2: 462 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 463 REG_CFG_DATA + (reg & 2))); 464 break; 465 case 4: 466 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 467 REG_CFG_DATA)); 468 break; 469 default: 470 data = ~0; 471 break; 472 } 473 mtx_unlock_spin(&sc->sc_cfg_mtx); 474 return (data); 475 } 476 477 static void 478 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 479 u_int reg, uint32_t data, int bytes) 480 { 481 uint32_t addr; 482 483 addr = CONFIG_ACCESS_ENABLE; 484 addr |= (bus & 0xff) << 16; 485 addr |= (slot & 0x1f) << 11; 486 addr |= (func & 0x7) << 8; 487 addr |= reg & 0xfc; 488 if (sc->sc_pcie) 489 addr |= (reg & 0xf00) << 16; 490 491 mtx_lock_spin(&sc->sc_cfg_mtx); 492 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 493 494 switch (bytes) { 495 case 1: 496 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 497 REG_CFG_DATA + (reg & 3), data); 498 break; 499 case 2: 500 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 501 REG_CFG_DATA + (reg & 2), htole16(data)); 502 break; 503 case 4: 504 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 505 REG_CFG_DATA, htole32(data)); 506 break; 507 } 508 mtx_unlock_spin(&sc->sc_cfg_mtx); 509 } 510 511 #if 0 512 static void 513 dump(struct fsl_pcib_softc *sc) 514 { 515 unsigned int i; 516 517 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 518 for (i = 0; i < 5; i++) { 519 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 520 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 521 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 522 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 523 } 524 printf("\n"); 525 for (i = 1; i < 4; i++) { 526 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 527 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 528 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 529 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 530 } 531 printf("\n"); 532 #undef RD 533 534 for (i = 0; i < 0x48; i += 4) { 535 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 536 i, 4)); 537 } 538 } 539 #endif 540 541 static int 542 fsl_pcib_maxslots(device_t dev) 543 { 544 struct fsl_pcib_softc *sc = device_get_softc(dev); 545 546 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 547 } 548 549 static uint32_t 550 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 551 u_int reg, int bytes) 552 { 553 struct fsl_pcib_softc *sc = device_get_softc(dev); 554 555 if (bus == sc->sc_busnr && !sc->sc_pcie && 556 slot < PCI_SLOT_FIRST) 557 return (~0); 558 559 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 560 } 561 562 static void 563 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 564 u_int reg, uint32_t val, int bytes) 565 { 566 struct fsl_pcib_softc *sc = device_get_softc(dev); 567 568 if (bus == sc->sc_busnr && !sc->sc_pcie && 569 slot < PCI_SLOT_FIRST) 570 return; 571 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 572 } 573 574 static void 575 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 576 uint64_t size, uint64_t pci_start) 577 { 578 uint32_t attr, bar, tar; 579 580 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 581 582 attr = PIWAR_EN; 583 584 switch (tgt) { 585 case -1: 586 attr &= ~PIWAR_EN; 587 break; 588 case PIWAR_TRGT_LOCAL: 589 attr |= (ffsl(size) - 2); 590 default: 591 attr |= (tgt << PIWAR_TRGT_S); 592 break; 593 } 594 tar = start >> 12; 595 bar = pci_start >> 12; 596 597 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 598 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 599 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 601 } 602 603 static void 604 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 605 uint64_t size, uint64_t pci_start) 606 { 607 uint32_t attr, bar, tar; 608 609 switch (res) { 610 case SYS_RES_MEMORY: 611 attr = 0x80044000 | (ffsll(size) - 2); 612 break; 613 case SYS_RES_IOPORT: 614 attr = 0x80088000 | (ffsll(size) - 2); 615 break; 616 default: 617 attr = 0x0004401f; 618 break; 619 } 620 bar = start >> 12; 621 tar = pci_start >> 12; 622 623 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 624 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 625 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 626 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 627 } 628 629 static void 630 fsl_pcib_err_init(device_t dev) 631 { 632 struct fsl_pcib_softc *sc; 633 uint16_t sec_stat, dsr; 634 uint32_t dcr, err_en; 635 636 sc = device_get_softc(dev); 637 638 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 639 if (sec_stat) 640 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 641 if (sc->sc_pcie) { 642 /* Clear error bits */ 643 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 644 0xffffffff); 645 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 646 0xffffffff); 647 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 648 0xffffffff); 649 650 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 651 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 652 if (dsr) 653 fsl_pcib_cfgwrite(sc, 0, 0, 0, 654 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 655 0xffff, 2); 656 657 /* Enable all errors reporting */ 658 err_en = 0x00bfff00; 659 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 660 err_en); 661 662 /* Enable error reporting: URR, FER, NFER */ 663 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 664 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 665 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 666 PCIEM_CTL_NFER_ENABLE; 667 fsl_pcib_cfgwrite(sc, 0, 0, 0, 668 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 669 } 670 } 671 672 static int 673 fsl_pcib_detach(device_t dev) 674 { 675 struct fsl_pcib_softc *sc; 676 677 sc = device_get_softc(dev); 678 679 mtx_destroy(&sc->sc_cfg_mtx); 680 681 return (bus_generic_detach(dev)); 682 } 683 684 static int 685 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 686 { 687 device_t dev; 688 int error, i, trgt; 689 690 dev = sc->sc_dev; 691 692 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 693 694 /* 695 * Configure LAW decode windows. 696 */ 697 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 698 &sc->sc_ioport_target); 699 if (error != 0) { 700 device_printf(dev, "could not retrieve PCI LAW target info\n"); 701 return (error); 702 } 703 704 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 705 switch (sc->pci_sc.sc_range[i].pci_hi & 706 OFW_PCI_PHYS_HI_SPACEMASK) { 707 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 708 continue; 709 case OFW_PCI_PHYS_HI_SPACE_IO: 710 trgt = sc->sc_ioport_target; 711 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 712 sc->pci_sc.sc_range[i].host, 713 sc->pci_sc.sc_range[i].size, 714 sc->pci_sc.sc_range[i].pci); 715 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 716 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 717 sc->pci_sc.sc_range[i].size - 1; 718 break; 719 case OFW_PCI_PHYS_HI_SPACE_MEM32: 720 case OFW_PCI_PHYS_HI_SPACE_MEM64: 721 trgt = sc->sc_iomem_target; 722 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 723 sc->pci_sc.sc_range[i].host, 724 sc->pci_sc.sc_range[i].size, 725 sc->pci_sc.sc_range[i].pci); 726 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 727 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 728 sc->pci_sc.sc_range[i].size - 1; 729 break; 730 default: 731 panic("Unknown range type %#x\n", 732 sc->pci_sc.sc_range[i].pci_hi & 733 OFW_PCI_PHYS_HI_SPACEMASK); 734 } 735 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 736 sc->pci_sc.sc_range[i].size); 737 if (error != 0) { 738 device_printf(dev, "could not program LAW for range " 739 "%d\n", i); 740 return (error); 741 } 742 } 743 744 /* 745 * Set outbout and inbound windows. 746 */ 747 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 748 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 749 750 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 751 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 752 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0, 753 ptoa(Maxmem), 0); 754 755 /* Direct-map the CCSR for MSIs. */ 756 /* Freescale PCIe 2.x has a dedicated MSI window. */ 757 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */ 758 if (sc->sc_ip_maj >= 2) 759 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa, 760 ccsrbar_size, ccsrbar_pa); 761 else 762 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa, 763 ccsrbar_size, ccsrbar_pa); 764 765 return (0); 766 } 767 768 static int fsl_pcib_alloc_msi(device_t dev, device_t child, 769 int count, int maxcount, int *irqs) 770 { 771 vmem_addr_t start; 772 int err, i; 773 774 if (msi_vmem == NULL) 775 return (ENODEV); 776 777 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0, 778 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 779 780 if (err) 781 return (err); 782 783 for (i = 0; i < count; i++) 784 irqs[i] = start + i; 785 786 return (0); 787 } 788 789 static int fsl_pcib_release_msi(device_t dev, device_t child, 790 int count, int *irqs) 791 { 792 if (msi_vmem == NULL) 793 return (ENODEV); 794 795 vmem_xfree(msi_vmem, irqs[0], count); 796 return (0); 797 } 798 799 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq) 800 { 801 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq)); 802 } 803 804 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq) 805 { 806 return (fsl_pcib_release_msi(dev, child, 1, &irq)); 807 } 808 809 static int fsl_pcib_map_msi(device_t dev, device_t child, 810 int irq, uint64_t *addr, uint32_t *data) 811 { 812 struct fsl_msi_map *mp; 813 814 SLIST_FOREACH(mp, &fsl_msis, slist) { 815 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS) 816 break; 817 } 818 819 if (mp == NULL) 820 return (ENODEV); 821 822 *data = (irq & 255); 823 *addr = ccsrbar_pa + mp->target; 824 825 return (0); 826 } 827 828 /* 829 * Linux device trees put the msi@<x> as children of the SoC, with ranges based 830 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between 831 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC 832 * driver just to allocate a subregion for a sibling driver). This driver will 833 * use ccsr_write() and ccsr_read() instead. 834 */ 835 836 #define FSL_NUM_IRQS 8 837 #define FSL_NUM_MSI_PER_IRQ 32 838 #define FSL_MSI_TARGET 0x140 839 840 struct fsl_msi_softc { 841 vm_offset_t sc_base; 842 vm_offset_t sc_target; 843 int sc_msi_base_irq; 844 struct fsl_msi_map sc_map; 845 struct fsl_msi_irq { 846 /* This struct gets passed as the filter private data. */ 847 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */ 848 struct resource *res; 849 int irq; 850 void *cookie; 851 int vectors[FSL_NUM_MSI_PER_IRQ]; 852 vm_offset_t reg; 853 } sc_msi_irq[FSL_NUM_IRQS]; 854 }; 855 856 static int 857 fsl_msi_intr_filter(void *priv) 858 { 859 struct fsl_msi_irq *data = priv; 860 uint32_t reg; 861 int i; 862 863 reg = ccsr_read4(ccsrbar_va + data->reg); 864 i = 0; 865 while (reg != 0) { 866 if (reg & 1) 867 powerpc_dispatch_intr(data->vectors[i], NULL); 868 reg >>= 1; 869 i++; 870 } 871 872 return (FILTER_HANDLED); 873 } 874 875 static int 876 fsl_msi_probe(device_t dev) 877 { 878 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi")) 879 return (ENXIO); 880 881 device_set_desc(dev, "Freescale MSI"); 882 883 return (BUS_PROBE_DEFAULT); 884 } 885 886 static int 887 fsl_msi_attach(device_t dev) 888 { 889 struct fsl_msi_softc *sc; 890 struct fsl_msi_irq *irq; 891 int i; 892 893 sc = device_get_softc(dev); 894 895 if (msi_vmem == NULL) 896 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK); 897 898 /* Manually play with resource entries. */ 899 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); 900 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1); 901 902 if (sc->sc_map.target == 0) 903 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET; 904 905 for (i = 0; i < FSL_NUM_IRQS; i++) { 906 irq = &sc->sc_msi_irq[i]; 907 irq->irq = i; 908 irq->reg = sc->sc_base + 16 * i; 909 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 910 &irq->irq, RF_ACTIVE); 911 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE, 912 fsl_msi_intr_filter, NULL, irq, &irq->cookie); 913 } 914 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev), 915 FSL_NUM_MSIS, 0, 0); 916 917 /* Let vmem and the IRQ subsystem work their magic for allocations. */ 918 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK); 919 920 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist); 921 922 return (0); 923 } 924 925 static void 926 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv) 927 { 928 struct fsl_msi_softc *sc; 929 struct fsl_msi_irq *irqd; 930 931 sc = device_get_softc(dev); 932 933 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ]; 934 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector; 935 } 936 937 static device_method_t fsl_msi_methods[] = { 938 DEVMETHOD(device_probe, fsl_msi_probe), 939 DEVMETHOD(device_attach, fsl_msi_attach), 940 941 DEVMETHOD(pic_enable, fsl_msi_enable), 942 DEVMETHOD_END 943 }; 944 945 static driver_t fsl_msi_driver = { 946 "fsl_msi", 947 fsl_msi_methods, 948 sizeof(struct fsl_msi_softc) 949 }; 950 951 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0, 952 BUS_PASS_INTERRUPT + 1); 953