1 /*- 2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 3 * Copyright 2006 by Juniper Networks. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _MPC85XX_H_ 31 #define _MPC85XX_H_ 32 33 #include <machine/platformvar.h> 34 35 /* 36 * Configuration control and status registers 37 */ 38 extern vm_offset_t ccsrbar_va; 39 #define CCSRBAR_VA ccsrbar_va 40 #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0) 41 #define OCP85XX_BPTR (CCSRBAR_VA + 0x20) 42 43 #define OCP85XX_BSTRH (CCSRBAR_VA + 0x20) 44 #define OCP85XX_BSTRL (CCSRBAR_VA + 0x24) 45 #define OCP85XX_BSTAR (CCSRBAR_VA + 0x28) 46 47 #define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094) 48 #define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4) 49 50 /* 51 * Run Control and Power Management registers 52 */ 53 #define CCSR_CTBENR (CCSRBAR_VA + 0xE2084) 54 #define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C) 55 #define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094) 56 57 /* 58 * DDR Memory controller. 59 */ 60 #define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080) 61 62 /* 63 * E500 Coherency Module registers 64 */ 65 #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) 66 67 /* 68 * Local access registers 69 */ 70 /* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */ 71 #define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n)) 72 #define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n)) 73 #define OCP85XX_LAWSR_QORIQ(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) 74 #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) 75 #define OCP85XX_LAWSR_85XX(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n)) 76 #define OCP85XX_LAWSR(n) (mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \ 77 OCP85XX_LAWSR_85XX(n)) 78 79 /* Attribute register */ 80 #define OCP85XX_ENA_MASK 0x80000000 81 #define OCP85XX_DIS_MASK 0x7fffffff 82 83 #define OCP85XX_TGTIF_LBC_QORIQ 0x1f 84 #define OCP85XX_TGTIF_RAM_INTL_QORIQ 0x14 85 #define OCP85XX_TGTIF_RAM1_QORIQ 0x10 86 #define OCP85XX_TGTIF_RAM2_QORIQ 0x11 87 #define OCP85XX_TGTIF_BMAN 0x18 88 #define OCP85XX_TGTIF_DCSR 0x1D 89 #define OCP85XX_TGTIF_QMAN 0x3C 90 #define OCP85XX_TRGT_SHIFT_QORIQ 20 91 92 #define OCP85XX_TGTIF_LBC_85XX 0x04 93 #define OCP85XX_TGTIF_RAM_INTL_85XX 0x0b 94 #define OCP85XX_TGTIF_RIO_85XX 0x0c 95 #define OCP85XX_TGTIF_RAM1_85XX 0x0f 96 #define OCP85XX_TGTIF_RAM2_85XX 0x16 97 98 #define OCP85XX_TGTIF_LBC \ 99 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX) 100 #define OCP85XX_TGTIF_RAM_INTL \ 101 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX) 102 #define OCP85XX_TGTIF_RIO \ 103 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX) 104 #define OCP85XX_TGTIF_RAM1 \ 105 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX) 106 #define OCP85XX_TGTIF_RAM2 \ 107 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX) 108 109 /* 110 * L2 cache registers 111 */ 112 #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) 113 114 /* 115 * L3 CoreNet platform cache (CPC) registers 116 */ 117 #define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000) 118 #define OCP85XX_CPC_CSR0_CE 0x80000000 119 #define OCP85XX_CPC_CSR0_PE 0x40000000 120 #define OCP85XX_CPC_CSR0_FI 0x00200000 121 #define OCP85XX_CPC_CSR0_WT 0x00080000 122 #define OCP85XX_CPC_CSR0_FL 0x00000800 123 #define OCP85XX_CPC_CSR0_LFC 0x00000400 124 #define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008) 125 #define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff 126 #define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6) 127 128 /* 129 * Power-On Reset configuration 130 */ 131 #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c) 132 #define OCP85XX_PORDEVSR_IO_SEL 0x00780000 133 #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19 134 135 #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) 136 137 /* 138 * Status Registers. 139 */ 140 #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) 141 142 /* 143 * Run Control/Power Management Registers. 144 */ 145 #define OCP85XX_RCPM_CDOZSR (CCSRBAR_VA + 0xe2004) 146 #define OCP85XX_RCPM_CDOZCR (CCSRBAR_VA + 0xe200c) 147 148 /* 149 * Prototypes. 150 */ 151 uint32_t ccsr_read4(uintptr_t addr); 152 void ccsr_write4(uintptr_t addr, uint32_t val); 153 int law_enable(int trgt, uint64_t bar, uint32_t size); 154 int law_disable(int trgt, uint64_t bar, uint32_t size); 155 int law_getmax(void); 156 int law_pci_target(struct resource *, int *, int *); 157 158 DECLARE_CLASS(mpc85xx_platform); 159 int mpc85xx_attach(platform_t); 160 161 void mpc85xx_enable_l3_cache(void); 162 void mpc85xx_fix_errata(vm_offset_t); 163 void dataloss_erratum_access(vm_offset_t, uint32_t); 164 int mpc85xx_is_qoriq(void); 165 166 #endif /* _MPC85XX_H_ */ 167