1 /*- 2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 3 * Copyright 2006 by Juniper Networks. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _MPC85XX_H_ 31 #define _MPC85XX_H_ 32 33 /* 34 * Configuration control and status registers 35 */ 36 #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0) 37 #define OCP85XX_BPTR (CCSRBAR_VA + 0x20) 38 39 /* 40 * E500 Coherency Module registers 41 */ 42 #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) 43 44 /* 45 * Local access registers 46 */ 47 #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n)) 48 #define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n)) 49 50 #define OCP85XX_TGTIF_LBC 4 51 #define OCP85XX_TGTIF_RAM_INTL 11 52 #define OCP85XX_TGTIF_RIO 12 53 #define OCP85XX_TGTIF_RAM1 15 54 #define OCP85XX_TGTIF_RAM2 22 55 56 /* 57 * L2 cache registers 58 */ 59 #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) 60 61 /* 62 * Power-On Reset configuration 63 */ 64 #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c) 65 #define OCP85XX_PORDEVSR_IO_SEL 0x00780000 66 #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19 67 68 #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) 69 70 #define OCP85XX_DEVDISR (CCSRBAR_VA + 0xe0070) 71 #define OCP85XX_DEVDISR_PCIE0 0x20000000 72 #define OCP85XX_DEVDISR_PCIE1 0x04000000 73 #define OCP85XX_DEVDISR_PCIE2 0x02000000 74 75 /* 76 * Status Registers. 77 */ 78 #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) 79 80 /* 81 * Prototypes. 82 */ 83 uint32_t ccsr_read4(uintptr_t addr); 84 void ccsr_write4(uintptr_t addr, uint32_t val); 85 int law_enable(int trgt, u_long addr, u_long size); 86 int law_disable(int trgt, u_long addr, u_long size); 87 int law_getmax(void); 88 int law_pci_target(struct resource *, int *, int *); 89 90 #endif /* _MPC85XX_H_ */ 91