xref: /freebsd/sys/powerpc/mpc85xx/mpc85xx.h (revision 39ee7a7a6bdd1557b1c3532abf60d139798ac88b)
1 /*-
2  * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3  * Copyright 2006 by Juniper Networks.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  */
29 
30 #ifndef _MPC85XX_H_
31 #define _MPC85XX_H_
32 
33 #include <machine/platformvar.h>
34 
35 /*
36  * Configuration control and status registers
37  */
38 extern vm_offset_t		ccsrbar_va;
39 #define CCSRBAR_VA		ccsrbar_va
40 #define	OCP85XX_CCSRBAR		(CCSRBAR_VA + 0x0)
41 #define	OCP85XX_BPTR		(CCSRBAR_VA + 0x20)
42 
43 /*
44  * E500 Coherency Module registers
45  */
46 #define	OCP85XX_EEBPCR		(CCSRBAR_VA + 0x1010)
47 
48 /*
49  * Local access registers
50  */
51 #define	OCP85XX_LAWBAR(n)	(CCSRBAR_VA + 0xc08 + 0x20 * (n))
52 #define	OCP85XX_LAWSR(n)	(CCSRBAR_VA + 0xc10 + 0x20 * (n))
53 
54 #define	OCP85XX_TGTIF_LBC	4
55 #define	OCP85XX_TGTIF_RAM_INTL	11
56 #define	OCP85XX_TGTIF_RIO	12
57 #define	OCP85XX_TGTIF_RAM1	15
58 #define	OCP85XX_TGTIF_RAM2	22
59 
60 /*
61  * L2 cache registers
62  */
63 #define OCP85XX_L2CTL		(CCSRBAR_VA + 0x20000)
64 
65 /*
66  * Power-On Reset configuration
67  */
68 #define	OCP85XX_PORDEVSR	(CCSRBAR_VA + 0xe000c)
69 #define OCP85XX_PORDEVSR_IO_SEL	0x00780000
70 #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
71 
72 #define	OCP85XX_PORDEVSR2	(CCSRBAR_VA + 0xe0014)
73 
74 /*
75  * Status Registers.
76  */
77 #define	OCP85XX_RSTCR		(CCSRBAR_VA + 0xe00b0)
78 
79 /*
80  * Prototypes.
81  */
82 uint32_t ccsr_read4(uintptr_t addr);
83 void ccsr_write4(uintptr_t addr, uint32_t val);
84 int law_enable(int trgt, u_long addr, u_long size);
85 int law_disable(int trgt, u_long addr, u_long size);
86 int law_getmax(void);
87 int law_pci_target(struct resource *, int *, int *);
88 
89 DECLARE_CLASS(mpc85xx_platform);
90 int mpc85xx_attach(platform_t);
91 
92 #endif /* _MPC85XX_H_ */
93