1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_platform.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/reboot.h> 36 #include <sys/rman.h> 37 38 #include <vm/vm.h> 39 #include <vm/vm_param.h> 40 #include <vm/pmap.h> 41 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/machdep.h> 45 #include <machine/pio.h> 46 #include <machine/spr.h> 47 48 #include <dev/fdt/fdt_common.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 #include <dev/ofw/openfirm.h> 54 55 #include <powerpc/mpc85xx/mpc85xx.h> 56 57 /* 58 * MPC85xx system specific routines 59 */ 60 61 uint32_t 62 ccsr_read4(uintptr_t addr) 63 { 64 volatile uint32_t *ptr = (void *)addr; 65 66 return (*ptr); 67 } 68 69 void 70 ccsr_write4(uintptr_t addr, uint32_t val) 71 { 72 volatile uint32_t *ptr = (void *)addr; 73 74 *ptr = val; 75 powerpc_iomb(); 76 } 77 78 int 79 law_getmax(void) 80 { 81 uint32_t ver; 82 int law_max; 83 84 ver = SVR_VER(mfspr(SPR_SVR)); 85 switch (ver) { 86 case SVR_MPC8555: 87 case SVR_MPC8555E: 88 law_max = 8; 89 break; 90 case SVR_MPC8533: 91 case SVR_MPC8533E: 92 case SVR_MPC8548: 93 case SVR_MPC8548E: 94 law_max = 10; 95 break; 96 case SVR_P5020: 97 case SVR_P5020E: 98 case SVR_P5021: 99 case SVR_P5021E: 100 case SVR_P5040: 101 case SVR_P5040E: 102 law_max = 32; 103 break; 104 default: 105 law_max = 8; 106 } 107 108 return (law_max); 109 } 110 111 static inline void 112 law_write(uint32_t n, uint64_t bar, uint32_t sr) 113 { 114 115 if (mpc85xx_is_qoriq()) { 116 ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32); 117 ccsr_write4(OCP85XX_LAWBARL(n), bar); 118 ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr); 119 ccsr_read4(OCP85XX_LAWSR_QORIQ(n)); 120 } else { 121 ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12); 122 ccsr_write4(OCP85XX_LAWSR_85XX(n), sr); 123 ccsr_read4(OCP85XX_LAWSR_85XX(n)); 124 } 125 126 /* 127 * The last write to LAWAR should be followed by a read 128 * of LAWAR before any device try to use any of windows. 129 * What more the read of LAWAR should be followed by isync 130 * instruction. 131 */ 132 133 isync(); 134 } 135 136 static inline void 137 law_read(uint32_t n, uint64_t *bar, uint32_t *sr) 138 { 139 140 if (mpc85xx_is_qoriq()) { 141 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 | 142 ccsr_read4(OCP85XX_LAWBARL(n)); 143 *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n)); 144 } else { 145 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12; 146 *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n)); 147 } 148 } 149 150 static int 151 law_find_free(void) 152 { 153 uint32_t i,sr; 154 uint64_t bar; 155 int law_max; 156 157 law_max = law_getmax(); 158 /* Find free LAW */ 159 for (i = 0; i < law_max; i++) { 160 law_read(i, &bar, &sr); 161 if ((sr & 0x80000000) == 0) 162 break; 163 } 164 165 return (i); 166 } 167 168 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | \ 169 (flsl(size + (size - 1)) - 2)) 170 171 int 172 law_enable(int trgt, uint64_t bar, uint32_t size) 173 { 174 uint64_t bar_tmp; 175 uint32_t sr, sr_tmp; 176 int i, law_max; 177 178 if (size == 0) 179 return (0); 180 181 law_max = law_getmax(); 182 sr = _LAW_SR(trgt, size); 183 184 /* Bail if already programmed. */ 185 for (i = 0; i < law_max; i++) { 186 law_read(i, &bar_tmp, &sr_tmp); 187 if (sr == sr_tmp && bar == bar_tmp) 188 return (0); 189 } 190 191 /* Find an unused access window. */ 192 i = law_find_free(); 193 194 if (i == law_max) 195 return (ENOSPC); 196 197 law_write(i, bar, sr); 198 return (0); 199 } 200 201 int 202 law_disable(int trgt, uint64_t bar, uint32_t size) 203 { 204 uint64_t bar_tmp; 205 uint32_t sr, sr_tmp; 206 int i, law_max; 207 208 law_max = law_getmax(); 209 sr = _LAW_SR(trgt, size); 210 211 /* Find and disable requested LAW. */ 212 for (i = 0; i < law_max; i++) { 213 law_read(i, &bar_tmp, &sr_tmp); 214 if (sr == sr_tmp && bar == bar_tmp) { 215 law_write(i, 0, 0); 216 return (0); 217 } 218 } 219 220 return (ENOENT); 221 } 222 223 int 224 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io) 225 { 226 u_long start; 227 uint32_t ver; 228 int trgt, rv; 229 230 ver = SVR_VER(mfspr(SPR_SVR)); 231 232 start = rman_get_start(res) & 0xf000; 233 234 rv = 0; 235 trgt = -1; 236 switch (start) { 237 case 0x0000: 238 case 0x8000: 239 trgt = 0; 240 break; 241 case 0x1000: 242 case 0x9000: 243 trgt = 1; 244 break; 245 case 0x2000: 246 case 0xa000: 247 if (ver == SVR_MPC8548E || ver == SVR_MPC8548) 248 trgt = 3; 249 else 250 trgt = 2; 251 break; 252 case 0x3000: 253 case 0xb000: 254 if (ver == SVR_MPC8548E || ver == SVR_MPC8548) 255 rv = EINVAL; 256 else 257 trgt = 3; 258 break; 259 default: 260 rv = ENXIO; 261 } 262 if (rv == 0) { 263 *trgt_mem = trgt; 264 *trgt_io = trgt; 265 } 266 return (rv); 267 } 268 269 static void 270 l3cache_inval(void) 271 { 272 273 /* Flash invalidate the CPC and clear all the locks */ 274 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI | 275 OCP85XX_CPC_CSR0_LFC); 276 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI | 277 OCP85XX_CPC_CSR0_LFC)) 278 ; 279 } 280 281 static void 282 l3cache_enable(void) 283 { 284 285 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE | 286 OCP85XX_CPC_CSR0_PE); 287 /* Read back to sync write */ 288 ccsr_read4(OCP85XX_CPC_CSR0); 289 } 290 291 void 292 mpc85xx_enable_l3_cache(void) 293 { 294 uint32_t csr, size, ver; 295 296 /* Enable L3 CoreNet Platform Cache (CPC) */ 297 ver = SVR_VER(mfspr(SPR_SVR)); 298 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 || 299 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) { 300 csr = ccsr_read4(OCP85XX_CPC_CSR0); 301 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { 302 l3cache_inval(); 303 l3cache_enable(); 304 } 305 306 csr = ccsr_read4(OCP85XX_CPC_CSR0); 307 if ((boothowto & RB_VERBOSE) != 0 || 308 (csr & OCP85XX_CPC_CSR0_CE) == 0) { 309 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0)); 310 printf("L3 Corenet Platform Cache: %d KB %sabled\n", 311 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? 312 "dis" : "en"); 313 } 314 } 315 } 316 317 int 318 mpc85xx_is_qoriq(void) 319 { 320 uint16_t pvr = mfpvr() >> 16; 321 322 /* QorIQ register set is only in e500mc and derivative core based SoCs. */ 323 if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500) 324 return (1); 325 326 return (0); 327 } 328 329 uint32_t 330 mpc85xx_get_platform_clock(void) 331 { 332 phandle_t soc; 333 static uint32_t freq; 334 335 if (freq != 0) 336 return (freq); 337 338 soc = OF_finddevice("/soc"); 339 340 /* freq isn't modified on error. */ 341 OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq)); 342 343 return (freq); 344 } 345 346 uint32_t 347 mpc85xx_get_system_clock(void) 348 { 349 uint32_t freq; 350 351 freq = mpc85xx_get_platform_clock(); 352 353 return (freq / 2); 354 } 355