xref: /freebsd/sys/powerpc/mpc85xx/mpc85xx.c (revision f0cfa1b168014f56c02b83e5f28412cc5f78d117)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include "opt_platform.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/reboot.h>
38 #include <sys/rman.h>
39 
40 #include <vm/vm.h>
41 #include <vm/vm_param.h>
42 #include <vm/pmap.h>
43 
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/machdep.h>
47 #include <machine/pio.h>
48 #include <machine/spr.h>
49 
50 #include <dev/fdt/fdt_common.h>
51 
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55 #include <dev/ofw/openfirm.h>
56 
57 #include <powerpc/mpc85xx/mpc85xx.h>
58 
59 
60 /*
61  * MPC85xx system specific routines
62  */
63 
64 uint32_t
65 ccsr_read4(uintptr_t addr)
66 {
67 	volatile uint32_t *ptr = (void *)addr;
68 
69 	return (*ptr);
70 }
71 
72 void
73 ccsr_write4(uintptr_t addr, uint32_t val)
74 {
75 	volatile uint32_t *ptr = (void *)addr;
76 
77 	*ptr = val;
78 	powerpc_iomb();
79 }
80 
81 int
82 law_getmax(void)
83 {
84 	uint32_t ver;
85 	int law_max;
86 
87 	ver = SVR_VER(mfspr(SPR_SVR));
88 	switch (ver) {
89 	case SVR_MPC8555:
90 	case SVR_MPC8555E:
91 		law_max = 8;
92 		break;
93 	case SVR_MPC8533:
94 	case SVR_MPC8533E:
95 	case SVR_MPC8548:
96 	case SVR_MPC8548E:
97 		law_max = 10;
98 		break;
99 	case SVR_P5020:
100 	case SVR_P5020E:
101 	case SVR_P5021:
102 	case SVR_P5021E:
103 	case SVR_P5040:
104 	case SVR_P5040E:
105 		law_max = 32;
106 		break;
107 	default:
108 		law_max = 8;
109 	}
110 
111 	return (law_max);
112 }
113 
114 static inline void
115 law_write(uint32_t n, uint64_t bar, uint32_t sr)
116 {
117 
118 	if (mpc85xx_is_qoriq()) {
119 		ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
120 		ccsr_write4(OCP85XX_LAWBARL(n), bar);
121 		ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
122 		ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
123 	} else {
124 		ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
125 		ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
126 		ccsr_read4(OCP85XX_LAWSR_85XX(n));
127 	}
128 
129 	/*
130 	 * The last write to LAWAR should be followed by a read
131 	 * of LAWAR before any device try to use any of windows.
132 	 * What more the read of LAWAR should be followed by isync
133 	 * instruction.
134 	 */
135 
136 	isync();
137 }
138 
139 static inline void
140 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
141 {
142 
143 	if (mpc85xx_is_qoriq()) {
144 		*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
145 		    ccsr_read4(OCP85XX_LAWBARL(n));
146 		*sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
147 	} else {
148 		*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
149 		*sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
150 	}
151 }
152 
153 static int
154 law_find_free(void)
155 {
156 	uint32_t i,sr;
157 	uint64_t bar;
158 	int law_max;
159 
160 	law_max = law_getmax();
161 	/* Find free LAW */
162 	for (i = 0; i < law_max; i++) {
163 		law_read(i, &bar, &sr);
164 		if ((sr & 0x80000000) == 0)
165 			break;
166 	}
167 
168 	return (i);
169 }
170 
171 #define	_LAW_SR(trgt,size)	(0x80000000 | (trgt << 20) | \
172 				(flsl(size + (size - 1)) - 2))
173 
174 int
175 law_enable(int trgt, uint64_t bar, uint32_t size)
176 {
177 	uint64_t bar_tmp;
178 	uint32_t sr, sr_tmp;
179 	int i, law_max;
180 
181 	if (size == 0)
182 		return (0);
183 
184 	law_max = law_getmax();
185 	sr = _LAW_SR(trgt, size);
186 
187 	/* Bail if already programmed. */
188 	for (i = 0; i < law_max; i++) {
189 		law_read(i, &bar_tmp, &sr_tmp);
190 		if (sr == sr_tmp && bar == bar_tmp)
191 			return (0);
192 	}
193 
194 	/* Find an unused access window. */
195 	i = law_find_free();
196 
197 	if (i == law_max)
198 		return (ENOSPC);
199 
200 	law_write(i, bar, sr);
201 	return (0);
202 }
203 
204 int
205 law_disable(int trgt, uint64_t bar, uint32_t size)
206 {
207 	uint64_t bar_tmp;
208 	uint32_t sr, sr_tmp;
209 	int i, law_max;
210 
211 	law_max = law_getmax();
212 	sr = _LAW_SR(trgt, size);
213 
214 	/* Find and disable requested LAW. */
215 	for (i = 0; i < law_max; i++) {
216 		law_read(i, &bar_tmp, &sr_tmp);
217 		if (sr == sr_tmp && bar == bar_tmp) {
218 			law_write(i, 0, 0);
219 			return (0);
220 		}
221 	}
222 
223 	return (ENOENT);
224 }
225 
226 int
227 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
228 {
229 	u_long start;
230 	uint32_t ver;
231 	int trgt, rv;
232 
233 	ver = SVR_VER(mfspr(SPR_SVR));
234 
235 	start = rman_get_start(res) & 0xf000;
236 
237 	rv = 0;
238 	trgt = -1;
239 	switch (start) {
240 	case 0x0000:
241 	case 0x8000:
242 		trgt = 0;
243 		break;
244 	case 0x1000:
245 	case 0x9000:
246 		trgt = 1;
247 		break;
248 	case 0x2000:
249 	case 0xa000:
250 		if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
251 			trgt = 3;
252 		else
253 			trgt = 2;
254 		break;
255 	case 0x3000:
256 	case 0xb000:
257 		if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
258 			rv = EINVAL;
259 		else
260 			trgt = 3;
261 		break;
262 	default:
263 		rv = ENXIO;
264 	}
265 	if (rv == 0) {
266 		*trgt_mem = trgt;
267 		*trgt_io = trgt;
268 	}
269 	return (rv);
270 }
271 
272 static void
273 l3cache_inval(void)
274 {
275 
276 	/* Flash invalidate the CPC and clear all the locks */
277 	ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
278 	    OCP85XX_CPC_CSR0_LFC);
279 	while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
280 	    OCP85XX_CPC_CSR0_LFC))
281 		;
282 }
283 
284 static void
285 l3cache_enable(void)
286 {
287 
288 	ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
289 	    OCP85XX_CPC_CSR0_PE);
290 	/* Read back to sync write */
291 	ccsr_read4(OCP85XX_CPC_CSR0);
292 }
293 
294 void
295 mpc85xx_enable_l3_cache(void)
296 {
297 	uint32_t csr, size, ver;
298 
299 	/* Enable L3 CoreNet Platform Cache (CPC) */
300 	ver = SVR_VER(mfspr(SPR_SVR));
301 	if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
302 	    ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
303 		csr = ccsr_read4(OCP85XX_CPC_CSR0);
304 		if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
305 			l3cache_inval();
306 			l3cache_enable();
307 		}
308 
309 		csr = ccsr_read4(OCP85XX_CPC_CSR0);
310 		if ((boothowto & RB_VERBOSE) != 0 ||
311 		    (csr & OCP85XX_CPC_CSR0_CE) == 0) {
312 			size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
313 			printf("L3 Corenet Platform Cache: %d KB %sabled\n",
314 			    size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
315 			    "dis" : "en");
316 		}
317 	}
318 }
319 
320 int
321 mpc85xx_is_qoriq(void)
322 {
323 	uint16_t pvr = mfpvr() >> 16;
324 
325 	/* QorIQ register set is only in e500mc and derivative core based SoCs. */
326 	if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
327 		return (1);
328 
329 	return (0);
330 }
331 
332 static void
333 mpc85xx_dataloss_erratum_spr976(void)
334 {
335 	uint32_t svr = SVR_VER(mfspr(SPR_SVR));
336 
337 	/* Ignore whether it's the E variant */
338 	svr &= ~0x8;
339 
340 	if (svr != SVR_P3041 && svr != SVR_P4040 &&
341 	    svr != SVR_P4080 && svr != SVR_P5020)
342 		return;
343 
344 	mb();
345 	isync();
346 	mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
347 	isync();
348 }
349 
350 static vm_offset_t
351 mpc85xx_map_dcsr(void)
352 {
353 	phandle_t node;
354 	u_long b, s;
355 	int err;
356 
357 	/*
358 	 * Try to access the dcsr node directly i.e. through /aliases/.
359 	 */
360 	if ((node = OF_finddevice("dcsr")) != -1)
361 		if (fdt_is_compatible_strict(node, "fsl,dcsr"))
362 			goto moveon;
363 	/*
364 	 * Find the node the long way.
365 	 */
366 	if ((node = OF_finddevice("/")) == -1)
367 		return (0);
368 
369 	if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
370 		return (0);
371 
372 moveon:
373 	err = fdt_get_range(node, 0, &b, &s);
374 
375 	if (err != 0)
376 		return (0);
377 
378 	law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
379 	return pmap_early_io_map(b, 0x400000);
380 }
381 
382 
383 
384 void
385 mpc85xx_fix_errata(vm_offset_t va_ccsr)
386 {
387 	uint32_t svr = SVR_VER(mfspr(SPR_SVR));
388 	vm_offset_t va_dcsr;
389 
390 	/* Ignore whether it's the E variant */
391 	svr &= ~0x8;
392 
393 	if (svr != SVR_P3041 && svr != SVR_P4040 &&
394 	    svr != SVR_P4080 && svr != SVR_P5020)
395 		return;
396 
397 	if (mfmsr() & PSL_EE)
398 		return;
399 
400 	/*
401 	 * dcsr region need to be mapped thus patch can refer to.
402 	 * Align dcsr right after ccsbar.
403 	 */
404 	va_dcsr = mpc85xx_map_dcsr();
405 	if (va_dcsr == 0)
406 		goto err;
407 
408 	/*
409 	 * As A004510 errata specify, special purpose register 976
410 	 * SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
411 	 * does not document SPR976 register.
412 	 */
413 	mpc85xx_dataloss_erratum_spr976();
414 
415 	/*
416 	 * Specific settings in the CCF and core platform cache (CPC)
417 	 * are required to reconfigure the CoreNet coherency fabric.
418 	 * The register settings that should be updated are described
419 	 * in errata and relay on base address, offset and updated value.
420 	 * Special conditions must be used to update these registers correctly.
421 	 */
422 	dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
423 	dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
424 	dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
425 	dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
426 	dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
427 
428 	switch (svr) {
429 	case SVR_P5020:
430 		dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
431 		break;
432 	case SVR_P4040:
433 	case SVR_P4080:
434 		dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
435 		break;
436 	case SVR_P3041:
437 		dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
438 	}
439 	dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
440 	dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
441 
442 err:
443 	return;
444 }
445 
446 uint32_t
447 mpc85xx_get_platform_clock(void)
448 {
449 	phandle_t soc;
450 	static uint32_t freq;
451 
452 	if (freq != 0)
453 		return (freq);
454 
455 	soc = OF_finddevice("/soc");
456 
457 	/* freq isn't modified on error. */
458 	OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq));
459 
460 	return (freq);
461 }
462 
463 uint32_t
464 mpc85xx_get_system_clock(void)
465 {
466 	uint32_t freq;
467 
468 	freq = mpc85xx_get_platform_clock();
469 
470 	return (freq / 2);
471 }
472